lpc43xx_cgu.h

00001 /**
00002  * @file    lpc43xx_cgu.h
00003  * @brief   
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 /* Peripheral group ----------------------------------------------------------- */
00023 /** @defgroup CGU CGU (Clock Generation Unit)
00024  * @ingroup LPC4300CMSIS_FwLib_Drivers
00025  * @{
00026  */
00027 
00028 #ifndef lpc43xx_CGU_H_
00029 #define lpc43xx_CGU_H_
00030 
00031 /* Includes ------------------------------------------------------------------- */
00032 #include "LPC43xx.h"
00033 #include "lpc_types.h"
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 /* Private Macros -------------------------------------------------------------- */
00041 /** @defgroup CGU_Private_Macros CGU Private Macros
00042  * @{
00043  */
00044 
00045 /** Branch clocks from CGU_BASE_SAFE */
00046 #define CGU_ENTITY_NONE             CGU_ENTITY_NUM
00047 
00048 /** Check bit at specific position is clear or not */
00049 #define ISBITCLR(x,bit)             ((x&(1<<bit))^(1<<bit))
00050 /** Check bit at specific position is set or not */
00051 #define ISBITSET(x,bit)             (x&(1<<bit))
00052 /** Set mask */
00053 #define ISMASKSET(x,mask)           (x&mask)
00054 
00055 /** CGU number of clock source */
00056 #define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
00057 
00058 /*********************************************************************//**
00059  * Macro defines for CGU control mask bit definitions
00060  **********************************************************************/
00061 /** CGU control enable mask bit */
00062 #define CGU_CTRL_EN_MASK            1
00063 /** CGU control clock-source mask bit */
00064 #define CGU_CTRL_SRC_MASK           (0xF<<24)
00065 /** CGU control auto block mask bit */
00066 #define CGU_CTRL_AUTOBLOCK_MASK     (1<<11)
00067 
00068 /*********************************************************************//**
00069  * Macro defines for CGU PLL1 mask bit definitions
00070  **********************************************************************/
00071 /** CGU PLL1 feedback select mask bit */
00072 #define CGU_PLL1_FBSEL_MASK         (1<<6)
00073 /** CGU PLL1 Input clock bypass control mask bit */
00074 #define CGU_PLL1_BYPASS_MASK        (1<<1)
00075 /** CGU PLL1 direct CCO output mask bit */
00076 #define CGU_PLL1_DIRECT_MASK        (1<<7)
00077 
00078 /**
00079  * @}
00080  */
00081 
00082 /* Public Types --------------------------------------------------------------- */
00083 /** @defgroup CGU_Public_Types CGU Public Types
00084  * @{
00085  */
00086 
00087 /*********************************************************************//**
00088  * @brief CGU enumeration
00089  **********************************************************************/
00090 /*
00091  * @brief   CGU clock source enumerate definition
00092  */
00093 typedef enum {
00094     /* Clock Source */
00095     CGU_CLKSRC_32KHZ_OSC = 0,                   /**< 32KHz oscillator clock source  */
00096     CGU_CLKSRC_IRC,                             /**< IRC 12 Mhz clock source        */
00097     CGU_CLKSRC_ENET_RX_CLK,                     /**< Ethernet receive clock source  */
00098     CGU_CLKSRC_ENET_TX_CLK,                     /**< Ethernet transmit clock source */
00099     CGU_CLKSRC_GP_CLKIN,                        /**< General purpose clock source   */
00100     CGU_CLKSRC_TCK,                             /**< TCK clock source               */
00101     CGU_CLKSRC_XTAL_OSC,                        /**< Crystal oscillator clock source*/
00102     CGU_CLKSRC_PLL0,                            /**< PLL0 (USB0) clock source       */
00103     CGU_CLKSRC_PLL0_AUDIO,
00104     CGU_CLKSRC_PLL1,                            /**< PLL1 clock source              */
00105     CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,     /**< IDIVA clock source             */
00106     CGU_CLKSRC_IDIVB,                           /**< IDIVB clock source             */
00107     CGU_CLKSRC_IDIVC,                           /**< IDIVC clock source             */
00108     CGU_CLKSRC_IDIVD,                           /**< IDIVD clock source             */
00109     CGU_CLKSRC_IDIVE,                           /**< IDIVE clock source             */
00110 
00111     /* Base */
00112     CGU_BASE_SAFE,                              /**< Base save clock (always on) for WDT */
00113     CGU_BASE_USB0,                              /**< USB0 base clock                */
00114     CGU_BASE_PERIPH,                            /**  Peripheral bus (SGPIO)         */
00115     CGU_BASE_USB1,                              /**< USB1 base clock                */
00116     CGU_BASE_M4,                                /**< ARM Cortex-M4 Core base clock  */
00117     CGU_BASE_SPIFI,                             /**< SPIFI base clock               */
00118     CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2,                           /**< Ethernet PHY Rx base clock     */
00119     CGU_BASE_PHY_TX,                            /**< Ethernet PHY Tx base clock     */
00120     CGU_BASE_APB1,                              /**< APB peripheral block #1 base clock */
00121     CGU_BASE_APB3,                              /**< APB peripheral block #3 base clock */
00122     CGU_BASE_LCD,                               /**< LCD base clock                 */
00123     CGU_BASE_ENET_CSR,
00124     CGU_BASE_SDIO,                              /**< SDIO base clock                */
00125     CGU_BASE_SSP0,                              /**< SSP0 base clock                */
00126     CGU_BASE_SSP1,                              /**< SSP1 base clock                */
00127     CGU_BASE_UART0,                             /**< UART0 base clock               */
00128     CGU_BASE_UART1,                             /**< UART1 base clock               */
00129     CGU_BASE_UART2,                             /**< UART2 base clock               */
00130     CGU_BASE_UART3,                             /**< UART3 base clock               */
00131     CGU_BASE_CLKOUT,                            /**< CLKOUT base clock              */
00132     CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
00133     CGU_BASE_OUT0,
00134     CGU_BASE_OUT1,
00135     CGU_ENTITY_NUM                              /**< Number or clock source entity  */
00136 } CGU_ENTITY_T;
00137 
00138 /*
00139  * @brief   CGU PPL0 mode enumerate definition
00140  */
00141 typedef enum {
00142     CGU_PLL0_MODE_1d = 0,
00143     CGU_PLL0_MODE_1c,
00144     CGU_PLL0_MODE_1b,
00145     CGU_PLL0_MODE_1a
00146 } CGU_PLL0_MODE;
00147 
00148 /*
00149  * @brief   CGU peripheral enumerate definition
00150  */
00151 typedef enum {
00152     CGU_PERIPHERAL_ADC0 = 0,                    /**< ADC0       */
00153     CGU_PERIPHERAL_ADC1,                        /**< ADC1       */
00154     CGU_PERIPHERAL_AES,                         /**< AES        */
00155 //  CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
00156     CGU_PERIPHERAL_APB1_BUS,                    /**< APB1 bus           */
00157     CGU_PERIPHERAL_APB3_BUS,                    /**< APB3 bus           */
00158     CGU_PERIPHERAL_CAN,                         /**< CAN                */
00159     CGU_PERIPHERAL_CREG,                        /**< CREG               */
00160     CGU_PERIPHERAL_DAC,                         /**< DAC                */
00161     CGU_PERIPHERAL_DMA,                         /**< DMA                */
00162     CGU_PERIPHERAL_EMC,                         /**< EMC                */
00163     CGU_PERIPHERAL_ETHERNET,                    /**< Ethernet           */
00164     CGU_PERIPHERAL_ETHERNET_TX, //HIDE          /**< Ethernet transmit  */
00165     CGU_PERIPHERAL_GPIO,                        /**< GPIO               */
00166     CGU_PERIPHERAL_I2C0,                        /**< I2C0               */
00167     CGU_PERIPHERAL_I2C1,                        /**< I2C1               */
00168     CGU_PERIPHERAL_I2S,                         /**< I2S                */
00169     CGU_PERIPHERAL_LCD,                         /**< LCD                */
00170     CGU_PERIPHERAL_M4CORE,                      /**< ARM Cortex-M4 Core */
00171     CGU_PERIPHERAL_M4_BUS,                      /**< ARM Cortex-M4 Bus  */
00172     CGU_PERIPHERAL_MOTOCON,                     /**< Motor Control      */
00173     CGU_PERIPHERAL_QEI,                         /**< QEI                */
00174     CGU_PERIPHERAL_RITIMER,                     /**< RIT Timer          */
00175     CGU_PERIPHERAL_SCT,                         /**< SCT                */
00176     CGU_PERIPHERAL_SCU,                         /**< SCU                */
00177     CGU_PERIPHERAL_SDIO,                        /**< SDIO               */
00178     CGU_PERIPHERAL_SPIFI,                       /**< SPIFI              */
00179     CGU_PERIPHERAL_SSP0,                        /**< SSP0               */
00180     CGU_PERIPHERAL_SSP1,                        /**< SSP1               */
00181     CGU_PERIPHERAL_TIMER0,                      /**< TIMER 0            */
00182     CGU_PERIPHERAL_TIMER1,                      /**< TIMER 1            */
00183     CGU_PERIPHERAL_TIMER2,                      /**< TIMER 2            */
00184     CGU_PERIPHERAL_TIMER3,                      /**< TIMER 3            */
00185     CGU_PERIPHERAL_UART0,                       /**< UART0              */
00186     CGU_PERIPHERAL_UART1,                       /**< UART1              */
00187     CGU_PERIPHERAL_UART2,                       /**< UART2              */
00188     CGU_PERIPHERAL_UART3,                       /**< UART3              */
00189     CGU_PERIPHERAL_USB0,                        /**< USB0               */
00190     CGU_PERIPHERAL_USB1,                        /**< USB1               */
00191     CGU_PERIPHERAL_WWDT,                        /**< WWDT               */
00192     CGU_PERIPHERAL_NUM
00193 } CGU_PERIPHERAL_T ;
00194 
00195 /**
00196  *  @brief  CGU error status enumerate definition
00197  */
00198 typedef enum {
00199     CGU_ERROR_SUCCESS = 0,
00200     CGU_ERROR_CONNECT_TOGETHER,
00201     CGU_ERROR_INVALID_ENTITY,
00202     CGU_ERROR_INVALID_CLOCK_SOURCE,
00203     CGU_ERROR_INVALID_PARAM,
00204     CGU_ERROR_FREQ_OUTOF_RANGE
00205 } CGU_ERROR;
00206 
00207 /********************************************************************//**
00208 * @brief CGU structure definitions
00209 **********************************************************************/
00210 /*
00211  * @brief   CGU peripheral clock structure
00212  */
00213 typedef struct {
00214     uint8_t RegBaseEntity;                      /**< Base register address      */
00215     uint16_t RegBranchOffset;                   /**< Branch register offset     */
00216     uint8_t PerBaseEntity;                      /**< Base peripheral address    */
00217     uint16_t PerBranchOffset;                   /**< Base peripheral offset     */
00218     uint8_t next;                               /**< Pointer to next structure  */
00219 } CGU_PERIPHERAL_S;
00220 
00221 /**
00222  * @}
00223  */
00224 
00225 
00226 /* Public Functions ----------------------------------------------------------- */
00227 /** @defgroup CGU_Public_Functions CGU Public Functions
00228  * @{
00229  */
00230 
00231 /** Clock generate initialize/de-initialize */
00232 uint32_t    CGU_Init(uint32_t wantedFreq);
00233 uint32_t    CGU_DeInit(void);
00234 
00235 /** Clock Generator and Clock Control */
00236 uint32_t    CGU_ConfigPWR(CGU_PERIPHERAL_T  PPType, FunctionalState en);
00237 uint32_t    CGU_GetPCLKFrequency(CGU_PERIPHERAL_T  Clock);
00238 
00239 /** Clock Source and Base Clock operation */
00240 uint32_t    CGU_SetXTALOSC(uint32_t ClockFrequency);
00241 uint32_t    CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
00242 uint32_t    CGU_SetPLL0(void);
00243 uint32_t    CGU_SetPLL0audio(void);
00244 uint32_t    CGU_SetPLL1(uint32_t mult);
00245 uint32_t    CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
00246 uint32_t    CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
00247 uint32_t    CGU_GetBaseStatus(CGU_ENTITY_T Base);
00248 void        CGU_UpdateClock(void);
00249 uint32_t    CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
00250 
00251 /**
00252  * @}
00253  */
00254 
00255 
00256 #ifdef __cplusplus
00257 }
00258 #endif
00259 
00260 #endif /* lpc43xx_CGU_H_ */
00261 
00262 /**
00263  * @}
00264  */
00265