CGU Public Functions
[CGU (Clock Generation Unit)]

Clock Generator and Clock Control.

Clock Generator and Clock Control.

Parameters:

[in]	PPType	peripheral type, should be: CGU_PERIPHERAL_ADC0 :ADC0 CGU_PERIPHERAL_ADC1 :ADC1 CGU_PERIPHERAL_AES :AES CGU_PERIPHERAL_APB1_BUS :APB1 bus CGU_PERIPHERAL_APB3_BUS :APB3 bus CGU_PERIPHERAL_CAN :CAN CGU_PERIPHERAL_CREG :CREG CGU_PERIPHERAL_DAC :DAC CGU_PERIPHERAL_DMA :DMA CGU_PERIPHERAL_EMC :EMC CGU_PERIPHERAL_ETHERNET :ETHERNET CGU_PERIPHERAL_GPIO :GPIO CGU_PERIPHERAL_I2C0 :I2C0 CGU_PERIPHERAL_I2C1 :I2C1 CGU_PERIPHERAL_I2S :I2S CGU_PERIPHERAL_LCD :LCD CGU_PERIPHERAL_M3CORE :M3 core CGU_PERIPHERAL_M3_BUS :M3 bus CGU_PERIPHERAL_MOTOCON :Motor control CGU_PERIPHERAL_QEI :QEI CGU_PERIPHERAL_RITIMER :RIT timer CGU_PERIPHERAL_SCT :SCT CGU_PERIPHERAL_SCU :SCU CGU_PERIPHERAL_SDIO :SDIO CGU_PERIPHERAL_SPIFI :SPIFI CGU_PERIPHERAL_SSP0 :SSP0 CGU_PERIPHERAL_SSP1 :SSP1 CGU_PERIPHERAL_TIMER0 :TIMER0 CGU_PERIPHERAL_TIMER1 :TIMER1 CGU_PERIPHERAL_TIMER2 :TIMER2 CGU_PERIPHERAL_TIMER3 :TIMER3 CGU_PERIPHERAL_UART0 :UART0 CGU_PERIPHERAL_UART1 :UART1 CGU_PERIPHERAL_UART2 :UART2 CGU_PERIPHERAL_UART3 :UART3 CGU_PERIPHERAL_USB0 :USB0 CGU_PERIPHERAL_USB1 :USB1 CGU_PERIPHERAL_WWDT :WWDT
[in]	en	status, should be: ENABLE: Enable power DISABLE: Disable power

Returns:

Configure status, could be:

• CGU_ERROR_SUCCESS: successful
• Other: error

Definition at line 329 of file lpc43xx_cgu.c.

Enable clock entity.

Parameters:

[in]	ClockEntity	Clock entity, should be: CGU_CLKSRC_32KHZ_OSC :32Khz oscillator CGU_CLKSRC_IRC :IRC clock CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock CGU_CLKSRC_GP_CLKIN :General purpose input clock CGU_CLKSRC_XTAL_OSC :Crystal oscillator CGU_CLKSRC_PLL0 :PLL0 clock CGU_CLKSRC_PLL1 :PLL1 clock CGU_CLKSRC_IDIVA :Integer divider register A CGU_CLKSRC_IDIVB :Integer divider register B CGU_CLKSRC_IDIVC :Integer divider register C CGU_CLKSRC_IDIVD :Integer divider register D CGU_CLKSRC_IDIVE :Integer divider register E CGU_BASE_SAFE :Base safe clock (always on)for WDT CGU_BASE_USB0 :Base clock for USB0 CGU_BASE_PERIPH :Base clock for Peripheral bus CGU_BASE_USB1 :Base clock for USB1 CGU_BASE_M4 :System base clock for ARM Cortex-M3 core and APB peripheral blocks #0 and #2 CGU_BASE_SPIFI :Base clock for SPIFI CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx CGU_BASE_APB1 :Base clock for APB peripheral block #1 CGU_BASE_APB3 :Base clock for APB peripheral block #3 CGU_BASE_LCD :Base clock for LCD CGU_BASE_SDIO :Base clock for SDIO card reader CGU_BASE_SSP0 :Base clock for SSP0 CGU_BASE_SSP1 :Base clock for SSP1 CGU_BASE_UART0 :Base clock for UART0 CGU_BASE_UART1 :Base clock for UART1 CGU_BASE_UART2 :Base clock for UART2 CGU_BASE_UART3 :Base clock for UART3 CGU_BASE_CLKOUT :Base clock for CLKOUT pin
[in]	en	status, should be: ENABLE: Enable power DISABLE: Disable power

Returns:

Setting status, could be:

• CGU_ERROR_SUCCESS: successful
• CGU_ERROR_INVALID_ENTITY: Invalid entity

Definition at line 637 of file lpc43xx_cgu.c.

Connect entity clock source.

Parameters:

[in]	ClockSource	Clock source, should be: CGU_CLKSRC_32KHZ_OSC :32Khz oscillator CGU_CLKSRC_IRC :IRC clock CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock CGU_CLKSRC_GP_CLKIN :General purpose input clock CGU_CLKSRC_XTAL_OSC :Crystal oscillator CGU_CLKSRC_PLL0 :PLL0 clock CGU_CLKSRC_PLL1 :PLL1 clock CGU_CLKSRC_IDIVA :Integer divider register A CGU_CLKSRC_IDIVB :Integer divider register B CGU_CLKSRC_IDIVC :Integer divider register C CGU_CLKSRC_IDIVD :Integer divider register D CGU_CLKSRC_IDIVE :Integer divider register E
[in]	ClockEntity	Clock entity, should be: CGU_CLKSRC_PLL0 :PLL0 clock CGU_CLKSRC_PLL1 :PLL1 clock CGU_CLKSRC_IDIVA :Integer divider register A CGU_CLKSRC_IDIVB :Integer divider register B CGU_CLKSRC_IDIVC :Integer divider register C CGU_CLKSRC_IDIVD :Integer divider register D CGU_CLKSRC_IDIVE :Integer divider register E CGU_BASE_SAFE :Base safe clock (always on)for WDT CGU_BASE_USB0 :Base clock for USB0 CGU_BASE_USB1 :Base clock for USB1 CGU_BASE_M4 :System base clock for ARM Cortex-M3 core and APB peripheral blocks #0 and #2 CGU_BASE_SPIFI :Base clock for SPIFI CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx CGU_BASE_APB1 :Base clock for APB peripheral block #1 CGU_BASE_APB3 :Base clock for APB peripheral block #3 CGU_BASE_LCD :Base clock for LCD CGU_BASE_SDIO :Base clock for SDIO card reader CGU_BASE_SSP0 :Base clock for SSP0 CGU_BASE_SSP1 :Base clock for SSP1 CGU_BASE_UART0 :Base clock for UART0 CGU_BASE_UART1 :Base clock for UART1 CGU_BASE_UART2 :Base clock for UART2 CGU_BASE_UART3 :Base clock for UART3 CGU_BASE_CLKOUT :Base clock for CLKOUT pin

Returns:

Setting status, could be:

• CGU_ERROR_SUCCESS: successful
• CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together
• CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error
• CGU_ERROR_INVALID_ENTITY: Invalid entity error

Definition at line 758 of file lpc43xx_cgu.c.

Get current base status.

Parameters:

[in]

Base

Base type, should be: CGU_BASE_USB0 :Base clock for USB0 CGU_BASE_USB1 :Base clock for USB1 CGU_BASE_M4 :System base clock for ARM Cortex-M3 core and APB peripheral blocks #0 and #2 CGU_BASE_SPIFI :Base clock for SPIFI CGU_BASE_APB1 :Base clock for APB peripheral block #1 CGU_BASE_APB3 :Base clock for APB peripheral block #3 CGU_BASE_SDIO :Base clock for SDIO card reader CGU_BASE_SSP0 :Base clock for SSP0 CGU_BASE_SSP1 :Base clock for SSP1 CGU_BASE_UART0 :Base clock for UART0 CGU_BASE_UART1 :Base clock for UART1 CGU_BASE_UART2 :Base clock for UART2 CGU_BASE_UART3 :Base clock for UART3

Returns:

Always return 0

Definition at line 931 of file lpc43xx_cgu.c.

Get peripheral clock frequency.

Parameters:

[in]

Clock

Peripheral type, should be: CGU_PERIPHERAL_ADC0 :ADC0 CGU_PERIPHERAL_ADC1 :ADC1 CGU_PERIPHERAL_AES :AES CGU_PERIPHERAL_APB1_BUS :APB1 bus CGU_PERIPHERAL_APB3_BUS :APB3 bus CGU_PERIPHERAL_CAN :CAN CGU_PERIPHERAL_CREG :CREG CGU_PERIPHERAL_DAC :DAC CGU_PERIPHERAL_DMA :DMA CGU_PERIPHERAL_EMC :EMC CGU_PERIPHERAL_ETHERNET :ETHERNET CGU_PERIPHERAL_GPIO :GPIO CGU_PERIPHERAL_I2C0 :I2C0 CGU_PERIPHERAL_I2C1 :I2C1 CGU_PERIPHERAL_I2S :I2S CGU_PERIPHERAL_LCD :LCD CGU_PERIPHERAL_M3CORE :M3 core CGU_PERIPHERAL_M3_BUS :M3 bus CGU_PERIPHERAL_MOTOCON :Motor control CGU_PERIPHERAL_QEI :QEI CGU_PERIPHERAL_RITIMER :RIT timer CGU_PERIPHERAL_SCT :SCT CGU_PERIPHERAL_SCU :SCU CGU_PERIPHERAL_SDIO :SDIO CGU_PERIPHERAL_SPIFI :SPIFI CGU_PERIPHERAL_SSP0 :SSP0 CGU_PERIPHERAL_SSP1 :SSP1 CGU_PERIPHERAL_TIMER0 :TIMER0 CGU_PERIPHERAL_TIMER1 :TIMER1 CGU_PERIPHERAL_TIMER2 :TIMER2 CGU_PERIPHERAL_TIMER3 :TIMER3 CGU_PERIPHERAL_UART0 :UART0 CGU_PERIPHERAL_UART1 :UART1 CGU_PERIPHERAL_UART2 :UART2 CGU_PERIPHERAL_UART3 :UART3 CGU_PERIPHERAL_USB0 :USB0 CGU_PERIPHERAL_USB1 :USB1 CGU_PERIPHERAL_WWDT :WWDT

Returns:

Return frequently value

Definition at line 447 of file lpc43xx_cgu.c.

Clock generate initialize/de-initialize.

Clock generate initialize/de-initialize.

Parameters:

[in]

None

Returns:

Initialize status, could be:

• CGU_ERROR_SUCCESS: successful
• Other: error

Definition at line 239 of file lpc43xx_cgu.c.

Compare one source clock to another source clock.

Parameters:

[in]	Clock	Clock entity that will be compared to second source, should be: CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock CGU_CLKSRC_GP_CLKIN :General purpose input clock CGU_CLKSRC_XTAL_OSC :Crystal oscillator CGU_CLKSRC_PLL0 :PLL0 clock CGU_CLKSRC_PLL1 :PLL1 clock CGU_CLKSRC_IDIVA :Integer divider register A CGU_CLKSRC_IDIVB :Integer divider register B CGU_CLKSRC_IDIVC :Integer divider register C CGU_CLKSRC_IDIVD :Integer divider register D CGU_CLKSRC_IDIVE :Integer divider register E CGU_BASE_SAFE :Base safe clock (always on)for WDT CGU_BASE_USB0 :Base clock for USB0 CGU_BASE_USB1 :Base clock for USB1 CGU_BASE_M4 :System base clock for ARM Cortex-M3 core and APB peripheral blocks #0 and #2 CGU_BASE_SPIFI :Base clock for SPIFI CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx CGU_BASE_APB1 :Base clock for APB peripheral block #1 CGU_BASE_APB3 :Base clock for APB peripheral block #3 CGU_BASE_LCD :Base clock for LCD CGU_BASE_SDIO :Base clock for SDIO card reader CGU_BASE_SSP0 :Base clock for SSP0 CGU_BASE_SSP1 :Base clock for SSP1 CGU_BASE_UART0 :Base clock for UART0 CGU_BASE_UART1 :Base clock for UART1 CGU_BASE_UART2 :Base clock for UART2 CGU_BASE_UART3 :Base clock for UART3 CGU_BASE_CLKOUT :Base clock for CLKOUT pin
[in]	CompareToClock	Clock source that to be compared to first source, should be different to first source.
[in]	m	Multiple value pointer
[in]	d	Divider value pointer

Returns:

Compare status, could be:

• (-1): fail
• 0: successful

Note:

Formula used to compare: FClock = m*FCompareToClock/d

Definition at line 1115 of file lpc43xx_cgu.c.

Set clock divider.

Parameters:

[in]	SelectDivider	Clock source, should be: CGU_CLKSRC_IDIVA :Integer divider register A CGU_CLKSRC_IDIVB :Integer divider register B CGU_CLKSRC_IDIVC :Integer divider register C CGU_CLKSRC_IDIVD :Integer divider register D CGU_CLKSRC_IDIVE :Integer divider register E
[in]	divisor	Divisor value, should be: 0..255

Returns:

Setting status, could be:

• CGU_ERROR_SUCCESS: successful
• CGU_ERROR_INVALID_ENTITY: Invalid entity

Definition at line 572 of file lpc43xx_cgu.c.

Get current USB PLL clock from XTAL.

Parameters:

[in]

None

Returns:

Returned clock value

Definition at line 808 of file lpc43xx_cgu.c.

Get current Audio PLL clock from XTAL.

Parameters:

[in]

None

Returns:

Returned clock value

Definition at line 827 of file lpc43xx_cgu.c.

Setting PLL1.

Parameters:

[in]

mult

Multiple value

Returns:

Setting status, could be:

• CGU_ERROR_SUCCESS: successful
• CGU_ERROR_INVALID_PARAM: Invalid parameter error

Definition at line 873 of file lpc43xx_cgu.c.

Clock Source and Base Clock operation.

Clock Source and Base Clock operation.

Parameters:

[in]

ClockFrequency

XTAL Frequency value

Returns:

Setting status, could be:

• CGU_ERROR_SUCCESS: successful
• CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range

Definition at line 541 of file lpc43xx_cgu.c.

Update clock.

Parameters:

[in]

None

Returns:

None

Definition at line 491 of file lpc43xx_cgu.c.