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Timer Registers
Hardware interface definitions for the Timer Peripheral. More...
Data Structures | |
| struct | mxc_tmr_regs_t |
| Structure type to access the Timer Registers, see MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure. More... | |
Modules | |
| Register Offsets | |
Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and MXC_CFG_TMR_INSTANCES for the . | |
| TMR_CTRL Register | |
Field Positions and Bit Masks for the TMR_CTRL register. | |
| TMR_COUNT16_0 Register | |
Field Positions and Bit Masks for the TMR_COUNT16_0 register. | |
| TMR_TERM_CNT16_0 Register | |
Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. | |
| _TMR_COUNT16_1_ Register | |
Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. | |
| TMR_TERM_CNT16_1 Register | |
Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. | |
| TMR_INTFL Register | |
Field Positions and Bit Masks for the TMR_INTFL register. | |
| TMR_INTEN Register | |
Field Positions and Bit Masks for the TMR_INTEN register. | |
Detailed Description
Hardware interface definitions for the Timer Peripheral.
Definitions for the Hardware Access Layer of the Timer Peripherals. Includes:
- Registers
- Fields
- Positions
- Values
- Masks
Generated on Tue Jul 12 2022 15:37:31 by
1.7.2