gpio.c

00001 /**
00002  * @file    gpio.c
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * Copyright (c) 2016-2017 NXP
00008  * SPDX-License-Identifier: Apache-2.0
00009  *
00010  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00011  * not use this file except in compliance with the License.
00012  * You may obtain a copy of the License at
00013  *
00014  * http://www.apache.org/licenses/LICENSE-2.0
00015  *
00016  * Unless required by applicable law or agreed to in writing, software
00017  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00018  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00019  * See the License for the specific language governing permissions and
00020  * limitations under the License.
00021  */
00022 
00023 #include "fsl_device_registers.h"
00024 #include "DAP_config.h"
00025 #include "gpio.h"
00026 #include "daplink.h"
00027 #include "hic_init.h"
00028 #include "fsl_clock.h "
00029 
00030 static void busy_wait(uint32_t cycles)
00031 {
00032     volatile uint32_t i = cycles;
00033     while (i > 0) {
00034         i--;
00035     }
00036 }
00037 
00038 void gpio_init(void)
00039 {
00040     // Enable hardfault on unaligned access for the interface only.
00041     // If this is done in the bootloader than then it might (will) break
00042     // older application firmware or firmware from 3rd party vendors.
00043 #if  defined(DAPLINK_IF)
00044     SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
00045 #endif
00046     // enable clock to ports
00047     SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
00048     SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
00049     // configure pin as GPIO
00050     LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1);
00051     // led off - enable output
00052     LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT;
00053     LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT;
00054     // led on
00055     LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT;
00056     // reset button configured as gpio input
00057     PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET;
00058     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1);
00059     /* Enable LVLRST_EN */
00060     PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1)  |  /* GPIO */
00061             PORT_PCR_ODE_MASK;  /* Open-drain */
00062     PIN_nRESET_EN_GPIO->PSOR  = PIN_nRESET_EN;
00063     PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN;
00064     // Configure SWO UART RX.
00065     PIN_SWO_RX_PORT->PCR[PIN_SWO_RX_BIT] = PORT_PCR_MUX(3); // UART1
00066     PIN_SWO_RX_GPIO->PDDR &= ~(1 << PIN_SWO_RX_BIT); // Input
00067 
00068     // Enable pulldowns on power monitor control signals to reduce power consumption.
00069     PIN_CTRL0_PORT->PCR[PIN_CTRL0_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
00070     PIN_CTRL1_PORT->PCR[PIN_CTRL1_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
00071     PIN_CTRL2_PORT->PCR[PIN_CTRL2_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
00072     PIN_CTRL3_PORT->PCR[PIN_CTRL3_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
00073 
00074     // Enable pulldown on GPIO0_B to prevent it floating.
00075     PIN_GPIO0_B_PORT->PCR[PIN_GPIO0_B_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
00076 
00077     // configure power enable pin as GPIO
00078     PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
00079     // set output to 0
00080     PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
00081     // switch gpio to output
00082     PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN;
00083 
00084     // Let the voltage rails stabilize.  This is especailly important
00085     // during software resets, since the target's 3.3v rail can take
00086     // 20-50ms to drain.  During this time the target could be driving
00087     // the reset pin low, causing the bootloader to think the reset
00088     // button is pressed.
00089     // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
00090     busy_wait(1000000);
00091 }
00092 
00093 void gpio_set_board_power(bool powerEnabled)
00094 {
00095     if (powerEnabled) {
00096         // enable power switch
00097         PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN;
00098     }
00099     else {
00100         // disable power switch
00101         PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
00102     }
00103 }
00104 
00105 uint32_t UART1_GetFreq(void)
00106 {
00107     return CLOCK_GetCoreSysClkFreq();
00108 }
00109 
00110 void UART1_InitPins(void)
00111 {
00112     // RX pin inited in gpio_init();
00113     // TX not used.
00114 }
00115 
00116 void UART1_DeinitPins(void)
00117 {
00118     // No need to deinit the RX pin.
00119     // TX not used.
00120 }
00121 
00122 void gpio_set_hid_led(gpio_led_state_t state)
00123 {
00124     if (state) {
00125         LED_CONNECTED_GPIO->PCOR = LED_CONNECTED; // LED on
00126     } else {
00127         LED_CONNECTED_GPIO->PSOR = LED_CONNECTED; // LED off
00128     }
00129 }
00130 
00131 void gpio_set_cdc_led(gpio_led_state_t state)
00132 {
00133     gpio_set_hid_led(state);
00134 }
00135 
00136 void gpio_set_msc_led(gpio_led_state_t state)
00137 {
00138     gpio_set_hid_led(state);
00139 }
00140 
00141 uint8_t gpio_get_reset_btn_no_fwrd(void)
00142 {
00143     return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1;
00144 }
00145 
00146 uint8_t gpio_get_reset_btn_fwrd(void)
00147 {
00148     return 0;
00149 }