uart.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_UART_COMPONENT_
00031 #define _SAM3U_UART_COMPONENT_
00032 
00033 /* ============================================================================= */
00034 /**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
00035 /* ============================================================================= */
00036 /** \addtogroup SAM3U_UART Universal Asynchronous Receiver Transmitter */
00037 /*@{*/
00038 
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040 /** \brief Uart hardware registers */
00041 typedef struct {
00042   WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
00043   RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
00044   WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
00045   WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
00046   RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
00047   RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
00048   RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
00049   WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
00050   RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
00051   RoReg Reserved1[55];
00052   RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
00053   RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
00054   RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
00055   RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
00056   RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
00057   RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
00058   RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
00059   RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
00060   WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
00061   RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
00062 } Uart;
00063 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00064 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
00065 #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
00066 #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
00067 #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
00068 #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
00069 #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
00070 #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
00071 #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
00072 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
00073 #define UART_MR_PAR_Pos 9
00074 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
00075 #define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
00076 #define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
00077 #define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
00078 #define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
00079 #define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
00080 #define UART_MR_CHMODE_Pos 14
00081 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
00082 #define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
00083 #define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
00084 #define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
00085 #define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
00086 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
00087 #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
00088 #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
00089 #define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
00090 #define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
00091 #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
00092 #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
00093 #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
00094 #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
00095 #define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
00096 #define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
00097 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
00098 #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
00099 #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
00100 #define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
00101 #define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
00102 #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
00103 #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
00104 #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
00105 #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
00106 #define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
00107 #define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
00108 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
00109 #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
00110 #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
00111 #define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
00112 #define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
00113 #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
00114 #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
00115 #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
00116 #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
00117 #define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
00118 #define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
00119 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
00120 #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
00121 #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
00122 #define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
00123 #define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
00124 #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
00125 #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
00126 #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
00127 #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
00128 #define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
00129 #define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
00130 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
00131 #define UART_RHR_RXCHR_Pos 0
00132 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
00133 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
00134 #define UART_THR_TXCHR_Pos 0
00135 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
00136 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
00137 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
00138 #define UART_BRGR_CD_Pos 0
00139 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
00140 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
00141 /* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
00142 #define UART_RPR_RXPTR_Pos 0
00143 #define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
00144 #define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
00145 /* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
00146 #define UART_RCR_RXCTR_Pos 0
00147 #define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
00148 #define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
00149 /* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
00150 #define UART_TPR_TXPTR_Pos 0
00151 #define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
00152 #define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
00153 /* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
00154 #define UART_TCR_TXCTR_Pos 0
00155 #define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
00156 #define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
00157 /* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
00158 #define UART_RNPR_RXNPTR_Pos 0
00159 #define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
00160 #define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
00161 /* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
00162 #define UART_RNCR_RXNCTR_Pos 0
00163 #define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
00164 #define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
00165 /* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
00166 #define UART_TNPR_TXNPTR_Pos 0
00167 #define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
00168 #define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
00169 /* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
00170 #define UART_TNCR_TXNCTR_Pos 0
00171 #define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
00172 #define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
00173 /* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
00174 #define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
00175 #define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
00176 #define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
00177 #define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
00178 /* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
00179 #define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
00180 #define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
00181 
00182 /*@}*/
00183 
00184 
00185 #endif /* _SAM3U_UART_COMPONENT_ */