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M480.h
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00001 /**************************************************************************//** 00002 * @file M480.h 00003 * @version V1.00 00004 * @brief M480 peripheral access layer header file. 00005 * This file contains all the peripheral register's definitions, 00006 * bits definitions and memory mapping for NuMicro M480 MCU. 00007 * 00008 * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. 00009 * 00010 * Redistribution and use in source and binary forms, with or without modification, 00011 * are permitted provided that the following conditions are met: 00012 * 1. Redistributions of source code must retain the above copyright notice, 00013 * this list of conditions and the following disclaimer. 00014 * 2. Redistributions in binary form must reproduce the above copyright notice, 00015 * this list of conditions and the following disclaimer in the documentation 00016 * and/or other materials provided with the distribution. 00017 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 00018 * may be used to endorse or promote products derived from this software 00019 * without specific prior written permission. 00020 * 00021 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00022 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00023 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00024 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00025 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00026 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00027 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00028 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00029 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00031 *****************************************************************************/ 00032 /** 00033 \mainpage NuMicro M480 Driver Reference Guide 00034 * 00035 * <b>Introduction</b> 00036 * 00037 * This user manual describes the usage of M480 Series MCU device driver 00038 * 00039 * <b>Disclaimer</b> 00040 * 00041 * The Software is furnished "AS IS", without warranty as to performance or results, and 00042 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all 00043 * warranties, express, implied or otherwise, with regard to the Software, its use, or 00044 * operation, including without limitation any and all warranties of merchantability, fitness 00045 * for a particular purpose, and non-infringement of intellectual property rights. 00046 * 00047 * <b>Important Notice</b> 00048 * 00049 * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, 00050 * any malfunction or failure of which may cause loss of human life, bodily injury or severe 00051 * property damage. Such applications are deemed, "Insecure Usage". 00052 * 00053 * Insecure usage includes, but is not limited to: equipment for surgical implementation, 00054 * atomic energy control instruments, airplane or spaceship instruments, the control or 00055 * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal 00056 * instruments, all types of safety devices, and other applications intended to support or 00057 * sustain life. 00058 * 00059 * All Insecure Usage shall be made at customer's risk, and in the event that third parties 00060 * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify 00061 * the damages and liabilities thus incurred by Nuvoton. 00062 * 00063 * Please note that all data and specifications are subject to change without notice. All the 00064 * trademarks of products and companies mentioned in this datasheet belong to their respective 00065 * owners. 00066 * 00067 * <b>Copyright Notice</b> 00068 * 00069 * Copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. 00070 */ 00071 #ifndef __M480_H__ 00072 #define __M480_H__ 00073 00074 #ifdef __cplusplus 00075 extern "C" { 00076 #endif 00077 00078 /******************************************************************************/ 00079 /* Processor and Core Peripherals */ 00080 /******************************************************************************/ 00081 /** @addtogroup CMSIS_Device Device CMSIS Definitions 00082 Configuration of the Cortex-M4 Processor and Core Peripherals 00083 @{ 00084 */ 00085 00086 /** 00087 * @details Interrupt Number Definition. 00088 */ 00089 typedef enum IRQn { 00090 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ 00091 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00092 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 00093 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 00094 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 00095 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 00096 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 00097 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 00098 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 00099 00100 /****** M480 Specific Interrupt Numbers ********************************************************/ 00101 00102 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ 00103 IRC_IRQn = 1, /*!< Internal RC Interrupt */ 00104 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ 00105 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ 00106 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ 00107 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ 00108 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ 00109 WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ 00110 WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ 00111 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ 00112 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ 00113 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ 00114 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ 00115 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ 00116 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ 00117 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ 00118 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ 00119 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ 00120 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ 00121 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ 00122 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ 00123 QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ 00124 SPI0_IRQn = 23, /*!< SPI0 Interrupt */ 00125 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ 00126 EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ 00127 EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ 00128 EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ 00129 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ 00130 EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ 00131 EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ 00132 EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ 00133 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ 00134 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ 00135 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ 00136 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ 00137 UART0_IRQn = 36, /*!< UART 0 Interrupt */ 00138 UART1_IRQn = 37, /*!< UART 1 Interrupt */ 00139 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ 00140 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ 00141 PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */ 00142 DAC_IRQn = 41, /*!< DAC Interrupt */ 00143 ADC0_IRQn = 42, /*!< ADC0 Interrupt */ 00144 ADC1_IRQn = 43, /*!< ADC1 Interrupt */ 00145 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ 00146 ADC2_IRQn = 46, /*!< ADC2 Interrupt */ 00147 ADC3_IRQn = 47, /*!< ADC3 Interrupt */ 00148 UART2_IRQn = 48, /*!< UART2 Interrupt */ 00149 UART3_IRQn = 49, /*!< UART3 Interrupt */ 00150 SPI1_IRQn = 51, /*!< SPI1 Interrupt */ 00151 SPI2_IRQn = 52, /*!< SPI2 Interrupt */ 00152 USBD_IRQn = 53, /*!< USB device Interrupt */ 00153 USBH_IRQn = 54, /*!< USB host Interrupt */ 00154 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ 00155 CAN0_IRQn = 56, /*!< CAN0 Interrupt */ 00156 CAN1_IRQn = 57, /*!< CAN1 Interrupt */ 00157 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ 00158 SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ 00159 SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ 00160 SPI3_IRQn = 62, /*!< SPI3 Interrupt */ 00161 EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */ 00162 EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */ 00163 SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ 00164 USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ 00165 I2S0_IRQn = 68, /*!< I2S0 Interrupt */ 00166 OPA_IRQn = 70, /*!< OPA Interrupt */ 00167 CRPT_IRQn = 71, /*!< CRPT Interrupt */ 00168 GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ 00169 EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ 00170 UART4_IRQn = 74, /*!< UART4 Interrupt */ 00171 UART5_IRQn = 75, /*!< UART5 Interrupt */ 00172 USCI0_IRQn = 76, /*!< USCI0 Interrupt */ 00173 USCI1_IRQn = 77, /*!< USCI1 Interrupt */ 00174 BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ 00175 BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ 00176 SPIM_IRQn = 80, /*!< SPIM Interrupt */ 00177 I2C2_IRQn = 82, /*!< I2C2 Interrupt */ 00178 QEI0_IRQn = 84, /*!< QEI0 Interrupt */ 00179 QEI1_IRQn = 85, /*!< QEI1 Interrupt */ 00180 ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ 00181 ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ 00182 GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ 00183 EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ 00184 SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ 00185 HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ 00186 USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ 00187 } 00188 IRQn_Type ; 00189 00190 00191 /* 00192 * ========================================================================== 00193 * ----------- Processor and Core Peripheral Section ------------------------ 00194 * ========================================================================== 00195 */ 00196 00197 /* Configuration of the Cortex-M4 Processor and Core Peripherals */ 00198 #define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ 00199 #define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ 00200 #define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ 00201 #define __MPU_PRESENT 1UL /*!< MPU present or not */ 00202 #ifdef __FPU_PRESENT 00203 #undef __FPU_PRESENT 00204 #define __FPU_PRESENT 1UL /*!< FPU present or not */ 00205 #else 00206 #define __FPU_PRESENT 1UL /*!< FPU present or not */ 00207 #endif 00208 00209 /*@}*/ /* end of group CMSIS_Device */ 00210 00211 00212 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 00213 #include "system_M480.h" /* System include file */ 00214 #include <stdint.h> 00215 00216 00217 00218 #if defined ( __CC_ARM ) 00219 #pragma anon_unions 00220 #endif 00221 00222 /******************************************************************************/ 00223 /* Register definitions */ 00224 /******************************************************************************/ 00225 00226 #include "m480_sys_reg.h" 00227 #include "m480_clk_reg.h" 00228 #include "m480_fmc_reg.h" 00229 #include "m480_gpio_reg.h" 00230 #include "m480_rtc_reg.h" 00231 #include "m480_uart_reg.h" 00232 #include "m480_hsusbd_reg.h" 00233 00234 00235 /** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base 00236 Memory Mapped Structure for Peripherals 00237 @{ 00238 */ 00239 /* Peripheral and SRAM base address */ 00240 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ 00241 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ 00242 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ 00243 #define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */ 00244 #define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */ 00245 00246 /*!< AHB peripherals */ 00247 #define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) 00248 #define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) 00249 #define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) 00250 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) 00251 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) 00252 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) 00253 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) 00254 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) 00255 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) 00256 #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) 00257 #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) 00258 #define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL) 00259 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) 00260 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) 00261 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) 00262 #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) 00263 #define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL) 00264 #define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL) 00265 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) 00266 #define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) 00267 #define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) 00268 #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) 00269 #define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL) 00270 #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) 00271 #define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL) 00272 00273 /*!< APB2 peripherals */ 00274 #define WDT_BASE (APBPERIPH_BASE + 0x00000UL) 00275 #define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) 00276 #define OPA_BASE (APBPERIPH_BASE + 0x06000UL) 00277 #define I2S_BASE (APBPERIPH_BASE + 0x08000UL) 00278 #define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL) 00279 #define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL) 00280 #define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) 00281 #define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) 00282 #define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) 00283 #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) 00284 #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) 00285 #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) 00286 #define UART2_BASE (APBPERIPH_BASE + 0x32000UL) 00287 #define UART4_BASE (APBPERIPH_BASE + 0x34000UL) 00288 #define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) 00289 #define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) 00290 #define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) 00291 #define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) 00292 #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) 00293 #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) 00294 00295 00296 /*!< APB1 peripherals */ 00297 #define RTC_BASE (APBPERIPH_BASE + 0x01000UL) 00298 #define EADC_BASE (APBPERIPH_BASE + 0x03000UL) 00299 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) 00300 #define USBD_BASE (APBPERIPH_BASE + 0x80000UL) 00301 #define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) 00302 #define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL) 00303 #define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL) 00304 #define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL) 00305 #define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) 00306 #define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) 00307 #define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) 00308 #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) 00309 #define UART1_BASE (APBPERIPH_BASE + 0x31000UL) 00310 #define UART3_BASE (APBPERIPH_BASE + 0x33000UL) 00311 #define UART5_BASE (APBPERIPH_BASE + 0x35000UL) 00312 #define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) 00313 #define CAN1_BASE (APBPERIPH_BASE + 0x61000UL) 00314 #define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) 00315 #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) 00316 #define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) 00317 #define CRPT_BASE (0x50080000UL) 00318 #define SPIM_BASE (0x40007000UL) 00319 00320 #define SC0_BASE (APBPERIPH_BASE + 0x50000UL) 00321 #define SC1_BASE (APBPERIPH_BASE + 0x51000UL) 00322 #define SC2_BASE (APBPERIPH_BASE + 0x52000UL) 00323 #define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) 00324 #define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) 00325 #define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL) 00326 #define OPA0_BASE (APBPERIPH_BASE + 0x06000UL) 00327 00328 /*@}*/ /* end of group PERIPHERAL_MEM_MAP */ 00329 00330 00331 /** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer 00332 The Declaration of Peripherals 00333 @{ 00334 */ 00335 00336 #define SYS ((SYS_T *) SYS_BASE) 00337 #define CLK ((CLK_T *) CLK_BASE) 00338 #define NMI ((NMI_T *) NMI_BASE) 00339 #define PA ((GPIO_T *) GPIOA_BASE) 00340 #define PB ((GPIO_T *) GPIOB_BASE) 00341 #define PC ((GPIO_T *) GPIOC_BASE) 00342 #define PD ((GPIO_T *) GPIOD_BASE) 00343 #define PE ((GPIO_T *) GPIOE_BASE) 00344 #define PF ((GPIO_T *) GPIOF_BASE) 00345 #define PG ((GPIO_T *) GPIOG_BASE) 00346 #define PH ((GPIO_T *) GPIOH_BASE) 00347 #define GPA ((GPIO_T *) GPIOA_BASE) 00348 #define GPB ((GPIO_T *) GPIOB_BASE) 00349 #define GPC ((GPIO_T *) GPIOC_BASE) 00350 #define GPD ((GPIO_T *) GPIOD_BASE) 00351 #define GPE ((GPIO_T *) GPIOE_BASE) 00352 #define GPF ((GPIO_T *) GPIOF_BASE) 00353 #define GPG ((GPIO_T *) GPIOG_BASE) 00354 #define GPH ((GPIO_T *) GPIOH_BASE) 00355 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) 00356 #define PDMA ((PDMA_T *) PDMA_BASE) 00357 #define USBH ((USBH_T *) USBH_BASE) 00358 #define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) 00359 #define EMAC ((EMAC_T *) EMAC_BASE) 00360 #define FMC ((FMC_T *) FMC_BASE) 00361 #define SDH0 ((SDH_T *) SDH0_BASE) 00362 #define SDH1 ((SDH_T *) SDH1_BASE) 00363 #define EBI ((EBI_T *) EBI_BASE) 00364 #define CRC ((CRC_T *) CRC_BASE) 00365 #define TAMPER ((TAMPER_T *) TAMPER_BASE) 00366 00367 #define WDT ((WDT_T *) WDT_BASE) 00368 #define WWDT ((WWDT_T *) WWDT_BASE) 00369 #define RTC ((RTC_T *) RTC_BASE) 00370 #define EADC ((EADC_T *) EADC_BASE) 00371 #define ACMP01 ((ACMP_T *) ACMP01_BASE) 00372 00373 #define I2S0 ((I2S_T *) I2S_BASE) 00374 #define USBD ((USBD_T *) USBD_BASE) 00375 #define OTG ((OTG_T *) OTG_BASE) 00376 #define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) 00377 #define HSOTG ((HSOTG_T *) HSOTG_BASE) 00378 #define TIMER0 ((TIMER_T *) TIMER0_BASE) 00379 #define TIMER1 ((TIMER_T *) TIMER1_BASE) 00380 #define TIMER2 ((TIMER_T *) TIMER2_BASE) 00381 #define TIMER3 ((TIMER_T *) TIMER3_BASE) 00382 #define EPWM0 ((EPWM_T *) EPWM0_BASE) 00383 #define EPWM1 ((EPWM_T *) EPWM1_BASE) 00384 #define BPWM0 ((BPWM_T *) BPWM0_BASE) 00385 #define BPWM1 ((BPWM_T *) BPWM1_BASE) 00386 #define ECAP0 ((ECAP_T *) ECAP0_BASE) 00387 #define ECAP1 ((ECAP_T *) ECAP1_BASE) 00388 #define QEI0 ((QEI_T *) QEI0_BASE) 00389 #define QEI1 ((QEI_T *) QEI1_BASE) 00390 #define QSPI0 ((QSPI_T *) QSPI0_BASE) 00391 #define SPI0 ((SPI_T *) SPI0_BASE) 00392 #define SPI1 ((SPI_T *) SPI1_BASE) 00393 #define SPI2 ((SPI_T *) SPI2_BASE) 00394 #define SPI3 ((SPI_T *) SPI3_BASE) 00395 #define UART0 ((UART_T *) UART0_BASE) 00396 #define UART1 ((UART_T *) UART1_BASE) 00397 #define UART2 ((UART_T *) UART2_BASE) 00398 #define UART3 ((UART_T *) UART3_BASE) 00399 #define UART4 ((UART_T *) UART4_BASE) 00400 #define UART5 ((UART_T *) UART5_BASE) 00401 #define I2C0 ((I2C_T *) I2C0_BASE) 00402 #define I2C1 ((I2C_T *) I2C1_BASE) 00403 #define I2C2 ((I2C_T *) I2C2_BASE) 00404 #define SC0 ((SC_T *) SC0_BASE) 00405 #define SC1 ((SC_T *) SC1_BASE) 00406 #define SC2 ((SC_T *) SC2_BASE) 00407 #define CAN0 ((CAN_T *) CAN0_BASE) 00408 #define CAN1 ((CAN_T *) CAN1_BASE) 00409 #define CRPT ((CRPT_T *) CRPT_BASE) 00410 #define SPIM ((volatile SPIM_T *) SPIM_BASE) 00411 #define DAC0 ((DAC_T *) DAC0_BASE) 00412 #define DAC1 ((DAC_T *) DAC1_BASE) 00413 #define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ 00414 #define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */ 00415 #define OPA ((OPA_T *) OPA_BASE) 00416 #define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ 00417 #define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ 00418 #define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ 00419 #define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */ 00420 00421 /*@}*/ /* end of group ERIPHERAL_DECLARATION */ 00422 00423 /** @addtogroup IO_ROUTINE I/O Routines 00424 The Declaration of I/O Routines 00425 @{ 00426 */ 00427 00428 typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type 00429 typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type 00430 typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type 00431 00432 /** 00433 * @brief Get a 8-bit unsigned value from specified address 00434 * @param[in] addr Address to get 8-bit data from 00435 * @return 8-bit unsigned value stored in specified address 00436 */ 00437 #define M8(addr) (*((vu8 *) (addr))) 00438 00439 /** 00440 * @brief Get a 16-bit unsigned value from specified address 00441 * @param[in] addr Address to get 16-bit data from 00442 * @return 16-bit unsigned value stored in specified address 00443 * @note The input address must be 16-bit aligned 00444 */ 00445 #define M16(addr) (*((vu16 *) (addr))) 00446 00447 /** 00448 * @brief Get a 32-bit unsigned value from specified address 00449 * @param[in] addr Address to get 32-bit data from 00450 * @return 32-bit unsigned value stored in specified address 00451 * @note The input address must be 32-bit aligned 00452 */ 00453 #define M32(addr) (*((vu32 *) (addr))) 00454 00455 /** 00456 * @brief Set a 32-bit unsigned value to specified I/O port 00457 * @param[in] port Port address to set 32-bit data 00458 * @param[in] value Value to write to I/O port 00459 * @return None 00460 * @note The output port must be 32-bit aligned 00461 */ 00462 #define outpw(port,value) *((volatile unsigned int *)(port)) = (value) 00463 00464 /** 00465 * @brief Get a 32-bit unsigned value from specified I/O port 00466 * @param[in] port Port address to get 32-bit data from 00467 * @return 32-bit unsigned value stored in specified I/O port 00468 * @note The input port must be 32-bit aligned 00469 */ 00470 #define inpw(port) (*((volatile unsigned int *)(port))) 00471 00472 /** 00473 * @brief Set a 16-bit unsigned value to specified I/O port 00474 * @param[in] port Port address to set 16-bit data 00475 * @param[in] value Value to write to I/O port 00476 * @return None 00477 * @note The output port must be 16-bit aligned 00478 */ 00479 #define outps(port,value) *((volatile unsigned short *)(port)) = (value) 00480 00481 /** 00482 * @brief Get a 16-bit unsigned value from specified I/O port 00483 * @param[in] port Port address to get 16-bit data from 00484 * @return 16-bit unsigned value stored in specified I/O port 00485 * @note The input port must be 16-bit aligned 00486 */ 00487 #define inps(port) (*((volatile unsigned short *)(port))) 00488 00489 /** 00490 * @brief Set a 8-bit unsigned value to specified I/O port 00491 * @param[in] port Port address to set 8-bit data 00492 * @param[in] value Value to write to I/O port 00493 * @return None 00494 */ 00495 #define outpb(port,value) *((volatile unsigned char *)(port)) = (value) 00496 00497 /** 00498 * @brief Get a 8-bit unsigned value from specified I/O port 00499 * @param[in] port Port address to get 8-bit data from 00500 * @return 8-bit unsigned value stored in specified I/O port 00501 */ 00502 #define inpb(port) (*((volatile unsigned char *)(port))) 00503 00504 /** 00505 * @brief Set a 32-bit unsigned value to specified I/O port 00506 * @param[in] port Port address to set 32-bit data 00507 * @param[in] value Value to write to I/O port 00508 * @return None 00509 * @note The output port must be 32-bit aligned 00510 */ 00511 #define outp32(port,value) *((volatile unsigned int *)(port)) = (value) 00512 00513 /** 00514 * @brief Get a 32-bit unsigned value from specified I/O port 00515 * @param[in] port Port address to get 32-bit data from 00516 * @return 32-bit unsigned value stored in specified I/O port 00517 * @note The input port must be 32-bit aligned 00518 */ 00519 #define inp32(port) (*((volatile unsigned int *)(port))) 00520 00521 /** 00522 * @brief Set a 16-bit unsigned value to specified I/O port 00523 * @param[in] port Port address to set 16-bit data 00524 * @param[in] value Value to write to I/O port 00525 * @return None 00526 * @note The output port must be 16-bit aligned 00527 */ 00528 #define outp16(port,value) *((volatile unsigned short *)(port)) = (value) 00529 00530 /** 00531 * @brief Get a 16-bit unsigned value from specified I/O port 00532 * @param[in] port Port address to get 16-bit data from 00533 * @return 16-bit unsigned value stored in specified I/O port 00534 * @note The input port must be 16-bit aligned 00535 */ 00536 #define inp16(port) (*((volatile unsigned short *)(port))) 00537 00538 /** 00539 * @brief Set a 8-bit unsigned value to specified I/O port 00540 * @param[in] port Port address to set 8-bit data 00541 * @param[in] value Value to write to I/O port 00542 * @return None 00543 */ 00544 #define outp8(port,value) *((volatile unsigned char *)(port)) = (value) 00545 00546 /** 00547 * @brief Get a 8-bit unsigned value from specified I/O port 00548 * @param[in] port Port address to get 8-bit data from 00549 * @return 8-bit unsigned value stored in specified I/O port 00550 */ 00551 #define inp8(port) (*((volatile unsigned char *)(port))) 00552 00553 00554 /*@}*/ /* end of group IO_ROUTINE */ 00555 00556 /******************************************************************************/ 00557 /* Legacy Constants */ 00558 /******************************************************************************/ 00559 /** @addtogroup Legacy_Constants Legacy Constants 00560 Legacy Constants 00561 @{ 00562 */ 00563 00564 #ifndef NULL 00565 #define NULL (0) ///< NULL pointer 00566 #endif 00567 00568 #define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value 00569 #define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value 00570 00571 #define ENABLE (1UL) ///< Enable, define to use in API parameters 00572 #define DISABLE (0UL) ///< Disable, define to use in API parameters 00573 00574 /* Define one bit mask */ 00575 #define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer 00576 #define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer 00577 #define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer 00578 #define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer 00579 #define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer 00580 #define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer 00581 #define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer 00582 #define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer 00583 #define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer 00584 #define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer 00585 #define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer 00586 #define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer 00587 #define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer 00588 #define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer 00589 #define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer 00590 #define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer 00591 #define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer 00592 #define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer 00593 #define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer 00594 #define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer 00595 #define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer 00596 #define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer 00597 #define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer 00598 #define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer 00599 #define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer 00600 #define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer 00601 #define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer 00602 #define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer 00603 #define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer 00604 #define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer 00605 #define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer 00606 #define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer 00607 00608 /* Byte Mask Definitions */ 00609 #define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer 00610 #define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer 00611 #define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer 00612 #define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer 00613 00614 #define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ 00615 #define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ 00616 #define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ 00617 #define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ 00618 00619 /*@}*/ /* end of group Legacy_Constants */ 00620 00621 00622 /******************************************************************************/ 00623 /* Peripheral header files */ 00624 /******************************************************************************/ 00625 #include "m480_sys.h" 00626 #include "m480_clk.h" 00627 #include "m480_uart.h" 00628 #include "m480_gpio.h" 00629 #include "m480_fmc.h" 00630 #include "m480_rtc.h" 00631 00632 00633 #ifdef __cplusplus 00634 } 00635 #endif 00636 00637 #endif /* __M480_H__ */ 00638
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