Arrow / Mbed OS DAPLink Reset

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Embed: (wiki syntax)

« Back to documentation index

M480.h File Reference
Typedefs | Enumerations

M480.h File Reference

M480 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro M480 MCU. More...

Go to the source code of this file.

Typedefs

typedef enum IRQn IRQn_Type
typedef volatile unsigned char vu8
 Define 8-bit unsigned volatile data type.
typedef volatile unsigned short vu16
 Define 16-bit unsigned volatile data type.
typedef volatile unsigned long vu32
 Define 32-bit unsigned volatile data type.

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3,
  WDT_IRQn = 4, PMC_IRQn = 5, EFC0_IRQn = 6, UART_IRQn = 8,
  SMC_IRQn = 9, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13,
  USART1_IRQn = 14, USART2_IRQn = 15, HSMCI_IRQn = 17, TWI0_IRQn = 18,
  TWI1_IRQn = 19, SPI_IRQn = 20, SSC_IRQn = 21, TC0_IRQn = 22,
  TC1_IRQn = 23, TC2_IRQn = 24, PWM_IRQn = 25, ADC12B_IRQn = 26,
  ADC_IRQn = 27, DMAC_IRQn = 28, UDPHS_IRQn = 29, PERIPH_COUNT_IRQn = 30,
  NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, DMA0_IRQn = 0, DMA1_IRQn = 1,
  DMA2_IRQn = 2, DMA3_IRQn = 3, DMA_Error_IRQn = 4, Reserved21_IRQn = 5,
  FTFL_IRQn = 6, Read_Collision_IRQn = 7, LVD_LVW_IRQn = 8, LLW_IRQn = 9,
  Watchdog_IRQn = 10, I2C0_IRQn = 11, SPI0_IRQn = 12, I2S0_Tx_IRQn = 13,
  I2S0_Rx_IRQn = 14, UART0_LON_IRQn = 15, UART0_RX_TX_IRQn = 16, UART0_ERR_IRQn = 17,
  UART1_RX_TX_IRQn = 18, UART1_ERR_IRQn = 19, UART2_RX_TX_IRQn = 20, UART2_ERR_IRQn = 21,
  ADC0_IRQn = 22, CMP0_IRQn = 23, CMP1_IRQn = 24, FTM0_IRQn = 25,
  FTM1_IRQn = 26, CMT_IRQn = 27, RTC_IRQn = 28, RTC_Seconds_IRQn = 29,
  PIT0_IRQn = 30, PIT1_IRQn = 31, PIT2_IRQn = 32, PIT3_IRQn = 33,
  PDB0_IRQn = 34, USB0_IRQn = 35, USBDCD_IRQn = 36, TSI0_IRQn = 37,
  MCG_IRQn = 38, LPTimer_IRQn = 39, PORTA_IRQn = 40, PORTB_IRQn = 41,
  PORTC_IRQn = 42, PORTD_IRQn = 43, PORTE_IRQn = 44, SWI_IRQn = 45,
  NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, DMA0_DMA16_IRQn = 0, DMA1_DMA17_IRQn = 1,
  DMA2_DMA18_IRQn = 2, DMA3_DMA19_IRQn = 3, DMA4_DMA20_IRQn = 4, DMA5_DMA21_IRQn = 5,
  DMA6_DMA22_IRQn = 6, DMA7_DMA23_IRQn = 7, DMA8_DMA24_IRQn = 8, DMA9_DMA25_IRQn = 9,
  DMA10_DMA26_IRQn = 10, DMA11_DMA27_IRQn = 11, DMA12_DMA28_IRQn = 12, DMA13_DMA29_IRQn = 13,
  DMA14_DMA30_IRQn = 14, DMA15_DMA31_IRQn = 15, DMA_Error_IRQn = 16, MCM_IRQn = 17,
  FTFE_IRQn = 18, Read_Collision_IRQn = 19, LVD_LVW_IRQn = 20, LLWU_IRQn = 21,
  WDOG_EWM_IRQn = 22, RNG_IRQn = 23, I2C0_IRQn = 24, I2C1_IRQn = 25,
  SPI0_IRQn = 26, SPI1_IRQn = 27, I2S0_Tx_IRQn = 28, I2S0_Rx_IRQn = 29,
  Reserved46_IRQn = 30, UART0_RX_TX_IRQn = 31, UART0_ERR_IRQn = 32, UART1_RX_TX_IRQn = 33,
  UART1_ERR_IRQn = 34, UART2_RX_TX_IRQn = 35, UART2_ERR_IRQn = 36, UART3_RX_TX_IRQn = 37,
  UART3_ERR_IRQn = 38, ADC0_IRQn = 39, CMP0_IRQn = 40, CMP1_IRQn = 41,
  FTM0_IRQn = 42, FTM1_IRQn = 43, FTM2_IRQn = 44, CMT_IRQn = 45,
  RTC_IRQn = 46, RTC_Seconds_IRQn = 47, PIT0_IRQn = 48, PIT1_IRQn = 49,
  PIT2_IRQn = 50, PIT3_IRQn = 51, PDB0_IRQn = 52, USB0_IRQn = 53,
  USBDCD_IRQn = 54, Reserved71_IRQn = 55, DAC0_IRQn = 56, MCG_IRQn = 57,
  LPTMR0_IRQn = 58, PORTA_IRQn = 59, PORTB_IRQn = 60, PORTC_IRQn = 61,
  PORTD_IRQn = 62, PORTE_IRQn = 63, SWI_IRQn = 64, SPI2_IRQn = 65,
  UART4_RX_TX_IRQn = 66, UART4_ERR_IRQn = 67, Reserved84_IRQn = 68, Reserved85_IRQn = 69,
  CMP2_IRQn = 70, FTM3_IRQn = 71, DAC1_IRQn = 72, ADC1_IRQn = 73,
  I2C2_IRQn = 74, CAN0_ORed_Message_buffer_IRQn = 75, CAN0_Bus_Off_IRQn = 76, CAN0_Error_IRQn = 77,
  CAN0_Tx_Warning_IRQn = 78, CAN0_Rx_Warning_IRQn = 79, CAN0_Wake_Up_IRQn = 80, SDHC_IRQn = 81,
  Reserved98_IRQn = 82, Reserved99_IRQn = 83, Reserved100_IRQn = 84, Reserved101_IRQn = 85,
  LPUART0_IRQn = 86, TSI0_IRQn = 87, TPM1_IRQn = 88, TPM2_IRQn = 89,
  USBHSDCD_IRQn = 90, I2C3_IRQn = 91, CMP3_IRQn = 92, USBHS_IRQn = 93,
  CAN1_ORed_Message_buffer_IRQn = 94, CAN1_Bus_Off_IRQn = 95, CAN1_Error_IRQn = 96, CAN1_Tx_Warning_IRQn = 97,
  CAN1_Rx_Warning_IRQn = 98, CAN1_Wake_Up_IRQn = 99, NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1,
  DMA0_IRQn = 0, DMA1_IRQn = 1, DMA2_IRQn = 2, DMA3_IRQn = 3,
  Reserved20_IRQn = 4, FTFA_IRQn = 5, LVD_LVW_IRQn = 6, LLWU_IRQn = 7,
  I2C0_IRQn = 8, I2C1_IRQn = 9, SPI0_IRQn = 10, SPI1_IRQn = 11,
  UART0_IRQn = 12, UART1_IRQn = 13, UART2_IRQn = 14, ADC0_IRQn = 15,
  CMP0_IRQn = 16, TPM0_IRQn = 17, TPM1_IRQn = 18, TPM2_IRQn = 19,
  RTC_IRQn = 20, RTC_Seconds_IRQn = 21, PIT_IRQn = 22, I2S0_IRQn = 23,
  USB0_IRQn = 24, DAC0_IRQn = 25, TSI0_IRQn = 26, MCG_IRQn = 27,
  LPTMR0_IRQn = 28, Reserved45_IRQn = 29, PORTA_IRQn = 30, PORTC_PORTD_IRQn = 31,
  NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  BOD_IRQn = 0, IRC_IRQn = 1, PWRWU_IRQn = 2, RAMPE_IRQn = 3,
  CKFAIL_IRQn = 4, RTC_IRQn = 6, TAMPER_IRQn = 7, WDT_IRQn = 8,
  WWDT_IRQn = 9, EINT0_IRQn = 10, EINT1_IRQn = 11, EINT2_IRQn = 12,
  EINT3_IRQn = 13, EINT4_IRQn = 14, EINT5_IRQn = 15, GPA_IRQn = 16,
  GPB_IRQn = 17, GPC_IRQn = 18, GPD_IRQn = 19, GPE_IRQn = 20,
  GPF_IRQn = 21, QSPI0_IRQn = 22, SPI0_IRQn = 23, BRAKE0_IRQn = 24,
  EPWM0P0_IRQn = 25, EPWM0P1_IRQn = 26, EPWM0P2_IRQn = 27, BRAKE1_IRQn = 28,
  EPWM1P0_IRQn = 29, EPWM1P1_IRQn = 30, EPWM1P2_IRQn = 31, TMR0_IRQn = 32,
  TMR1_IRQn = 33, TMR2_IRQn = 34, TMR3_IRQn = 35, UART0_IRQn = 36,
  UART1_IRQn = 37, I2C0_IRQn = 38, I2C1_IRQn = 39, PDMA_IRQn = 40,
  DAC_IRQn = 41, ADC0_IRQn = 42, ADC1_IRQn = 43, ACMP01_IRQn = 44,
  ADC2_IRQn = 46, ADC3_IRQn = 47, UART2_IRQn = 48, UART3_IRQn = 49,
  SPI1_IRQn = 51, SPI2_IRQn = 52, USBD_IRQn = 53, USBH_IRQn = 54,
  USBOTG_IRQn = 55, CAN0_IRQn = 56, CAN1_IRQn = 57, SC0_IRQn = 58,
  SC1_IRQn = 59, SC2_IRQn = 60, SPI3_IRQn = 62, EMAC_TX_IRQn = 66,
  EMAC_RX_IRQn = 67, SDH0_IRQn = 64, USBD20_IRQn = 65, I2S0_IRQn = 68,
  OPA_IRQn = 70, CRPT_IRQn = 71, GPG_IRQn = 72, EINT6_IRQn = 73,
  UART4_IRQn = 74, UART5_IRQn = 75, USCI0_IRQn = 76, USCI1_IRQn = 77,
  BPWM0_IRQn = 78, BPWM1_IRQn = 79, SPIM_IRQn = 80, I2C2_IRQn = 82,
  QEI0_IRQn = 84, QEI1_IRQn = 85, ECAP0_IRQn = 86, ECAP1_IRQn = 87,
  GPH_IRQn = 88, EINT7_IRQn = 89, SDH1_IRQn = 90, HSUSBH_IRQn = 92,
  USBOTG20_IRQn = 93
}

Detailed Description

M480 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro M480 MCU.

Version:
V1.00 (C) 2017-2018 Nuvoton Technology Corp. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file M480.h.

Generated on Tue Jul 12 2022 15:37:30 by  doxygen 1.7.2