Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/stm32/stm32f103xb/cmsis/stm32f103xb.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | ****************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * @file stm32f103xb.h |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * @author MCD Application Team |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * @version V4.1.0 |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * @date 29-April-2016 |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * This file contains all the peripheral register's definitions, bits |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * definitions and memory mapping for STM32F1xx devices. |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * This file contains: |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * - Data structures and the address mapping for all peripherals |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * - Peripheral's registers declarations and bits definition |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * - Macros to access peripheral.s registers hardware |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | ****************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * @attention |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * Redistribution and use in source and binary forms, with or without modification, |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * are permitted provided that the following conditions are met: |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * 1. Redistributions of source code must retain the above copyright notice, |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * this list of conditions and the following disclaimer. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * this list of conditions and the following disclaimer in the documentation |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * and/or other materials provided with the distribution. |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * may be used to endorse or promote products derived from this software |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * without specific prior written permission. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | ****************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | /** @addtogroup CMSIS |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | /** @addtogroup stm32f103xb |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | #ifndef __STM32F103xB_H |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define __STM32F103xB_H |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | #ifdef __cplusplus |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | extern "C" { |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | /** @addtogroup Configuration_section_for_CMSIS |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | /** @addtogroup Peripheral_interrupt_number_definition |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | * in @ref Library_configuration_section |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | /*!< Interrupt Number Definition */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | typedef enum |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | } IRQn_Type; |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #include "core_cm3.h" |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #include "system_stm32f1xx.h" |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #include <stdint.h> |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | /** @addtogroup Peripheral_registers_structures |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | * @brief Analog to Digital Converter |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | __IO uint32_t SR; |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | __IO uint32_t CR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | __IO uint32_t CR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | __IO uint32_t SMPR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | __IO uint32_t SMPR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | __IO uint32_t JOFR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | __IO uint32_t JOFR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | __IO uint32_t JOFR3; |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | __IO uint32_t JOFR4; |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | __IO uint32_t HTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | __IO uint32_t LTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | __IO uint32_t SQR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | __IO uint32_t SQR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | __IO uint32_t SQR3; |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | __IO uint32_t JSQR; |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | __IO uint32_t JDR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | __IO uint32_t JDR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | __IO uint32_t JDR3; |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | __IO uint32_t JDR4; |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | __IO uint32_t DR; |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | } ADC_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | uint32_t RESERVED[16]; |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | } ADC_Common_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | * @brief Backup Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | uint32_t RESERVED0; |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | __IO uint32_t DR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | __IO uint32_t DR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | __IO uint32_t DR3; |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | __IO uint32_t DR4; |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | __IO uint32_t DR5; |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | __IO uint32_t DR6; |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | __IO uint32_t DR7; |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | __IO uint32_t DR8; |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | __IO uint32_t DR9; |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | __IO uint32_t DR10; |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | __IO uint32_t RTCCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | __IO uint32_t CR; |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | __IO uint32_t CSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | } BKP_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | * @brief Controller Area Network TxMailBox |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | { |
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0:01f31e923fe2 | 224 | __IO uint32_t TIR; |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | __IO uint32_t TDTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | __IO uint32_t TDLR; |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | __IO uint32_t TDHR; |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | } CAN_TxMailBox_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | * @brief Controller Area Network FIFOMailBox |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | __IO uint32_t RIR; |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | __IO uint32_t RDTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | __IO uint32_t RDLR; |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | __IO uint32_t RDHR; |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | } CAN_FIFOMailBox_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | * @brief Controller Area Network FilterRegister |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | __IO uint32_t FR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | __IO uint32_t FR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | } CAN_FilterRegister_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | * @brief Controller Area Network |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | __IO uint32_t MCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | __IO uint32_t MSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | __IO uint32_t TSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | __IO uint32_t RF0R; |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | __IO uint32_t RF1R; |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | __IO uint32_t IER; |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | __IO uint32_t ESR; |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | __IO uint32_t BTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | uint32_t RESERVED0[88]; |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | CAN_TxMailBox_TypeDef sTxMailBox[3]; |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | uint32_t RESERVED1[12]; |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | __IO uint32_t FMR; |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | __IO uint32_t FM1R; |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | uint32_t RESERVED2; |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | __IO uint32_t FS1R; |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | uint32_t RESERVED3; |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | __IO uint32_t FFA1R; |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | uint32_t RESERVED4; |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | __IO uint32_t FA1R; |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | uint32_t RESERVED5[8]; |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | CAN_FilterRegister_TypeDef sFilterRegister[14]; |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | } CAN_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | * @brief CRC calculation unit |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | } CRC_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | * @brief Debug MCU |
| Pawel Zarembski |
0:01f31e923fe2 | 298 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 301 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | __IO uint32_t IDCODE; |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | __IO uint32_t CR; |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | }DBGMCU_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | * @brief DMA Controller |
| Pawel Zarembski |
0:01f31e923fe2 | 308 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 309 | |
| Pawel Zarembski |
0:01f31e923fe2 | 310 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 311 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 312 | __IO uint32_t CCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 313 | __IO uint32_t CNDTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 314 | __IO uint32_t CPAR; |
| Pawel Zarembski |
0:01f31e923fe2 | 315 | __IO uint32_t CMAR; |
| Pawel Zarembski |
0:01f31e923fe2 | 316 | } DMA_Channel_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 317 | |
| Pawel Zarembski |
0:01f31e923fe2 | 318 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 319 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 320 | __IO uint32_t ISR; |
| Pawel Zarembski |
0:01f31e923fe2 | 321 | __IO uint32_t IFCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 322 | } DMA_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 323 | |
| Pawel Zarembski |
0:01f31e923fe2 | 324 | |
| Pawel Zarembski |
0:01f31e923fe2 | 325 | |
| Pawel Zarembski |
0:01f31e923fe2 | 326 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 327 | * @brief External Interrupt/Event Controller |
| Pawel Zarembski |
0:01f31e923fe2 | 328 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 329 | |
| Pawel Zarembski |
0:01f31e923fe2 | 330 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 331 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 332 | __IO uint32_t IMR; |
| Pawel Zarembski |
0:01f31e923fe2 | 333 | __IO uint32_t EMR; |
| Pawel Zarembski |
0:01f31e923fe2 | 334 | __IO uint32_t RTSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 335 | __IO uint32_t FTSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 336 | __IO uint32_t SWIER; |
| Pawel Zarembski |
0:01f31e923fe2 | 337 | __IO uint32_t PR; |
| Pawel Zarembski |
0:01f31e923fe2 | 338 | } EXTI_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 339 | |
| Pawel Zarembski |
0:01f31e923fe2 | 340 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 341 | * @brief FLASH Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 342 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 343 | |
| Pawel Zarembski |
0:01f31e923fe2 | 344 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 345 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 346 | __IO uint32_t ACR; |
| Pawel Zarembski |
0:01f31e923fe2 | 347 | __IO uint32_t KEYR; |
| Pawel Zarembski |
0:01f31e923fe2 | 348 | __IO uint32_t OPTKEYR; |
| Pawel Zarembski |
0:01f31e923fe2 | 349 | __IO uint32_t SR; |
| Pawel Zarembski |
0:01f31e923fe2 | 350 | __IO uint32_t CR; |
| Pawel Zarembski |
0:01f31e923fe2 | 351 | __IO uint32_t AR; |
| Pawel Zarembski |
0:01f31e923fe2 | 352 | __IO uint32_t RESERVED; |
| Pawel Zarembski |
0:01f31e923fe2 | 353 | __IO uint32_t OBR; |
| Pawel Zarembski |
0:01f31e923fe2 | 354 | __IO uint32_t WRPR; |
| Pawel Zarembski |
0:01f31e923fe2 | 355 | } FLASH_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 356 | |
| Pawel Zarembski |
0:01f31e923fe2 | 357 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 358 | * @brief Option Bytes Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 359 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 360 | |
| Pawel Zarembski |
0:01f31e923fe2 | 361 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 362 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 363 | __IO uint16_t RDP; |
| Pawel Zarembski |
0:01f31e923fe2 | 364 | __IO uint16_t USER; |
| Pawel Zarembski |
0:01f31e923fe2 | 365 | __IO uint16_t Data0; |
| Pawel Zarembski |
0:01f31e923fe2 | 366 | __IO uint16_t Data1; |
| Pawel Zarembski |
0:01f31e923fe2 | 367 | __IO uint16_t WRP0; |
| Pawel Zarembski |
0:01f31e923fe2 | 368 | __IO uint16_t WRP1; |
| Pawel Zarembski |
0:01f31e923fe2 | 369 | __IO uint16_t WRP2; |
| Pawel Zarembski |
0:01f31e923fe2 | 370 | __IO uint16_t WRP3; |
| Pawel Zarembski |
0:01f31e923fe2 | 371 | } OB_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 372 | |
| Pawel Zarembski |
0:01f31e923fe2 | 373 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 374 | * @brief General Purpose I/O |
| Pawel Zarembski |
0:01f31e923fe2 | 375 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 376 | |
| Pawel Zarembski |
0:01f31e923fe2 | 377 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 378 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 379 | __IO uint32_t CRL; |
| Pawel Zarembski |
0:01f31e923fe2 | 380 | __IO uint32_t CRH; |
| Pawel Zarembski |
0:01f31e923fe2 | 381 | __IO uint32_t IDR; |
| Pawel Zarembski |
0:01f31e923fe2 | 382 | __IO uint32_t ODR; |
| Pawel Zarembski |
0:01f31e923fe2 | 383 | __IO uint32_t BSRR; |
| Pawel Zarembski |
0:01f31e923fe2 | 384 | __IO uint32_t BRR; |
| Pawel Zarembski |
0:01f31e923fe2 | 385 | __IO uint32_t LCKR; |
| Pawel Zarembski |
0:01f31e923fe2 | 386 | } GPIO_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 387 | |
| Pawel Zarembski |
0:01f31e923fe2 | 388 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 389 | * @brief Alternate Function I/O |
| Pawel Zarembski |
0:01f31e923fe2 | 390 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 391 | |
| Pawel Zarembski |
0:01f31e923fe2 | 392 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 393 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 394 | __IO uint32_t EVCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 395 | __IO uint32_t MAPR; |
| Pawel Zarembski |
0:01f31e923fe2 | 396 | __IO uint32_t EXTICR[4]; |
| Pawel Zarembski |
0:01f31e923fe2 | 397 | uint32_t RESERVED0; |
| Pawel Zarembski |
0:01f31e923fe2 | 398 | __IO uint32_t MAPR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 399 | } AFIO_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 400 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 401 | * @brief Inter Integrated Circuit Interface |
| Pawel Zarembski |
0:01f31e923fe2 | 402 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 403 | |
| Pawel Zarembski |
0:01f31e923fe2 | 404 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 405 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 406 | __IO uint32_t CR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 407 | __IO uint32_t CR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 408 | __IO uint32_t OAR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 409 | __IO uint32_t OAR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 410 | __IO uint32_t DR; |
| Pawel Zarembski |
0:01f31e923fe2 | 411 | __IO uint32_t SR1; |
| Pawel Zarembski |
0:01f31e923fe2 | 412 | __IO uint32_t SR2; |
| Pawel Zarembski |
0:01f31e923fe2 | 413 | __IO uint32_t CCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 414 | __IO uint32_t TRISE; |
| Pawel Zarembski |
0:01f31e923fe2 | 415 | } I2C_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 416 | |
| Pawel Zarembski |
0:01f31e923fe2 | 417 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 418 | * @brief Independent WATCHDOG |
| Pawel Zarembski |
0:01f31e923fe2 | 419 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 420 | |
| Pawel Zarembski |
0:01f31e923fe2 | 421 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 422 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 423 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 424 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 425 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 426 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 427 | } IWDG_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 428 | |
| Pawel Zarembski |
0:01f31e923fe2 | 429 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 430 | * @brief Power Control |
| Pawel Zarembski |
0:01f31e923fe2 | 431 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 432 | |
| Pawel Zarembski |
0:01f31e923fe2 | 433 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 434 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 435 | __IO uint32_t CR; |
| Pawel Zarembski |
0:01f31e923fe2 | 436 | __IO uint32_t CSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 437 | } PWR_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 438 | |
| Pawel Zarembski |
0:01f31e923fe2 | 439 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 440 | * @brief Reset and Clock Control |
| Pawel Zarembski |
0:01f31e923fe2 | 441 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 442 | |
| Pawel Zarembski |
0:01f31e923fe2 | 443 | typedef struct |
| Pawel Zarembski |
0:01f31e923fe2 | 444 | { |
| Pawel Zarembski |
0:01f31e923fe2 | 445 | __IO uint32_t CR; |
| Pawel Zarembski |
0:01f31e923fe2 | 446 | __IO uint32_t CFGR; |
| Pawel Zarembski |
0:01f31e923fe2 | 447 | __IO uint32_t CIR; |
| Pawel Zarembski |
0:01f31e923fe2 | 448 | __IO uint32_t APB2RSTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 449 | __IO uint32_t APB1RSTR; |
| Pawel Zarembski |
0:01f31e923fe2 | 450 | __IO uint32_t AHBENR; |
| Pawel Zarembski |
0:01f31e923fe2 | 451 | __IO uint32_t APB2ENR; |
| Pawel Zarembski |
0:01f31e923fe2 | 452 | __IO uint32_t APB1ENR; |
| Pawel Zarembski |
0:01f31e923fe2 | 453 | __IO uint32_t BDCR; |
| Pawel Zarembski |
0:01f31e923fe2 | 454 | __IO uint32_t CSR; |
| Pawel Zarembski |
0:01f31e923fe2 | 455 | |
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0:01f31e923fe2 | 456 | |
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0:01f31e923fe2 | 457 | } RCC_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 458 | |
| Pawel Zarembski |
0:01f31e923fe2 | 459 | /** |
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0:01f31e923fe2 | 460 | * @brief Real-Time Clock |
| Pawel Zarembski |
0:01f31e923fe2 | 461 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 462 | |
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0:01f31e923fe2 | 463 | typedef struct |
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0:01f31e923fe2 | 464 | { |
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0:01f31e923fe2 | 465 | __IO uint32_t CRH; |
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0:01f31e923fe2 | 466 | __IO uint32_t CRL; |
| Pawel Zarembski |
0:01f31e923fe2 | 467 | __IO uint32_t PRLH; |
| Pawel Zarembski |
0:01f31e923fe2 | 468 | __IO uint32_t PRLL; |
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0:01f31e923fe2 | 469 | __IO uint32_t DIVH; |
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0:01f31e923fe2 | 470 | __IO uint32_t DIVL; |
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0:01f31e923fe2 | 471 | __IO uint32_t CNTH; |
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0:01f31e923fe2 | 472 | __IO uint32_t CNTL; |
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0:01f31e923fe2 | 473 | __IO uint32_t ALRH; |
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0:01f31e923fe2 | 474 | __IO uint32_t ALRL; |
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0:01f31e923fe2 | 475 | } RTC_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 476 | |
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0:01f31e923fe2 | 477 | /** |
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0:01f31e923fe2 | 478 | * @brief SD host Interface |
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0:01f31e923fe2 | 479 | */ |
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0:01f31e923fe2 | 480 | |
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0:01f31e923fe2 | 481 | typedef struct |
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0:01f31e923fe2 | 482 | { |
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0:01f31e923fe2 | 483 | __IO uint32_t POWER; |
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0:01f31e923fe2 | 484 | __IO uint32_t CLKCR; |
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0:01f31e923fe2 | 485 | __IO uint32_t ARG; |
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0:01f31e923fe2 | 486 | __IO uint32_t CMD; |
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0:01f31e923fe2 | 487 | __I uint32_t RESPCMD; |
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0:01f31e923fe2 | 488 | __I uint32_t RESP1; |
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0:01f31e923fe2 | 489 | __I uint32_t RESP2; |
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0:01f31e923fe2 | 490 | __I uint32_t RESP3; |
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0:01f31e923fe2 | 491 | __I uint32_t RESP4; |
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0:01f31e923fe2 | 492 | __IO uint32_t DTIMER; |
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0:01f31e923fe2 | 493 | __IO uint32_t DLEN; |
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0:01f31e923fe2 | 494 | __IO uint32_t DCTRL; |
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0:01f31e923fe2 | 495 | __I uint32_t DCOUNT; |
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0:01f31e923fe2 | 496 | __I uint32_t STA; |
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0:01f31e923fe2 | 497 | __IO uint32_t ICR; |
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0:01f31e923fe2 | 498 | __IO uint32_t MASK; |
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0:01f31e923fe2 | 499 | uint32_t RESERVED0[2]; |
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0:01f31e923fe2 | 500 | __I uint32_t FIFOCNT; |
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0:01f31e923fe2 | 501 | uint32_t RESERVED1[13]; |
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0:01f31e923fe2 | 502 | __IO uint32_t FIFO; |
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0:01f31e923fe2 | 503 | } SDIO_TypeDef; |
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0:01f31e923fe2 | 504 | |
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0:01f31e923fe2 | 505 | /** |
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0:01f31e923fe2 | 506 | * @brief Serial Peripheral Interface |
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0:01f31e923fe2 | 507 | */ |
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0:01f31e923fe2 | 508 | |
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0:01f31e923fe2 | 509 | typedef struct |
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0:01f31e923fe2 | 510 | { |
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0:01f31e923fe2 | 511 | __IO uint32_t CR1; |
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0:01f31e923fe2 | 512 | __IO uint32_t CR2; |
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0:01f31e923fe2 | 513 | __IO uint32_t SR; |
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0:01f31e923fe2 | 514 | __IO uint32_t DR; |
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0:01f31e923fe2 | 515 | __IO uint32_t CRCPR; |
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0:01f31e923fe2 | 516 | __IO uint32_t RXCRCR; |
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0:01f31e923fe2 | 517 | __IO uint32_t TXCRCR; |
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0:01f31e923fe2 | 518 | __IO uint32_t I2SCFGR; |
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0:01f31e923fe2 | 519 | } SPI_TypeDef; |
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0:01f31e923fe2 | 520 | |
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0:01f31e923fe2 | 521 | /** |
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0:01f31e923fe2 | 522 | * @brief TIM Timers |
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0:01f31e923fe2 | 523 | */ |
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0:01f31e923fe2 | 524 | typedef struct |
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0:01f31e923fe2 | 525 | { |
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0:01f31e923fe2 | 526 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 527 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 528 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 529 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 530 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 531 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 532 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 533 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 534 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 535 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 536 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 537 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 538 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 539 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 540 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 541 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 542 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 543 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 544 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 545 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 546 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 547 | }TIM_TypeDef; |
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0:01f31e923fe2 | 548 | |
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0:01f31e923fe2 | 549 | |
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0:01f31e923fe2 | 550 | /** |
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0:01f31e923fe2 | 551 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
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0:01f31e923fe2 | 552 | */ |
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0:01f31e923fe2 | 553 | |
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0:01f31e923fe2 | 554 | typedef struct |
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0:01f31e923fe2 | 555 | { |
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0:01f31e923fe2 | 556 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 557 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 558 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 559 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 560 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 561 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 562 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 563 | } USART_TypeDef; |
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0:01f31e923fe2 | 564 | |
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0:01f31e923fe2 | 565 | /** |
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0:01f31e923fe2 | 566 | * @brief Universal Serial Bus Full Speed Device |
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0:01f31e923fe2 | 567 | */ |
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0:01f31e923fe2 | 568 | |
| Pawel Zarembski |
0:01f31e923fe2 | 569 | typedef struct |
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0:01f31e923fe2 | 570 | { |
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0:01f31e923fe2 | 571 | __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 572 | __IO uint16_t RESERVED0; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 573 | __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 574 | __IO uint16_t RESERVED1; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 575 | __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 576 | __IO uint16_t RESERVED2; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 577 | __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 578 | __IO uint16_t RESERVED3; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 579 | __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 580 | __IO uint16_t RESERVED4; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 581 | __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 582 | __IO uint16_t RESERVED5; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 583 | __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 584 | __IO uint16_t RESERVED6; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 585 | __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 586 | __IO uint16_t RESERVED7[17]; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 587 | __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 588 | __IO uint16_t RESERVED8; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 589 | __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 590 | __IO uint16_t RESERVED9; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 591 | __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 592 | __IO uint16_t RESERVEDA; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 593 | __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 594 | __IO uint16_t RESERVEDB; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 595 | __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 596 | __IO uint16_t RESERVEDC; /*!< Reserved */ |
| Pawel Zarembski |
0:01f31e923fe2 | 597 | } USB_TypeDef; |
| Pawel Zarembski |
0:01f31e923fe2 | 598 | |
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0:01f31e923fe2 | 599 | |
| Pawel Zarembski |
0:01f31e923fe2 | 600 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 601 | * @brief Window WATCHDOG |
| Pawel Zarembski |
0:01f31e923fe2 | 602 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 603 | |
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0:01f31e923fe2 | 604 | typedef struct |
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0:01f31e923fe2 | 605 | { |
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0:01f31e923fe2 | 606 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 607 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 608 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 609 | } WWDG_TypeDef; |
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0:01f31e923fe2 | 610 | |
| Pawel Zarembski |
0:01f31e923fe2 | 611 | /** |
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0:01f31e923fe2 | 612 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 613 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 614 | |
| Pawel Zarembski |
0:01f31e923fe2 | 615 | /** @addtogroup Peripheral_memory_map |
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0:01f31e923fe2 | 616 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 617 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 618 | |
| Pawel Zarembski |
0:01f31e923fe2 | 619 | |
| Pawel Zarembski |
0:01f31e923fe2 | 620 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
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0:01f31e923fe2 | 621 | #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ |
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0:01f31e923fe2 | 622 | #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
| Pawel Zarembski |
0:01f31e923fe2 | 623 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
| Pawel Zarembski |
0:01f31e923fe2 | 624 | |
| Pawel Zarembski |
0:01f31e923fe2 | 625 | #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
| Pawel Zarembski |
0:01f31e923fe2 | 626 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
| Pawel Zarembski |
0:01f31e923fe2 | 627 | |
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0:01f31e923fe2 | 628 | |
| Pawel Zarembski |
0:01f31e923fe2 | 629 | /*!< Peripheral memory map */ |
| Pawel Zarembski |
0:01f31e923fe2 | 630 | #define APB1PERIPH_BASE PERIPH_BASE |
| Pawel Zarembski |
0:01f31e923fe2 | 631 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| Pawel Zarembski |
0:01f31e923fe2 | 632 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| Pawel Zarembski |
0:01f31e923fe2 | 633 | |
| Pawel Zarembski |
0:01f31e923fe2 | 634 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| Pawel Zarembski |
0:01f31e923fe2 | 635 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| Pawel Zarembski |
0:01f31e923fe2 | 636 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| Pawel Zarembski |
0:01f31e923fe2 | 637 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| Pawel Zarembski |
0:01f31e923fe2 | 638 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| Pawel Zarembski |
0:01f31e923fe2 | 639 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| Pawel Zarembski |
0:01f31e923fe2 | 640 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| Pawel Zarembski |
0:01f31e923fe2 | 641 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| Pawel Zarembski |
0:01f31e923fe2 | 642 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| Pawel Zarembski |
0:01f31e923fe2 | 643 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| Pawel Zarembski |
0:01f31e923fe2 | 644 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
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0:01f31e923fe2 | 645 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
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0:01f31e923fe2 | 646 | #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
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0:01f31e923fe2 | 647 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| Pawel Zarembski |
0:01f31e923fe2 | 648 | #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
| Pawel Zarembski |
0:01f31e923fe2 | 649 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
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0:01f31e923fe2 | 650 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
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0:01f31e923fe2 | 651 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
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0:01f31e923fe2 | 652 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
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0:01f31e923fe2 | 653 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
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0:01f31e923fe2 | 654 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
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0:01f31e923fe2 | 655 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
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0:01f31e923fe2 | 656 | #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
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0:01f31e923fe2 | 657 | #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
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0:01f31e923fe2 | 658 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
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0:01f31e923fe2 | 659 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
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0:01f31e923fe2 | 660 | |
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0:01f31e923fe2 | 661 | #define SDIO_BASE (PERIPH_BASE + 0x18000) |
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0:01f31e923fe2 | 662 | |
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0:01f31e923fe2 | 663 | #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
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0:01f31e923fe2 | 664 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
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0:01f31e923fe2 | 665 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
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0:01f31e923fe2 | 666 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
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0:01f31e923fe2 | 667 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
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0:01f31e923fe2 | 668 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
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0:01f31e923fe2 | 669 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
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0:01f31e923fe2 | 670 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
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0:01f31e923fe2 | 671 | #define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
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0:01f31e923fe2 | 672 | #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
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0:01f31e923fe2 | 673 | |
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0:01f31e923fe2 | 674 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
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0:01f31e923fe2 | 675 | #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */ |
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0:01f31e923fe2 | 676 | #define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */ |
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0:01f31e923fe2 | 677 | #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
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0:01f31e923fe2 | 678 | |
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0:01f31e923fe2 | 679 | |
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0:01f31e923fe2 | 680 | |
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0:01f31e923fe2 | 681 | #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
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0:01f31e923fe2 | 682 | |
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0:01f31e923fe2 | 683 | /* USB device FS */ |
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0:01f31e923fe2 | 684 | #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ |
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0:01f31e923fe2 | 685 | #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ |
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0:01f31e923fe2 | 686 | |
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0:01f31e923fe2 | 687 | |
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0:01f31e923fe2 | 688 | /** |
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0:01f31e923fe2 | 689 | * @} |
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0:01f31e923fe2 | 690 | */ |
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0:01f31e923fe2 | 691 | |
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0:01f31e923fe2 | 692 | /** @addtogroup Peripheral_declaration |
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0:01f31e923fe2 | 693 | * @{ |
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0:01f31e923fe2 | 694 | */ |
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0:01f31e923fe2 | 695 | |
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0:01f31e923fe2 | 696 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
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0:01f31e923fe2 | 697 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
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0:01f31e923fe2 | 698 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
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0:01f31e923fe2 | 699 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
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0:01f31e923fe2 | 700 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
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0:01f31e923fe2 | 701 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
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0:01f31e923fe2 | 702 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
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0:01f31e923fe2 | 703 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
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0:01f31e923fe2 | 704 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
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0:01f31e923fe2 | 705 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
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0:01f31e923fe2 | 706 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
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0:01f31e923fe2 | 707 | #define USB ((USB_TypeDef *) USB_BASE) |
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0:01f31e923fe2 | 708 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
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0:01f31e923fe2 | 709 | #define BKP ((BKP_TypeDef *) BKP_BASE) |
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0:01f31e923fe2 | 710 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
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0:01f31e923fe2 | 711 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
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0:01f31e923fe2 | 712 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
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0:01f31e923fe2 | 713 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
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0:01f31e923fe2 | 714 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
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0:01f31e923fe2 | 715 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
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0:01f31e923fe2 | 716 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
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0:01f31e923fe2 | 717 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
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0:01f31e923fe2 | 718 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
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0:01f31e923fe2 | 719 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
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0:01f31e923fe2 | 720 | #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE) |
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0:01f31e923fe2 | 721 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
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0:01f31e923fe2 | 722 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
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0:01f31e923fe2 | 723 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
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0:01f31e923fe2 | 724 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
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0:01f31e923fe2 | 725 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
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0:01f31e923fe2 | 726 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
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0:01f31e923fe2 | 727 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
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0:01f31e923fe2 | 728 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
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0:01f31e923fe2 | 729 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
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0:01f31e923fe2 | 730 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
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0:01f31e923fe2 | 731 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
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0:01f31e923fe2 | 732 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
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0:01f31e923fe2 | 733 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
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0:01f31e923fe2 | 734 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
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0:01f31e923fe2 | 735 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
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0:01f31e923fe2 | 736 | #define OB ((OB_TypeDef *) OB_BASE) |
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0:01f31e923fe2 | 737 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
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0:01f31e923fe2 | 738 | |
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0:01f31e923fe2 | 739 | |
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0:01f31e923fe2 | 740 | /** |
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0:01f31e923fe2 | 741 | * @} |
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0:01f31e923fe2 | 742 | */ |
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0:01f31e923fe2 | 743 | |
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0:01f31e923fe2 | 744 | /** @addtogroup Exported_constants |
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0:01f31e923fe2 | 745 | * @{ |
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0:01f31e923fe2 | 746 | */ |
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0:01f31e923fe2 | 747 | |
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0:01f31e923fe2 | 748 | /** @addtogroup Peripheral_Registers_Bits_Definition |
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0:01f31e923fe2 | 749 | * @{ |
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0:01f31e923fe2 | 750 | */ |
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0:01f31e923fe2 | 751 | |
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0:01f31e923fe2 | 752 | /******************************************************************************/ |
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0:01f31e923fe2 | 753 | /* Peripheral Registers_Bits_Definition */ |
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0:01f31e923fe2 | 754 | /******************************************************************************/ |
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0:01f31e923fe2 | 755 | |
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0:01f31e923fe2 | 756 | /******************************************************************************/ |
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0:01f31e923fe2 | 757 | /* */ |
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0:01f31e923fe2 | 758 | /* CRC calculation unit (CRC) */ |
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0:01f31e923fe2 | 759 | /* */ |
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0:01f31e923fe2 | 760 | /******************************************************************************/ |
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0:01f31e923fe2 | 761 | |
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0:01f31e923fe2 | 762 | /******************* Bit definition for CRC_DR register *********************/ |
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0:01f31e923fe2 | 763 | #define CRC_DR_DR_Pos (0U) |
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0:01f31e923fe2 | 764 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 765 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
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0:01f31e923fe2 | 766 | |
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0:01f31e923fe2 | 767 | /******************* Bit definition for CRC_IDR register ********************/ |
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0:01f31e923fe2 | 768 | #define CRC_IDR_IDR_Pos (0U) |
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0:01f31e923fe2 | 769 | #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
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0:01f31e923fe2 | 770 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
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0:01f31e923fe2 | 771 | |
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0:01f31e923fe2 | 772 | /******************** Bit definition for CRC_CR register ********************/ |
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0:01f31e923fe2 | 773 | #define CRC_CR_RESET_Pos (0U) |
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0:01f31e923fe2 | 774 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 775 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
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0:01f31e923fe2 | 776 | |
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0:01f31e923fe2 | 777 | /******************************************************************************/ |
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0:01f31e923fe2 | 778 | /* */ |
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0:01f31e923fe2 | 779 | /* Power Control */ |
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0:01f31e923fe2 | 780 | /* */ |
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0:01f31e923fe2 | 781 | /******************************************************************************/ |
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0:01f31e923fe2 | 782 | |
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0:01f31e923fe2 | 783 | /******************** Bit definition for PWR_CR register ********************/ |
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0:01f31e923fe2 | 784 | #define PWR_CR_LPDS_Pos (0U) |
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0:01f31e923fe2 | 785 | #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 786 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ |
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0:01f31e923fe2 | 787 | #define PWR_CR_PDDS_Pos (1U) |
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0:01f31e923fe2 | 788 | #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 789 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
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0:01f31e923fe2 | 790 | #define PWR_CR_CWUF_Pos (2U) |
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0:01f31e923fe2 | 791 | #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 792 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
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0:01f31e923fe2 | 793 | #define PWR_CR_CSBF_Pos (3U) |
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0:01f31e923fe2 | 794 | #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 795 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
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0:01f31e923fe2 | 796 | #define PWR_CR_PVDE_Pos (4U) |
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0:01f31e923fe2 | 797 | #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 798 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
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0:01f31e923fe2 | 799 | |
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0:01f31e923fe2 | 800 | #define PWR_CR_PLS_Pos (5U) |
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0:01f31e923fe2 | 801 | #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
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0:01f31e923fe2 | 802 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
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0:01f31e923fe2 | 803 | #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 804 | #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 805 | #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 806 | |
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0:01f31e923fe2 | 807 | /*!< PVD level configuration */ |
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0:01f31e923fe2 | 808 | #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ |
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0:01f31e923fe2 | 809 | #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ |
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0:01f31e923fe2 | 810 | #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ |
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0:01f31e923fe2 | 811 | #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ |
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0:01f31e923fe2 | 812 | #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ |
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0:01f31e923fe2 | 813 | #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ |
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0:01f31e923fe2 | 814 | #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ |
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0:01f31e923fe2 | 815 | #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ |
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0:01f31e923fe2 | 816 | |
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0:01f31e923fe2 | 817 | #define PWR_CR_DBP_Pos (8U) |
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0:01f31e923fe2 | 818 | #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 819 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
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0:01f31e923fe2 | 820 | |
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0:01f31e923fe2 | 821 | |
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0:01f31e923fe2 | 822 | /******************* Bit definition for PWR_CSR register ********************/ |
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0:01f31e923fe2 | 823 | #define PWR_CSR_WUF_Pos (0U) |
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0:01f31e923fe2 | 824 | #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 825 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
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0:01f31e923fe2 | 826 | #define PWR_CSR_SBF_Pos (1U) |
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0:01f31e923fe2 | 827 | #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 828 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
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0:01f31e923fe2 | 829 | #define PWR_CSR_PVDO_Pos (2U) |
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0:01f31e923fe2 | 830 | #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 831 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
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0:01f31e923fe2 | 832 | #define PWR_CSR_EWUP_Pos (8U) |
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0:01f31e923fe2 | 833 | #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 834 | #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ |
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0:01f31e923fe2 | 835 | |
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0:01f31e923fe2 | 836 | /******************************************************************************/ |
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0:01f31e923fe2 | 837 | /* */ |
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0:01f31e923fe2 | 838 | /* Backup registers */ |
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0:01f31e923fe2 | 839 | /* */ |
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0:01f31e923fe2 | 840 | /******************************************************************************/ |
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0:01f31e923fe2 | 841 | |
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0:01f31e923fe2 | 842 | /******************* Bit definition for BKP_DR1 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 843 | #define BKP_DR1_D_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 844 | #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 845 | #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 846 | |
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0:01f31e923fe2 | 847 | /******************* Bit definition for BKP_DR2 register ********************/ |
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0:01f31e923fe2 | 848 | #define BKP_DR2_D_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 849 | #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 850 | #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 851 | |
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0:01f31e923fe2 | 852 | /******************* Bit definition for BKP_DR3 register ********************/ |
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0:01f31e923fe2 | 853 | #define BKP_DR3_D_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 854 | #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 855 | #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 856 | |
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0:01f31e923fe2 | 857 | /******************* Bit definition for BKP_DR4 register ********************/ |
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0:01f31e923fe2 | 858 | #define BKP_DR4_D_Pos (0U) |
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0:01f31e923fe2 | 859 | #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 860 | #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 861 | |
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0:01f31e923fe2 | 862 | /******************* Bit definition for BKP_DR5 register ********************/ |
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0:01f31e923fe2 | 863 | #define BKP_DR5_D_Pos (0U) |
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0:01f31e923fe2 | 864 | #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 865 | #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 866 | |
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0:01f31e923fe2 | 867 | /******************* Bit definition for BKP_DR6 register ********************/ |
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0:01f31e923fe2 | 868 | #define BKP_DR6_D_Pos (0U) |
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0:01f31e923fe2 | 869 | #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ |
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0:01f31e923fe2 | 870 | #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ |
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0:01f31e923fe2 | 871 | |
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0:01f31e923fe2 | 872 | /******************* Bit definition for BKP_DR7 register ********************/ |
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0:01f31e923fe2 | 873 | #define BKP_DR7_D_Pos (0U) |
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0:01f31e923fe2 | 874 | #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 875 | #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ |
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0:01f31e923fe2 | 876 | |
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0:01f31e923fe2 | 877 | /******************* Bit definition for BKP_DR8 register ********************/ |
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0:01f31e923fe2 | 878 | #define BKP_DR8_D_Pos (0U) |
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0:01f31e923fe2 | 879 | #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 880 | #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ |
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0:01f31e923fe2 | 881 | |
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0:01f31e923fe2 | 882 | /******************* Bit definition for BKP_DR9 register ********************/ |
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0:01f31e923fe2 | 883 | #define BKP_DR9_D_Pos (0U) |
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0:01f31e923fe2 | 884 | #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ |
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0:01f31e923fe2 | 885 | #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ |
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0:01f31e923fe2 | 886 | |
| Pawel Zarembski |
0:01f31e923fe2 | 887 | /******************* Bit definition for BKP_DR10 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 888 | #define BKP_DR10_D_Pos (0U) |
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0:01f31e923fe2 | 889 | #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 890 | #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ |
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0:01f31e923fe2 | 891 | |
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0:01f31e923fe2 | 892 | #define RTC_BKP_NUMBER 10 |
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0:01f31e923fe2 | 893 | |
| Pawel Zarembski |
0:01f31e923fe2 | 894 | /****************** Bit definition for BKP_RTCCR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 895 | #define BKP_RTCCR_CAL_Pos (0U) |
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0:01f31e923fe2 | 896 | #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ |
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0:01f31e923fe2 | 897 | #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ |
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0:01f31e923fe2 | 898 | #define BKP_RTCCR_CCO_Pos (7U) |
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0:01f31e923fe2 | 899 | #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 900 | #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ |
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0:01f31e923fe2 | 901 | #define BKP_RTCCR_ASOE_Pos (8U) |
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0:01f31e923fe2 | 902 | #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 903 | #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ |
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0:01f31e923fe2 | 904 | #define BKP_RTCCR_ASOS_Pos (9U) |
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0:01f31e923fe2 | 905 | #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 906 | #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ |
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0:01f31e923fe2 | 907 | |
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0:01f31e923fe2 | 908 | /******************** Bit definition for BKP_CR register ********************/ |
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0:01f31e923fe2 | 909 | #define BKP_CR_TPE_Pos (0U) |
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0:01f31e923fe2 | 910 | #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 911 | #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 912 | #define BKP_CR_TPAL_Pos (1U) |
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0:01f31e923fe2 | 913 | #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 914 | #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ |
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0:01f31e923fe2 | 915 | |
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0:01f31e923fe2 | 916 | /******************* Bit definition for BKP_CSR register ********************/ |
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0:01f31e923fe2 | 917 | #define BKP_CSR_CTE_Pos (0U) |
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0:01f31e923fe2 | 918 | #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 919 | #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ |
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0:01f31e923fe2 | 920 | #define BKP_CSR_CTI_Pos (1U) |
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0:01f31e923fe2 | 921 | #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 922 | #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ |
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0:01f31e923fe2 | 923 | #define BKP_CSR_TPIE_Pos (2U) |
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0:01f31e923fe2 | 924 | #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 925 | #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ |
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0:01f31e923fe2 | 926 | #define BKP_CSR_TEF_Pos (8U) |
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0:01f31e923fe2 | 927 | #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 928 | #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ |
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0:01f31e923fe2 | 929 | #define BKP_CSR_TIF_Pos (9U) |
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0:01f31e923fe2 | 930 | #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 931 | #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ |
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0:01f31e923fe2 | 932 | |
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0:01f31e923fe2 | 933 | /******************************************************************************/ |
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0:01f31e923fe2 | 934 | /* */ |
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0:01f31e923fe2 | 935 | /* Reset and Clock Control */ |
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0:01f31e923fe2 | 936 | /* */ |
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0:01f31e923fe2 | 937 | /******************************************************************************/ |
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0:01f31e923fe2 | 938 | |
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0:01f31e923fe2 | 939 | /******************** Bit definition for RCC_CR register ********************/ |
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0:01f31e923fe2 | 940 | #define RCC_CR_HSION_Pos (0U) |
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0:01f31e923fe2 | 941 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 942 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ |
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0:01f31e923fe2 | 943 | #define RCC_CR_HSIRDY_Pos (1U) |
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0:01f31e923fe2 | 944 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 945 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ |
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0:01f31e923fe2 | 946 | #define RCC_CR_HSITRIM_Pos (3U) |
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0:01f31e923fe2 | 947 | #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ |
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0:01f31e923fe2 | 948 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ |
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0:01f31e923fe2 | 949 | #define RCC_CR_HSICAL_Pos (8U) |
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0:01f31e923fe2 | 950 | #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ |
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0:01f31e923fe2 | 951 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ |
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0:01f31e923fe2 | 952 | #define RCC_CR_HSEON_Pos (16U) |
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0:01f31e923fe2 | 953 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 954 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ |
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0:01f31e923fe2 | 955 | #define RCC_CR_HSERDY_Pos (17U) |
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0:01f31e923fe2 | 956 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 957 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ |
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0:01f31e923fe2 | 958 | #define RCC_CR_HSEBYP_Pos (18U) |
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0:01f31e923fe2 | 959 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 960 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ |
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0:01f31e923fe2 | 961 | #define RCC_CR_CSSON_Pos (19U) |
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0:01f31e923fe2 | 962 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 963 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ |
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0:01f31e923fe2 | 964 | #define RCC_CR_PLLON_Pos (24U) |
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0:01f31e923fe2 | 965 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 966 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ |
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0:01f31e923fe2 | 967 | #define RCC_CR_PLLRDY_Pos (25U) |
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0:01f31e923fe2 | 968 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 969 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ |
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0:01f31e923fe2 | 970 | |
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0:01f31e923fe2 | 971 | |
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0:01f31e923fe2 | 972 | /******************* Bit definition for RCC_CFGR register *******************/ |
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0:01f31e923fe2 | 973 | /*!< SW configuration */ |
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0:01f31e923fe2 | 974 | #define RCC_CFGR_SW_Pos (0U) |
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0:01f31e923fe2 | 975 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
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0:01f31e923fe2 | 976 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
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0:01f31e923fe2 | 977 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 978 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 979 | |
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0:01f31e923fe2 | 980 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
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0:01f31e923fe2 | 981 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
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0:01f31e923fe2 | 982 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
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0:01f31e923fe2 | 983 | |
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0:01f31e923fe2 | 984 | /*!< SWS configuration */ |
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0:01f31e923fe2 | 985 | #define RCC_CFGR_SWS_Pos (2U) |
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0:01f31e923fe2 | 986 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
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0:01f31e923fe2 | 987 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
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0:01f31e923fe2 | 988 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 989 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 990 | |
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0:01f31e923fe2 | 991 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
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0:01f31e923fe2 | 992 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
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0:01f31e923fe2 | 993 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
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0:01f31e923fe2 | 994 | |
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0:01f31e923fe2 | 995 | /*!< HPRE configuration */ |
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0:01f31e923fe2 | 996 | #define RCC_CFGR_HPRE_Pos (4U) |
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0:01f31e923fe2 | 997 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
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0:01f31e923fe2 | 998 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
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0:01f31e923fe2 | 999 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1000 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1001 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1002 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1003 | |
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0:01f31e923fe2 | 1004 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
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0:01f31e923fe2 | 1005 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
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0:01f31e923fe2 | 1006 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
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0:01f31e923fe2 | 1007 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
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0:01f31e923fe2 | 1008 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
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0:01f31e923fe2 | 1009 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
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0:01f31e923fe2 | 1010 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
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0:01f31e923fe2 | 1011 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
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0:01f31e923fe2 | 1012 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
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0:01f31e923fe2 | 1013 | |
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0:01f31e923fe2 | 1014 | /*!< PPRE1 configuration */ |
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0:01f31e923fe2 | 1015 | #define RCC_CFGR_PPRE1_Pos (8U) |
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0:01f31e923fe2 | 1016 | #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
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0:01f31e923fe2 | 1017 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
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0:01f31e923fe2 | 1018 | #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1019 | #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1020 | #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1021 | |
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0:01f31e923fe2 | 1022 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
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0:01f31e923fe2 | 1023 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
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0:01f31e923fe2 | 1024 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
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0:01f31e923fe2 | 1025 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
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0:01f31e923fe2 | 1026 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
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0:01f31e923fe2 | 1027 | |
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0:01f31e923fe2 | 1028 | /*!< PPRE2 configuration */ |
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0:01f31e923fe2 | 1029 | #define RCC_CFGR_PPRE2_Pos (11U) |
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0:01f31e923fe2 | 1030 | #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
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0:01f31e923fe2 | 1031 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
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0:01f31e923fe2 | 1032 | #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1033 | #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1034 | #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1035 | |
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0:01f31e923fe2 | 1036 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
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0:01f31e923fe2 | 1037 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
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0:01f31e923fe2 | 1038 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
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0:01f31e923fe2 | 1039 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
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0:01f31e923fe2 | 1040 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
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0:01f31e923fe2 | 1041 | |
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0:01f31e923fe2 | 1042 | /*!< ADCPPRE configuration */ |
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0:01f31e923fe2 | 1043 | #define RCC_CFGR_ADCPRE_Pos (14U) |
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0:01f31e923fe2 | 1044 | #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ |
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0:01f31e923fe2 | 1045 | #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
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0:01f31e923fe2 | 1046 | #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1047 | #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1048 | |
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0:01f31e923fe2 | 1049 | #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
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0:01f31e923fe2 | 1050 | #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
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0:01f31e923fe2 | 1051 | #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
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0:01f31e923fe2 | 1052 | #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
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0:01f31e923fe2 | 1053 | |
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0:01f31e923fe2 | 1054 | #define RCC_CFGR_PLLSRC_Pos (16U) |
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0:01f31e923fe2 | 1055 | #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1056 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
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0:01f31e923fe2 | 1057 | |
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0:01f31e923fe2 | 1058 | #define RCC_CFGR_PLLXTPRE_Pos (17U) |
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0:01f31e923fe2 | 1059 | #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1060 | #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ |
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0:01f31e923fe2 | 1061 | |
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0:01f31e923fe2 | 1062 | /*!< PLLMUL configuration */ |
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0:01f31e923fe2 | 1063 | #define RCC_CFGR_PLLMULL_Pos (18U) |
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0:01f31e923fe2 | 1064 | #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ |
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0:01f31e923fe2 | 1065 | #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
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0:01f31e923fe2 | 1066 | #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1067 | #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 1068 | #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 1069 | #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1070 | |
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0:01f31e923fe2 | 1071 | #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
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0:01f31e923fe2 | 1072 | #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
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0:01f31e923fe2 | 1073 | |
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0:01f31e923fe2 | 1074 | #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
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0:01f31e923fe2 | 1075 | #define RCC_CFGR_PLLMULL3_Pos (18U) |
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0:01f31e923fe2 | 1076 | #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1077 | #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ |
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0:01f31e923fe2 | 1078 | #define RCC_CFGR_PLLMULL4_Pos (19U) |
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0:01f31e923fe2 | 1079 | #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 1080 | #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ |
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0:01f31e923fe2 | 1081 | #define RCC_CFGR_PLLMULL5_Pos (18U) |
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0:01f31e923fe2 | 1082 | #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ |
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0:01f31e923fe2 | 1083 | #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ |
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0:01f31e923fe2 | 1084 | #define RCC_CFGR_PLLMULL6_Pos (20U) |
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0:01f31e923fe2 | 1085 | #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 1086 | #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ |
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0:01f31e923fe2 | 1087 | #define RCC_CFGR_PLLMULL7_Pos (18U) |
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0:01f31e923fe2 | 1088 | #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ |
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0:01f31e923fe2 | 1089 | #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ |
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0:01f31e923fe2 | 1090 | #define RCC_CFGR_PLLMULL8_Pos (19U) |
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0:01f31e923fe2 | 1091 | #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ |
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0:01f31e923fe2 | 1092 | #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ |
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0:01f31e923fe2 | 1093 | #define RCC_CFGR_PLLMULL9_Pos (18U) |
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0:01f31e923fe2 | 1094 | #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ |
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0:01f31e923fe2 | 1095 | #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ |
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0:01f31e923fe2 | 1096 | #define RCC_CFGR_PLLMULL10_Pos (21U) |
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0:01f31e923fe2 | 1097 | #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1098 | #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ |
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0:01f31e923fe2 | 1099 | #define RCC_CFGR_PLLMULL11_Pos (18U) |
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0:01f31e923fe2 | 1100 | #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ |
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0:01f31e923fe2 | 1101 | #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ |
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0:01f31e923fe2 | 1102 | #define RCC_CFGR_PLLMULL12_Pos (19U) |
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0:01f31e923fe2 | 1103 | #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ |
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0:01f31e923fe2 | 1104 | #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ |
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0:01f31e923fe2 | 1105 | #define RCC_CFGR_PLLMULL13_Pos (18U) |
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0:01f31e923fe2 | 1106 | #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ |
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0:01f31e923fe2 | 1107 | #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ |
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0:01f31e923fe2 | 1108 | #define RCC_CFGR_PLLMULL14_Pos (20U) |
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0:01f31e923fe2 | 1109 | #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ |
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0:01f31e923fe2 | 1110 | #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ |
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0:01f31e923fe2 | 1111 | #define RCC_CFGR_PLLMULL15_Pos (18U) |
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0:01f31e923fe2 | 1112 | #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ |
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0:01f31e923fe2 | 1113 | #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ |
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0:01f31e923fe2 | 1114 | #define RCC_CFGR_PLLMULL16_Pos (19U) |
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0:01f31e923fe2 | 1115 | #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ |
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0:01f31e923fe2 | 1116 | #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ |
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0:01f31e923fe2 | 1117 | #define RCC_CFGR_USBPRE_Pos (22U) |
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0:01f31e923fe2 | 1118 | #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 1119 | #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ |
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0:01f31e923fe2 | 1120 | |
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0:01f31e923fe2 | 1121 | /*!< MCO configuration */ |
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0:01f31e923fe2 | 1122 | #define RCC_CFGR_MCO_Pos (24U) |
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0:01f31e923fe2 | 1123 | #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ |
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0:01f31e923fe2 | 1124 | #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
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0:01f31e923fe2 | 1125 | #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 1126 | #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 1127 | #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 1128 | |
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0:01f31e923fe2 | 1129 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
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0:01f31e923fe2 | 1130 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
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0:01f31e923fe2 | 1131 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
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0:01f31e923fe2 | 1132 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
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0:01f31e923fe2 | 1133 | #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
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0:01f31e923fe2 | 1134 | |
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0:01f31e923fe2 | 1135 | /* Reference defines */ |
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0:01f31e923fe2 | 1136 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCO |
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0:01f31e923fe2 | 1137 | #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 |
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0:01f31e923fe2 | 1138 | #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 |
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0:01f31e923fe2 | 1139 | #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 |
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0:01f31e923fe2 | 1140 | #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK |
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0:01f31e923fe2 | 1141 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK |
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0:01f31e923fe2 | 1142 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI |
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0:01f31e923fe2 | 1143 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE |
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0:01f31e923fe2 | 1144 | #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 |
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0:01f31e923fe2 | 1145 | |
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0:01f31e923fe2 | 1146 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
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0:01f31e923fe2 | 1147 | #define RCC_CIR_LSIRDYF_Pos (0U) |
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0:01f31e923fe2 | 1148 | #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1149 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ |
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0:01f31e923fe2 | 1150 | #define RCC_CIR_LSERDYF_Pos (1U) |
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0:01f31e923fe2 | 1151 | #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1152 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ |
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0:01f31e923fe2 | 1153 | #define RCC_CIR_HSIRDYF_Pos (2U) |
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0:01f31e923fe2 | 1154 | #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1155 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ |
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0:01f31e923fe2 | 1156 | #define RCC_CIR_HSERDYF_Pos (3U) |
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0:01f31e923fe2 | 1157 | #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1158 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ |
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0:01f31e923fe2 | 1159 | #define RCC_CIR_PLLRDYF_Pos (4U) |
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0:01f31e923fe2 | 1160 | #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1161 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ |
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0:01f31e923fe2 | 1162 | #define RCC_CIR_CSSF_Pos (7U) |
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0:01f31e923fe2 | 1163 | #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1164 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ |
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0:01f31e923fe2 | 1165 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
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0:01f31e923fe2 | 1166 | #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1167 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ |
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0:01f31e923fe2 | 1168 | #define RCC_CIR_LSERDYIE_Pos (9U) |
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0:01f31e923fe2 | 1169 | #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1170 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ |
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0:01f31e923fe2 | 1171 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
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0:01f31e923fe2 | 1172 | #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1173 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ |
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0:01f31e923fe2 | 1174 | #define RCC_CIR_HSERDYIE_Pos (11U) |
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0:01f31e923fe2 | 1175 | #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1176 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ |
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0:01f31e923fe2 | 1177 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
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0:01f31e923fe2 | 1178 | #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1179 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ |
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0:01f31e923fe2 | 1180 | #define RCC_CIR_LSIRDYC_Pos (16U) |
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0:01f31e923fe2 | 1181 | #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1182 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ |
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0:01f31e923fe2 | 1183 | #define RCC_CIR_LSERDYC_Pos (17U) |
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0:01f31e923fe2 | 1184 | #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1185 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ |
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0:01f31e923fe2 | 1186 | #define RCC_CIR_HSIRDYC_Pos (18U) |
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0:01f31e923fe2 | 1187 | #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1188 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ |
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0:01f31e923fe2 | 1189 | #define RCC_CIR_HSERDYC_Pos (19U) |
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0:01f31e923fe2 | 1190 | #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 1191 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ |
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0:01f31e923fe2 | 1192 | #define RCC_CIR_PLLRDYC_Pos (20U) |
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0:01f31e923fe2 | 1193 | #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 1194 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ |
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0:01f31e923fe2 | 1195 | #define RCC_CIR_CSSC_Pos (23U) |
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0:01f31e923fe2 | 1196 | #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 1197 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ |
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0:01f31e923fe2 | 1198 | |
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0:01f31e923fe2 | 1199 | |
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0:01f31e923fe2 | 1200 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
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0:01f31e923fe2 | 1201 | #define RCC_APB2RSTR_AFIORST_Pos (0U) |
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0:01f31e923fe2 | 1202 | #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1203 | #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ |
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0:01f31e923fe2 | 1204 | #define RCC_APB2RSTR_IOPARST_Pos (2U) |
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0:01f31e923fe2 | 1205 | #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1206 | #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ |
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0:01f31e923fe2 | 1207 | #define RCC_APB2RSTR_IOPBRST_Pos (3U) |
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0:01f31e923fe2 | 1208 | #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1209 | #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ |
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0:01f31e923fe2 | 1210 | #define RCC_APB2RSTR_IOPCRST_Pos (4U) |
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0:01f31e923fe2 | 1211 | #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1212 | #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ |
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0:01f31e923fe2 | 1213 | #define RCC_APB2RSTR_IOPDRST_Pos (5U) |
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0:01f31e923fe2 | 1214 | #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1215 | #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ |
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0:01f31e923fe2 | 1216 | #define RCC_APB2RSTR_ADC1RST_Pos (9U) |
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0:01f31e923fe2 | 1217 | #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1218 | #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ |
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0:01f31e923fe2 | 1219 | |
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0:01f31e923fe2 | 1220 | #define RCC_APB2RSTR_ADC2RST_Pos (10U) |
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0:01f31e923fe2 | 1221 | #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1222 | #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ |
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0:01f31e923fe2 | 1223 | |
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0:01f31e923fe2 | 1224 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) |
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0:01f31e923fe2 | 1225 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1226 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ |
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0:01f31e923fe2 | 1227 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
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0:01f31e923fe2 | 1228 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1229 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ |
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0:01f31e923fe2 | 1230 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
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0:01f31e923fe2 | 1231 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1232 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ |
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0:01f31e923fe2 | 1233 | |
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0:01f31e923fe2 | 1234 | |
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0:01f31e923fe2 | 1235 | #define RCC_APB2RSTR_IOPERST_Pos (6U) |
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0:01f31e923fe2 | 1236 | #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1237 | #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ |
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0:01f31e923fe2 | 1238 | |
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0:01f31e923fe2 | 1239 | |
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0:01f31e923fe2 | 1240 | |
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0:01f31e923fe2 | 1241 | |
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0:01f31e923fe2 | 1242 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
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0:01f31e923fe2 | 1243 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
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0:01f31e923fe2 | 1244 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1245 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ |
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0:01f31e923fe2 | 1246 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
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0:01f31e923fe2 | 1247 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1248 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ |
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0:01f31e923fe2 | 1249 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
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0:01f31e923fe2 | 1250 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1251 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ |
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0:01f31e923fe2 | 1252 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
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0:01f31e923fe2 | 1253 | #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1254 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ |
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0:01f31e923fe2 | 1255 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
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0:01f31e923fe2 | 1256 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1257 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ |
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0:01f31e923fe2 | 1258 | |
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0:01f31e923fe2 | 1259 | #define RCC_APB1RSTR_CAN1RST_Pos (25U) |
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0:01f31e923fe2 | 1260 | #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 1261 | #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ |
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0:01f31e923fe2 | 1262 | |
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0:01f31e923fe2 | 1263 | #define RCC_APB1RSTR_BKPRST_Pos (27U) |
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0:01f31e923fe2 | 1264 | #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 1265 | #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ |
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0:01f31e923fe2 | 1266 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
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0:01f31e923fe2 | 1267 | #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 1268 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ |
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0:01f31e923fe2 | 1269 | |
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0:01f31e923fe2 | 1270 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
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0:01f31e923fe2 | 1271 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1272 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ |
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0:01f31e923fe2 | 1273 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
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0:01f31e923fe2 | 1274 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1275 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ |
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0:01f31e923fe2 | 1276 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
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0:01f31e923fe2 | 1277 | #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1278 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ |
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0:01f31e923fe2 | 1279 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
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0:01f31e923fe2 | 1280 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 1281 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ |
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0:01f31e923fe2 | 1282 | |
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0:01f31e923fe2 | 1283 | #define RCC_APB1RSTR_USBRST_Pos (23U) |
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0:01f31e923fe2 | 1284 | #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 1285 | #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ |
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0:01f31e923fe2 | 1286 | |
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0:01f31e923fe2 | 1287 | |
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0:01f31e923fe2 | 1288 | |
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0:01f31e923fe2 | 1289 | |
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0:01f31e923fe2 | 1290 | |
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0:01f31e923fe2 | 1291 | |
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0:01f31e923fe2 | 1292 | /****************** Bit definition for RCC_AHBENR register ******************/ |
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0:01f31e923fe2 | 1293 | #define RCC_AHBENR_DMA1EN_Pos (0U) |
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0:01f31e923fe2 | 1294 | #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1295 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ |
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0:01f31e923fe2 | 1296 | #define RCC_AHBENR_SRAMEN_Pos (2U) |
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0:01f31e923fe2 | 1297 | #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1298 | #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ |
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0:01f31e923fe2 | 1299 | #define RCC_AHBENR_FLITFEN_Pos (4U) |
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0:01f31e923fe2 | 1300 | #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1301 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ |
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0:01f31e923fe2 | 1302 | #define RCC_AHBENR_CRCEN_Pos (6U) |
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0:01f31e923fe2 | 1303 | #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1304 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ |
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0:01f31e923fe2 | 1305 | |
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0:01f31e923fe2 | 1306 | |
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0:01f31e923fe2 | 1307 | |
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0:01f31e923fe2 | 1308 | |
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0:01f31e923fe2 | 1309 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
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0:01f31e923fe2 | 1310 | #define RCC_APB2ENR_AFIOEN_Pos (0U) |
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0:01f31e923fe2 | 1311 | #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1312 | #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ |
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0:01f31e923fe2 | 1313 | #define RCC_APB2ENR_IOPAEN_Pos (2U) |
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0:01f31e923fe2 | 1314 | #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1315 | #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ |
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0:01f31e923fe2 | 1316 | #define RCC_APB2ENR_IOPBEN_Pos (3U) |
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0:01f31e923fe2 | 1317 | #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1318 | #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ |
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0:01f31e923fe2 | 1319 | #define RCC_APB2ENR_IOPCEN_Pos (4U) |
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0:01f31e923fe2 | 1320 | #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1321 | #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ |
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0:01f31e923fe2 | 1322 | #define RCC_APB2ENR_IOPDEN_Pos (5U) |
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0:01f31e923fe2 | 1323 | #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1324 | #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ |
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0:01f31e923fe2 | 1325 | #define RCC_APB2ENR_ADC1EN_Pos (9U) |
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0:01f31e923fe2 | 1326 | #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1327 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ |
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0:01f31e923fe2 | 1328 | |
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0:01f31e923fe2 | 1329 | #define RCC_APB2ENR_ADC2EN_Pos (10U) |
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0:01f31e923fe2 | 1330 | #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1331 | #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ |
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0:01f31e923fe2 | 1332 | |
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0:01f31e923fe2 | 1333 | #define RCC_APB2ENR_TIM1EN_Pos (11U) |
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0:01f31e923fe2 | 1334 | #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1335 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ |
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0:01f31e923fe2 | 1336 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
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0:01f31e923fe2 | 1337 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1338 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ |
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0:01f31e923fe2 | 1339 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
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0:01f31e923fe2 | 1340 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1341 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ |
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0:01f31e923fe2 | 1342 | |
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0:01f31e923fe2 | 1343 | |
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0:01f31e923fe2 | 1344 | #define RCC_APB2ENR_IOPEEN_Pos (6U) |
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0:01f31e923fe2 | 1345 | #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1346 | #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ |
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0:01f31e923fe2 | 1347 | |
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0:01f31e923fe2 | 1348 | |
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0:01f31e923fe2 | 1349 | |
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0:01f31e923fe2 | 1350 | |
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0:01f31e923fe2 | 1351 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
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0:01f31e923fe2 | 1352 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
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0:01f31e923fe2 | 1353 | #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1354 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ |
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0:01f31e923fe2 | 1355 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
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0:01f31e923fe2 | 1356 | #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1357 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ |
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0:01f31e923fe2 | 1358 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
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0:01f31e923fe2 | 1359 | #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1360 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ |
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0:01f31e923fe2 | 1361 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
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0:01f31e923fe2 | 1362 | #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1363 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ |
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0:01f31e923fe2 | 1364 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
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0:01f31e923fe2 | 1365 | #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1366 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ |
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0:01f31e923fe2 | 1367 | |
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0:01f31e923fe2 | 1368 | #define RCC_APB1ENR_CAN1EN_Pos (25U) |
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0:01f31e923fe2 | 1369 | #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 1370 | #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ |
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0:01f31e923fe2 | 1371 | |
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0:01f31e923fe2 | 1372 | #define RCC_APB1ENR_BKPEN_Pos (27U) |
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0:01f31e923fe2 | 1373 | #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 1374 | #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ |
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0:01f31e923fe2 | 1375 | #define RCC_APB1ENR_PWREN_Pos (28U) |
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0:01f31e923fe2 | 1376 | #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 1377 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ |
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0:01f31e923fe2 | 1378 | |
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0:01f31e923fe2 | 1379 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
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0:01f31e923fe2 | 1380 | #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1381 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ |
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0:01f31e923fe2 | 1382 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
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0:01f31e923fe2 | 1383 | #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1384 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ |
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0:01f31e923fe2 | 1385 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
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0:01f31e923fe2 | 1386 | #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1387 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ |
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0:01f31e923fe2 | 1388 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
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0:01f31e923fe2 | 1389 | #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 1390 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ |
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0:01f31e923fe2 | 1391 | |
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0:01f31e923fe2 | 1392 | #define RCC_APB1ENR_USBEN_Pos (23U) |
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0:01f31e923fe2 | 1393 | #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 1394 | #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ |
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0:01f31e923fe2 | 1395 | |
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0:01f31e923fe2 | 1396 | |
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0:01f31e923fe2 | 1397 | |
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0:01f31e923fe2 | 1398 | |
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0:01f31e923fe2 | 1399 | |
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0:01f31e923fe2 | 1400 | |
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0:01f31e923fe2 | 1401 | /******************* Bit definition for RCC_BDCR register *******************/ |
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0:01f31e923fe2 | 1402 | #define RCC_BDCR_LSEON_Pos (0U) |
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0:01f31e923fe2 | 1403 | #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1404 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ |
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0:01f31e923fe2 | 1405 | #define RCC_BDCR_LSERDY_Pos (1U) |
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0:01f31e923fe2 | 1406 | #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1407 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ |
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0:01f31e923fe2 | 1408 | #define RCC_BDCR_LSEBYP_Pos (2U) |
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0:01f31e923fe2 | 1409 | #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1410 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ |
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0:01f31e923fe2 | 1411 | |
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0:01f31e923fe2 | 1412 | #define RCC_BDCR_RTCSEL_Pos (8U) |
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0:01f31e923fe2 | 1413 | #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
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0:01f31e923fe2 | 1414 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
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0:01f31e923fe2 | 1415 | #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1416 | #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1417 | |
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0:01f31e923fe2 | 1418 | /*!< RTC congiguration */ |
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0:01f31e923fe2 | 1419 | #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
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0:01f31e923fe2 | 1420 | #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
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0:01f31e923fe2 | 1421 | #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
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0:01f31e923fe2 | 1422 | #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
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0:01f31e923fe2 | 1423 | |
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0:01f31e923fe2 | 1424 | #define RCC_BDCR_RTCEN_Pos (15U) |
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0:01f31e923fe2 | 1425 | #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1426 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ |
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0:01f31e923fe2 | 1427 | #define RCC_BDCR_BDRST_Pos (16U) |
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0:01f31e923fe2 | 1428 | #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1429 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ |
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0:01f31e923fe2 | 1430 | |
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0:01f31e923fe2 | 1431 | /******************* Bit definition for RCC_CSR register ********************/ |
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0:01f31e923fe2 | 1432 | #define RCC_CSR_LSION_Pos (0U) |
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0:01f31e923fe2 | 1433 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1434 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ |
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0:01f31e923fe2 | 1435 | #define RCC_CSR_LSIRDY_Pos (1U) |
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0:01f31e923fe2 | 1436 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1437 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ |
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0:01f31e923fe2 | 1438 | #define RCC_CSR_RMVF_Pos (24U) |
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0:01f31e923fe2 | 1439 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 1440 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ |
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0:01f31e923fe2 | 1441 | #define RCC_CSR_PINRSTF_Pos (26U) |
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0:01f31e923fe2 | 1442 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 1443 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ |
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0:01f31e923fe2 | 1444 | #define RCC_CSR_PORRSTF_Pos (27U) |
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0:01f31e923fe2 | 1445 | #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 1446 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ |
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0:01f31e923fe2 | 1447 | #define RCC_CSR_SFTRSTF_Pos (28U) |
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0:01f31e923fe2 | 1448 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 1449 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ |
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0:01f31e923fe2 | 1450 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
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0:01f31e923fe2 | 1451 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
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0:01f31e923fe2 | 1452 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ |
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0:01f31e923fe2 | 1453 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
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0:01f31e923fe2 | 1454 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
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0:01f31e923fe2 | 1455 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ |
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0:01f31e923fe2 | 1456 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
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0:01f31e923fe2 | 1457 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
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0:01f31e923fe2 | 1458 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ |
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0:01f31e923fe2 | 1459 | |
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0:01f31e923fe2 | 1460 | |
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0:01f31e923fe2 | 1461 | |
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0:01f31e923fe2 | 1462 | /******************************************************************************/ |
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0:01f31e923fe2 | 1463 | /* */ |
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0:01f31e923fe2 | 1464 | /* General Purpose and Alternate Function I/O */ |
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0:01f31e923fe2 | 1465 | /* */ |
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0:01f31e923fe2 | 1466 | /******************************************************************************/ |
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0:01f31e923fe2 | 1467 | |
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0:01f31e923fe2 | 1468 | /******************* Bit definition for GPIO_CRL register *******************/ |
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0:01f31e923fe2 | 1469 | #define GPIO_CRL_MODE_Pos (0U) |
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0:01f31e923fe2 | 1470 | #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ |
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0:01f31e923fe2 | 1471 | #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ |
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0:01f31e923fe2 | 1472 | |
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0:01f31e923fe2 | 1473 | #define GPIO_CRL_MODE0_Pos (0U) |
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0:01f31e923fe2 | 1474 | #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ |
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0:01f31e923fe2 | 1475 | #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
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0:01f31e923fe2 | 1476 | #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1477 | #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1478 | |
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0:01f31e923fe2 | 1479 | #define GPIO_CRL_MODE1_Pos (4U) |
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0:01f31e923fe2 | 1480 | #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ |
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0:01f31e923fe2 | 1481 | #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
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0:01f31e923fe2 | 1482 | #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1483 | #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1484 | |
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0:01f31e923fe2 | 1485 | #define GPIO_CRL_MODE2_Pos (8U) |
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0:01f31e923fe2 | 1486 | #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ |
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0:01f31e923fe2 | 1487 | #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
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0:01f31e923fe2 | 1488 | #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1489 | #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1490 | |
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0:01f31e923fe2 | 1491 | #define GPIO_CRL_MODE3_Pos (12U) |
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0:01f31e923fe2 | 1492 | #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ |
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0:01f31e923fe2 | 1493 | #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
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0:01f31e923fe2 | 1494 | #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1495 | #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1496 | |
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0:01f31e923fe2 | 1497 | #define GPIO_CRL_MODE4_Pos (16U) |
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0:01f31e923fe2 | 1498 | #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ |
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0:01f31e923fe2 | 1499 | #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
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0:01f31e923fe2 | 1500 | #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1501 | #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1502 | |
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0:01f31e923fe2 | 1503 | #define GPIO_CRL_MODE5_Pos (20U) |
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0:01f31e923fe2 | 1504 | #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ |
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0:01f31e923fe2 | 1505 | #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
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0:01f31e923fe2 | 1506 | #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 1507 | #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1508 | |
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0:01f31e923fe2 | 1509 | #define GPIO_CRL_MODE6_Pos (24U) |
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0:01f31e923fe2 | 1510 | #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ |
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0:01f31e923fe2 | 1511 | #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
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0:01f31e923fe2 | 1512 | #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 1513 | #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 1514 | |
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0:01f31e923fe2 | 1515 | #define GPIO_CRL_MODE7_Pos (28U) |
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0:01f31e923fe2 | 1516 | #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ |
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0:01f31e923fe2 | 1517 | #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
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0:01f31e923fe2 | 1518 | #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 1519 | #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ |
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0:01f31e923fe2 | 1520 | |
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0:01f31e923fe2 | 1521 | #define GPIO_CRL_CNF_Pos (2U) |
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0:01f31e923fe2 | 1522 | #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ |
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0:01f31e923fe2 | 1523 | #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ |
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0:01f31e923fe2 | 1524 | |
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0:01f31e923fe2 | 1525 | #define GPIO_CRL_CNF0_Pos (2U) |
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0:01f31e923fe2 | 1526 | #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ |
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0:01f31e923fe2 | 1527 | #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
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0:01f31e923fe2 | 1528 | #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1529 | #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1530 | |
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0:01f31e923fe2 | 1531 | #define GPIO_CRL_CNF1_Pos (6U) |
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0:01f31e923fe2 | 1532 | #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ |
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0:01f31e923fe2 | 1533 | #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
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0:01f31e923fe2 | 1534 | #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1535 | #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1536 | |
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0:01f31e923fe2 | 1537 | #define GPIO_CRL_CNF2_Pos (10U) |
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0:01f31e923fe2 | 1538 | #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ |
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0:01f31e923fe2 | 1539 | #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
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0:01f31e923fe2 | 1540 | #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1541 | #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1542 | |
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0:01f31e923fe2 | 1543 | #define GPIO_CRL_CNF3_Pos (14U) |
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0:01f31e923fe2 | 1544 | #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ |
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0:01f31e923fe2 | 1545 | #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
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0:01f31e923fe2 | 1546 | #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1547 | #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1548 | |
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0:01f31e923fe2 | 1549 | #define GPIO_CRL_CNF4_Pos (18U) |
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0:01f31e923fe2 | 1550 | #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ |
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0:01f31e923fe2 | 1551 | #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
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0:01f31e923fe2 | 1552 | #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1553 | #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 1554 | |
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0:01f31e923fe2 | 1555 | #define GPIO_CRL_CNF5_Pos (22U) |
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0:01f31e923fe2 | 1556 | #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ |
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0:01f31e923fe2 | 1557 | #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
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0:01f31e923fe2 | 1558 | #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 1559 | #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 1560 | |
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0:01f31e923fe2 | 1561 | #define GPIO_CRL_CNF6_Pos (26U) |
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0:01f31e923fe2 | 1562 | #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ |
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0:01f31e923fe2 | 1563 | #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
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0:01f31e923fe2 | 1564 | #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 1565 | #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 1566 | |
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0:01f31e923fe2 | 1567 | #define GPIO_CRL_CNF7_Pos (30U) |
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0:01f31e923fe2 | 1568 | #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ |
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0:01f31e923fe2 | 1569 | #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
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0:01f31e923fe2 | 1570 | #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ |
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0:01f31e923fe2 | 1571 | #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ |
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0:01f31e923fe2 | 1572 | |
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0:01f31e923fe2 | 1573 | /******************* Bit definition for GPIO_CRH register *******************/ |
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0:01f31e923fe2 | 1574 | #define GPIO_CRH_MODE_Pos (0U) |
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0:01f31e923fe2 | 1575 | #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ |
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0:01f31e923fe2 | 1576 | #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ |
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0:01f31e923fe2 | 1577 | |
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0:01f31e923fe2 | 1578 | #define GPIO_CRH_MODE8_Pos (0U) |
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0:01f31e923fe2 | 1579 | #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ |
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0:01f31e923fe2 | 1580 | #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
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0:01f31e923fe2 | 1581 | #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1582 | #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1583 | |
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0:01f31e923fe2 | 1584 | #define GPIO_CRH_MODE9_Pos (4U) |
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0:01f31e923fe2 | 1585 | #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ |
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0:01f31e923fe2 | 1586 | #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
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0:01f31e923fe2 | 1587 | #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1588 | #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1589 | |
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0:01f31e923fe2 | 1590 | #define GPIO_CRH_MODE10_Pos (8U) |
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0:01f31e923fe2 | 1591 | #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ |
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0:01f31e923fe2 | 1592 | #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
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0:01f31e923fe2 | 1593 | #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1594 | #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1595 | |
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0:01f31e923fe2 | 1596 | #define GPIO_CRH_MODE11_Pos (12U) |
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0:01f31e923fe2 | 1597 | #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ |
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0:01f31e923fe2 | 1598 | #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
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0:01f31e923fe2 | 1599 | #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1600 | #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1601 | |
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0:01f31e923fe2 | 1602 | #define GPIO_CRH_MODE12_Pos (16U) |
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0:01f31e923fe2 | 1603 | #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ |
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0:01f31e923fe2 | 1604 | #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
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0:01f31e923fe2 | 1605 | #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1606 | #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1607 | |
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0:01f31e923fe2 | 1608 | #define GPIO_CRH_MODE13_Pos (20U) |
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0:01f31e923fe2 | 1609 | #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ |
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0:01f31e923fe2 | 1610 | #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
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0:01f31e923fe2 | 1611 | #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 1612 | #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1613 | |
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0:01f31e923fe2 | 1614 | #define GPIO_CRH_MODE14_Pos (24U) |
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0:01f31e923fe2 | 1615 | #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ |
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0:01f31e923fe2 | 1616 | #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
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0:01f31e923fe2 | 1617 | #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 1618 | #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 1619 | |
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0:01f31e923fe2 | 1620 | #define GPIO_CRH_MODE15_Pos (28U) |
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0:01f31e923fe2 | 1621 | #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ |
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0:01f31e923fe2 | 1622 | #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
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0:01f31e923fe2 | 1623 | #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 1624 | #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ |
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0:01f31e923fe2 | 1625 | |
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0:01f31e923fe2 | 1626 | #define GPIO_CRH_CNF_Pos (2U) |
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0:01f31e923fe2 | 1627 | #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ |
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0:01f31e923fe2 | 1628 | #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ |
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0:01f31e923fe2 | 1629 | |
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0:01f31e923fe2 | 1630 | #define GPIO_CRH_CNF8_Pos (2U) |
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0:01f31e923fe2 | 1631 | #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ |
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0:01f31e923fe2 | 1632 | #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
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0:01f31e923fe2 | 1633 | #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1634 | #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1635 | |
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0:01f31e923fe2 | 1636 | #define GPIO_CRH_CNF9_Pos (6U) |
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0:01f31e923fe2 | 1637 | #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ |
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0:01f31e923fe2 | 1638 | #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
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0:01f31e923fe2 | 1639 | #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1640 | #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1641 | |
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0:01f31e923fe2 | 1642 | #define GPIO_CRH_CNF10_Pos (10U) |
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0:01f31e923fe2 | 1643 | #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ |
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0:01f31e923fe2 | 1644 | #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
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0:01f31e923fe2 | 1645 | #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1646 | #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1647 | |
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0:01f31e923fe2 | 1648 | #define GPIO_CRH_CNF11_Pos (14U) |
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0:01f31e923fe2 | 1649 | #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ |
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0:01f31e923fe2 | 1650 | #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
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0:01f31e923fe2 | 1651 | #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1652 | #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1653 | |
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0:01f31e923fe2 | 1654 | #define GPIO_CRH_CNF12_Pos (18U) |
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0:01f31e923fe2 | 1655 | #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ |
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0:01f31e923fe2 | 1656 | #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
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0:01f31e923fe2 | 1657 | #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1658 | #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 1659 | |
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0:01f31e923fe2 | 1660 | #define GPIO_CRH_CNF13_Pos (22U) |
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0:01f31e923fe2 | 1661 | #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ |
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0:01f31e923fe2 | 1662 | #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
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0:01f31e923fe2 | 1663 | #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 1664 | #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 1665 | |
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0:01f31e923fe2 | 1666 | #define GPIO_CRH_CNF14_Pos (26U) |
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0:01f31e923fe2 | 1667 | #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ |
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0:01f31e923fe2 | 1668 | #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
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0:01f31e923fe2 | 1669 | #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 1670 | #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 1671 | |
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0:01f31e923fe2 | 1672 | #define GPIO_CRH_CNF15_Pos (30U) |
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0:01f31e923fe2 | 1673 | #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ |
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0:01f31e923fe2 | 1674 | #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
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0:01f31e923fe2 | 1675 | #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ |
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0:01f31e923fe2 | 1676 | #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ |
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0:01f31e923fe2 | 1677 | |
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0:01f31e923fe2 | 1678 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
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0:01f31e923fe2 | 1679 | #define GPIO_IDR_IDR0_Pos (0U) |
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0:01f31e923fe2 | 1680 | #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1681 | #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ |
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0:01f31e923fe2 | 1682 | #define GPIO_IDR_IDR1_Pos (1U) |
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0:01f31e923fe2 | 1683 | #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1684 | #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ |
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0:01f31e923fe2 | 1685 | #define GPIO_IDR_IDR2_Pos (2U) |
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0:01f31e923fe2 | 1686 | #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1687 | #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ |
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0:01f31e923fe2 | 1688 | #define GPIO_IDR_IDR3_Pos (3U) |
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0:01f31e923fe2 | 1689 | #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1690 | #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ |
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0:01f31e923fe2 | 1691 | #define GPIO_IDR_IDR4_Pos (4U) |
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0:01f31e923fe2 | 1692 | #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1693 | #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ |
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0:01f31e923fe2 | 1694 | #define GPIO_IDR_IDR5_Pos (5U) |
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0:01f31e923fe2 | 1695 | #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1696 | #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ |
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0:01f31e923fe2 | 1697 | #define GPIO_IDR_IDR6_Pos (6U) |
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0:01f31e923fe2 | 1698 | #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1699 | #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ |
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0:01f31e923fe2 | 1700 | #define GPIO_IDR_IDR7_Pos (7U) |
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0:01f31e923fe2 | 1701 | #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1702 | #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ |
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0:01f31e923fe2 | 1703 | #define GPIO_IDR_IDR8_Pos (8U) |
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0:01f31e923fe2 | 1704 | #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1705 | #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ |
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0:01f31e923fe2 | 1706 | #define GPIO_IDR_IDR9_Pos (9U) |
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0:01f31e923fe2 | 1707 | #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1708 | #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ |
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0:01f31e923fe2 | 1709 | #define GPIO_IDR_IDR10_Pos (10U) |
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0:01f31e923fe2 | 1710 | #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1711 | #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ |
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0:01f31e923fe2 | 1712 | #define GPIO_IDR_IDR11_Pos (11U) |
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0:01f31e923fe2 | 1713 | #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1714 | #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ |
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0:01f31e923fe2 | 1715 | #define GPIO_IDR_IDR12_Pos (12U) |
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0:01f31e923fe2 | 1716 | #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1717 | #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ |
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0:01f31e923fe2 | 1718 | #define GPIO_IDR_IDR13_Pos (13U) |
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0:01f31e923fe2 | 1719 | #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1720 | #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ |
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0:01f31e923fe2 | 1721 | #define GPIO_IDR_IDR14_Pos (14U) |
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0:01f31e923fe2 | 1722 | #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1723 | #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ |
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0:01f31e923fe2 | 1724 | #define GPIO_IDR_IDR15_Pos (15U) |
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0:01f31e923fe2 | 1725 | #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1726 | #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ |
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0:01f31e923fe2 | 1727 | |
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0:01f31e923fe2 | 1728 | /******************* Bit definition for GPIO_ODR register *******************/ |
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0:01f31e923fe2 | 1729 | #define GPIO_ODR_ODR0_Pos (0U) |
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0:01f31e923fe2 | 1730 | #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1731 | #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ |
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0:01f31e923fe2 | 1732 | #define GPIO_ODR_ODR1_Pos (1U) |
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0:01f31e923fe2 | 1733 | #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1734 | #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ |
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0:01f31e923fe2 | 1735 | #define GPIO_ODR_ODR2_Pos (2U) |
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0:01f31e923fe2 | 1736 | #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1737 | #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ |
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0:01f31e923fe2 | 1738 | #define GPIO_ODR_ODR3_Pos (3U) |
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0:01f31e923fe2 | 1739 | #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1740 | #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ |
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0:01f31e923fe2 | 1741 | #define GPIO_ODR_ODR4_Pos (4U) |
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0:01f31e923fe2 | 1742 | #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1743 | #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ |
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0:01f31e923fe2 | 1744 | #define GPIO_ODR_ODR5_Pos (5U) |
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0:01f31e923fe2 | 1745 | #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1746 | #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ |
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0:01f31e923fe2 | 1747 | #define GPIO_ODR_ODR6_Pos (6U) |
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0:01f31e923fe2 | 1748 | #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1749 | #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ |
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0:01f31e923fe2 | 1750 | #define GPIO_ODR_ODR7_Pos (7U) |
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0:01f31e923fe2 | 1751 | #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1752 | #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ |
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0:01f31e923fe2 | 1753 | #define GPIO_ODR_ODR8_Pos (8U) |
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0:01f31e923fe2 | 1754 | #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1755 | #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ |
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0:01f31e923fe2 | 1756 | #define GPIO_ODR_ODR9_Pos (9U) |
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0:01f31e923fe2 | 1757 | #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1758 | #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ |
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0:01f31e923fe2 | 1759 | #define GPIO_ODR_ODR10_Pos (10U) |
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0:01f31e923fe2 | 1760 | #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1761 | #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ |
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0:01f31e923fe2 | 1762 | #define GPIO_ODR_ODR11_Pos (11U) |
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0:01f31e923fe2 | 1763 | #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1764 | #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ |
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0:01f31e923fe2 | 1765 | #define GPIO_ODR_ODR12_Pos (12U) |
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0:01f31e923fe2 | 1766 | #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1767 | #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ |
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0:01f31e923fe2 | 1768 | #define GPIO_ODR_ODR13_Pos (13U) |
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0:01f31e923fe2 | 1769 | #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1770 | #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ |
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0:01f31e923fe2 | 1771 | #define GPIO_ODR_ODR14_Pos (14U) |
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0:01f31e923fe2 | 1772 | #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1773 | #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ |
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0:01f31e923fe2 | 1774 | #define GPIO_ODR_ODR15_Pos (15U) |
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0:01f31e923fe2 | 1775 | #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1776 | #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ |
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0:01f31e923fe2 | 1777 | |
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0:01f31e923fe2 | 1778 | /****************** Bit definition for GPIO_BSRR register *******************/ |
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0:01f31e923fe2 | 1779 | #define GPIO_BSRR_BS0_Pos (0U) |
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0:01f31e923fe2 | 1780 | #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1781 | #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ |
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0:01f31e923fe2 | 1782 | #define GPIO_BSRR_BS1_Pos (1U) |
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0:01f31e923fe2 | 1783 | #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1784 | #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ |
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0:01f31e923fe2 | 1785 | #define GPIO_BSRR_BS2_Pos (2U) |
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0:01f31e923fe2 | 1786 | #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1787 | #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ |
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0:01f31e923fe2 | 1788 | #define GPIO_BSRR_BS3_Pos (3U) |
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0:01f31e923fe2 | 1789 | #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1790 | #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ |
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0:01f31e923fe2 | 1791 | #define GPIO_BSRR_BS4_Pos (4U) |
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0:01f31e923fe2 | 1792 | #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1793 | #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ |
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0:01f31e923fe2 | 1794 | #define GPIO_BSRR_BS5_Pos (5U) |
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0:01f31e923fe2 | 1795 | #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1796 | #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ |
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0:01f31e923fe2 | 1797 | #define GPIO_BSRR_BS6_Pos (6U) |
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0:01f31e923fe2 | 1798 | #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1799 | #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ |
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0:01f31e923fe2 | 1800 | #define GPIO_BSRR_BS7_Pos (7U) |
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0:01f31e923fe2 | 1801 | #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1802 | #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ |
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0:01f31e923fe2 | 1803 | #define GPIO_BSRR_BS8_Pos (8U) |
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0:01f31e923fe2 | 1804 | #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1805 | #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ |
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0:01f31e923fe2 | 1806 | #define GPIO_BSRR_BS9_Pos (9U) |
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0:01f31e923fe2 | 1807 | #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1808 | #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ |
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0:01f31e923fe2 | 1809 | #define GPIO_BSRR_BS10_Pos (10U) |
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0:01f31e923fe2 | 1810 | #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1811 | #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ |
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0:01f31e923fe2 | 1812 | #define GPIO_BSRR_BS11_Pos (11U) |
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0:01f31e923fe2 | 1813 | #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1814 | #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ |
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0:01f31e923fe2 | 1815 | #define GPIO_BSRR_BS12_Pos (12U) |
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0:01f31e923fe2 | 1816 | #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1817 | #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ |
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0:01f31e923fe2 | 1818 | #define GPIO_BSRR_BS13_Pos (13U) |
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0:01f31e923fe2 | 1819 | #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1820 | #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ |
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0:01f31e923fe2 | 1821 | #define GPIO_BSRR_BS14_Pos (14U) |
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0:01f31e923fe2 | 1822 | #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1823 | #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ |
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0:01f31e923fe2 | 1824 | #define GPIO_BSRR_BS15_Pos (15U) |
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0:01f31e923fe2 | 1825 | #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1826 | #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ |
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0:01f31e923fe2 | 1827 | |
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0:01f31e923fe2 | 1828 | #define GPIO_BSRR_BR0_Pos (16U) |
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0:01f31e923fe2 | 1829 | #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1830 | #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ |
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0:01f31e923fe2 | 1831 | #define GPIO_BSRR_BR1_Pos (17U) |
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0:01f31e923fe2 | 1832 | #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 1833 | #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ |
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0:01f31e923fe2 | 1834 | #define GPIO_BSRR_BR2_Pos (18U) |
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0:01f31e923fe2 | 1835 | #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 1836 | #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ |
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0:01f31e923fe2 | 1837 | #define GPIO_BSRR_BR3_Pos (19U) |
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0:01f31e923fe2 | 1838 | #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 1839 | #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ |
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0:01f31e923fe2 | 1840 | #define GPIO_BSRR_BR4_Pos (20U) |
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0:01f31e923fe2 | 1841 | #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 1842 | #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ |
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0:01f31e923fe2 | 1843 | #define GPIO_BSRR_BR5_Pos (21U) |
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0:01f31e923fe2 | 1844 | #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 1845 | #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ |
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0:01f31e923fe2 | 1846 | #define GPIO_BSRR_BR6_Pos (22U) |
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0:01f31e923fe2 | 1847 | #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 1848 | #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ |
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0:01f31e923fe2 | 1849 | #define GPIO_BSRR_BR7_Pos (23U) |
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0:01f31e923fe2 | 1850 | #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 1851 | #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ |
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0:01f31e923fe2 | 1852 | #define GPIO_BSRR_BR8_Pos (24U) |
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0:01f31e923fe2 | 1853 | #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 1854 | #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ |
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0:01f31e923fe2 | 1855 | #define GPIO_BSRR_BR9_Pos (25U) |
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0:01f31e923fe2 | 1856 | #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 1857 | #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ |
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0:01f31e923fe2 | 1858 | #define GPIO_BSRR_BR10_Pos (26U) |
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0:01f31e923fe2 | 1859 | #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 1860 | #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ |
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0:01f31e923fe2 | 1861 | #define GPIO_BSRR_BR11_Pos (27U) |
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0:01f31e923fe2 | 1862 | #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 1863 | #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ |
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0:01f31e923fe2 | 1864 | #define GPIO_BSRR_BR12_Pos (28U) |
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0:01f31e923fe2 | 1865 | #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 1866 | #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ |
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0:01f31e923fe2 | 1867 | #define GPIO_BSRR_BR13_Pos (29U) |
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0:01f31e923fe2 | 1868 | #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ |
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0:01f31e923fe2 | 1869 | #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ |
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0:01f31e923fe2 | 1870 | #define GPIO_BSRR_BR14_Pos (30U) |
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0:01f31e923fe2 | 1871 | #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ |
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0:01f31e923fe2 | 1872 | #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ |
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0:01f31e923fe2 | 1873 | #define GPIO_BSRR_BR15_Pos (31U) |
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0:01f31e923fe2 | 1874 | #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ |
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0:01f31e923fe2 | 1875 | #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ |
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0:01f31e923fe2 | 1876 | |
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0:01f31e923fe2 | 1877 | /******************* Bit definition for GPIO_BRR register *******************/ |
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0:01f31e923fe2 | 1878 | #define GPIO_BRR_BR0_Pos (0U) |
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0:01f31e923fe2 | 1879 | #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1880 | #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ |
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0:01f31e923fe2 | 1881 | #define GPIO_BRR_BR1_Pos (1U) |
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0:01f31e923fe2 | 1882 | #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1883 | #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ |
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0:01f31e923fe2 | 1884 | #define GPIO_BRR_BR2_Pos (2U) |
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0:01f31e923fe2 | 1885 | #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1886 | #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ |
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0:01f31e923fe2 | 1887 | #define GPIO_BRR_BR3_Pos (3U) |
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0:01f31e923fe2 | 1888 | #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1889 | #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ |
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0:01f31e923fe2 | 1890 | #define GPIO_BRR_BR4_Pos (4U) |
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0:01f31e923fe2 | 1891 | #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1892 | #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ |
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0:01f31e923fe2 | 1893 | #define GPIO_BRR_BR5_Pos (5U) |
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0:01f31e923fe2 | 1894 | #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1895 | #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ |
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0:01f31e923fe2 | 1896 | #define GPIO_BRR_BR6_Pos (6U) |
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0:01f31e923fe2 | 1897 | #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1898 | #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ |
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0:01f31e923fe2 | 1899 | #define GPIO_BRR_BR7_Pos (7U) |
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0:01f31e923fe2 | 1900 | #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1901 | #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ |
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0:01f31e923fe2 | 1902 | #define GPIO_BRR_BR8_Pos (8U) |
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0:01f31e923fe2 | 1903 | #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1904 | #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ |
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0:01f31e923fe2 | 1905 | #define GPIO_BRR_BR9_Pos (9U) |
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0:01f31e923fe2 | 1906 | #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1907 | #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ |
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0:01f31e923fe2 | 1908 | #define GPIO_BRR_BR10_Pos (10U) |
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0:01f31e923fe2 | 1909 | #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1910 | #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ |
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0:01f31e923fe2 | 1911 | #define GPIO_BRR_BR11_Pos (11U) |
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0:01f31e923fe2 | 1912 | #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1913 | #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ |
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0:01f31e923fe2 | 1914 | #define GPIO_BRR_BR12_Pos (12U) |
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0:01f31e923fe2 | 1915 | #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1916 | #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ |
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0:01f31e923fe2 | 1917 | #define GPIO_BRR_BR13_Pos (13U) |
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0:01f31e923fe2 | 1918 | #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1919 | #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ |
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0:01f31e923fe2 | 1920 | #define GPIO_BRR_BR14_Pos (14U) |
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0:01f31e923fe2 | 1921 | #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1922 | #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ |
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0:01f31e923fe2 | 1923 | #define GPIO_BRR_BR15_Pos (15U) |
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0:01f31e923fe2 | 1924 | #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1925 | #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ |
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0:01f31e923fe2 | 1926 | |
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0:01f31e923fe2 | 1927 | /****************** Bit definition for GPIO_LCKR register *******************/ |
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0:01f31e923fe2 | 1928 | #define GPIO_LCKR_LCK0_Pos (0U) |
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0:01f31e923fe2 | 1929 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1930 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ |
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0:01f31e923fe2 | 1931 | #define GPIO_LCKR_LCK1_Pos (1U) |
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0:01f31e923fe2 | 1932 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1933 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ |
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0:01f31e923fe2 | 1934 | #define GPIO_LCKR_LCK2_Pos (2U) |
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0:01f31e923fe2 | 1935 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1936 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ |
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0:01f31e923fe2 | 1937 | #define GPIO_LCKR_LCK3_Pos (3U) |
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0:01f31e923fe2 | 1938 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1939 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ |
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0:01f31e923fe2 | 1940 | #define GPIO_LCKR_LCK4_Pos (4U) |
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0:01f31e923fe2 | 1941 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 1942 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ |
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0:01f31e923fe2 | 1943 | #define GPIO_LCKR_LCK5_Pos (5U) |
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0:01f31e923fe2 | 1944 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 1945 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ |
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0:01f31e923fe2 | 1946 | #define GPIO_LCKR_LCK6_Pos (6U) |
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0:01f31e923fe2 | 1947 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 1948 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ |
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0:01f31e923fe2 | 1949 | #define GPIO_LCKR_LCK7_Pos (7U) |
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0:01f31e923fe2 | 1950 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 1951 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ |
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0:01f31e923fe2 | 1952 | #define GPIO_LCKR_LCK8_Pos (8U) |
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0:01f31e923fe2 | 1953 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 1954 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ |
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0:01f31e923fe2 | 1955 | #define GPIO_LCKR_LCK9_Pos (9U) |
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0:01f31e923fe2 | 1956 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 1957 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ |
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0:01f31e923fe2 | 1958 | #define GPIO_LCKR_LCK10_Pos (10U) |
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0:01f31e923fe2 | 1959 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 1960 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ |
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0:01f31e923fe2 | 1961 | #define GPIO_LCKR_LCK11_Pos (11U) |
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0:01f31e923fe2 | 1962 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 1963 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ |
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0:01f31e923fe2 | 1964 | #define GPIO_LCKR_LCK12_Pos (12U) |
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0:01f31e923fe2 | 1965 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 1966 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ |
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0:01f31e923fe2 | 1967 | #define GPIO_LCKR_LCK13_Pos (13U) |
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0:01f31e923fe2 | 1968 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 1969 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ |
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0:01f31e923fe2 | 1970 | #define GPIO_LCKR_LCK14_Pos (14U) |
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0:01f31e923fe2 | 1971 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 1972 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ |
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0:01f31e923fe2 | 1973 | #define GPIO_LCKR_LCK15_Pos (15U) |
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0:01f31e923fe2 | 1974 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 1975 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ |
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0:01f31e923fe2 | 1976 | #define GPIO_LCKR_LCKK_Pos (16U) |
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0:01f31e923fe2 | 1977 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 1978 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ |
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0:01f31e923fe2 | 1979 | |
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0:01f31e923fe2 | 1980 | /*----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 1981 | |
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0:01f31e923fe2 | 1982 | /****************** Bit definition for AFIO_EVCR register *******************/ |
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0:01f31e923fe2 | 1983 | #define AFIO_EVCR_PIN_Pos (0U) |
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0:01f31e923fe2 | 1984 | #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ |
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0:01f31e923fe2 | 1985 | #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ |
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0:01f31e923fe2 | 1986 | #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1987 | #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1988 | #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 1989 | #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 1990 | |
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0:01f31e923fe2 | 1991 | /*!< PIN configuration */ |
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0:01f31e923fe2 | 1992 | #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ |
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0:01f31e923fe2 | 1993 | #define AFIO_EVCR_PIN_PX1_Pos (0U) |
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0:01f31e923fe2 | 1994 | #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 1995 | #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ |
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0:01f31e923fe2 | 1996 | #define AFIO_EVCR_PIN_PX2_Pos (1U) |
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0:01f31e923fe2 | 1997 | #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 1998 | #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ |
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0:01f31e923fe2 | 1999 | #define AFIO_EVCR_PIN_PX3_Pos (0U) |
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0:01f31e923fe2 | 2000 | #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ |
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0:01f31e923fe2 | 2001 | #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ |
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0:01f31e923fe2 | 2002 | #define AFIO_EVCR_PIN_PX4_Pos (2U) |
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0:01f31e923fe2 | 2003 | #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 2004 | #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ |
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0:01f31e923fe2 | 2005 | #define AFIO_EVCR_PIN_PX5_Pos (0U) |
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0:01f31e923fe2 | 2006 | #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ |
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0:01f31e923fe2 | 2007 | #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ |
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0:01f31e923fe2 | 2008 | #define AFIO_EVCR_PIN_PX6_Pos (1U) |
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0:01f31e923fe2 | 2009 | #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ |
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0:01f31e923fe2 | 2010 | #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ |
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0:01f31e923fe2 | 2011 | #define AFIO_EVCR_PIN_PX7_Pos (0U) |
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0:01f31e923fe2 | 2012 | #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ |
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0:01f31e923fe2 | 2013 | #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ |
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0:01f31e923fe2 | 2014 | #define AFIO_EVCR_PIN_PX8_Pos (3U) |
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0:01f31e923fe2 | 2015 | #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 2016 | #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ |
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0:01f31e923fe2 | 2017 | #define AFIO_EVCR_PIN_PX9_Pos (0U) |
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0:01f31e923fe2 | 2018 | #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ |
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0:01f31e923fe2 | 2019 | #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ |
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0:01f31e923fe2 | 2020 | #define AFIO_EVCR_PIN_PX10_Pos (1U) |
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0:01f31e923fe2 | 2021 | #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ |
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0:01f31e923fe2 | 2022 | #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ |
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0:01f31e923fe2 | 2023 | #define AFIO_EVCR_PIN_PX11_Pos (0U) |
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0:01f31e923fe2 | 2024 | #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ |
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0:01f31e923fe2 | 2025 | #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ |
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0:01f31e923fe2 | 2026 | #define AFIO_EVCR_PIN_PX12_Pos (2U) |
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0:01f31e923fe2 | 2027 | #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ |
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0:01f31e923fe2 | 2028 | #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ |
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0:01f31e923fe2 | 2029 | #define AFIO_EVCR_PIN_PX13_Pos (0U) |
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0:01f31e923fe2 | 2030 | #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ |
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0:01f31e923fe2 | 2031 | #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ |
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0:01f31e923fe2 | 2032 | #define AFIO_EVCR_PIN_PX14_Pos (1U) |
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0:01f31e923fe2 | 2033 | #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ |
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0:01f31e923fe2 | 2034 | #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ |
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0:01f31e923fe2 | 2035 | #define AFIO_EVCR_PIN_PX15_Pos (0U) |
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0:01f31e923fe2 | 2036 | #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ |
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0:01f31e923fe2 | 2037 | #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ |
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0:01f31e923fe2 | 2038 | |
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0:01f31e923fe2 | 2039 | #define AFIO_EVCR_PORT_Pos (4U) |
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0:01f31e923fe2 | 2040 | #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ |
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0:01f31e923fe2 | 2041 | #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ |
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0:01f31e923fe2 | 2042 | #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 2043 | #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2044 | #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2045 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2046 | /*!< PORT configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2047 | #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2048 | #define AFIO_EVCR_PORT_PB_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2049 | #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2050 | #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2051 | #define AFIO_EVCR_PORT_PC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2052 | #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2053 | #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2054 | #define AFIO_EVCR_PORT_PD_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2055 | #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2056 | #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2057 | #define AFIO_EVCR_PORT_PE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2058 | #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2059 | #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2060 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2061 | #define AFIO_EVCR_EVOE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2062 | #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2063 | #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2064 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2065 | /****************** Bit definition for AFIO_MAPR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2066 | #define AFIO_MAPR_SPI1_REMAP_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2067 | #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2068 | #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2069 | #define AFIO_MAPR_I2C1_REMAP_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2070 | #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2071 | #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2072 | #define AFIO_MAPR_USART1_REMAP_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2073 | #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2074 | #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2075 | #define AFIO_MAPR_USART2_REMAP_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2076 | #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2077 | #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2078 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2079 | #define AFIO_MAPR_USART3_REMAP_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2080 | #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2081 | #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2082 | #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2083 | #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2084 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2085 | /* USART3_REMAP configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2086 | #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2087 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2088 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2089 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2090 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2091 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2092 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2093 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2094 | #define AFIO_MAPR_TIM1_REMAP_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2095 | #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2096 | #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2097 | #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2098 | #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2099 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2100 | /*!< TIM1_REMAP configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2101 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2102 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2103 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2104 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2105 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2106 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2107 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2108 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2109 | #define AFIO_MAPR_TIM2_REMAP_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2110 | #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2111 | #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2112 | #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2113 | #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2114 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2115 | /*!< TIM2_REMAP configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2116 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2117 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2118 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2119 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2120 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2121 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2122 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2123 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2124 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2125 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2126 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2127 | #define AFIO_MAPR_TIM3_REMAP_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2128 | #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2129 | #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2130 | #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2131 | #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2132 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2133 | /*!< TIM3_REMAP configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2134 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2135 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2136 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2137 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2138 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2139 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2140 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2141 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2142 | #define AFIO_MAPR_TIM4_REMAP_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2143 | #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2144 | #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2145 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2146 | #define AFIO_MAPR_CAN_REMAP_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2147 | #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2148 | #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2149 | #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2150 | #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2151 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2152 | /*!< CAN_REMAP configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2153 | #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2154 | #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2155 | #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2156 | #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2157 | #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2158 | #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2159 | #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2160 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2161 | #define AFIO_MAPR_PD01_REMAP_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2162 | #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2163 | #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2164 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2165 | /*!< SWJ_CFG configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2166 | #define AFIO_MAPR_SWJ_CFG_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2167 | #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2168 | #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2169 | #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2170 | #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2171 | #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2172 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2173 | #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2174 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2175 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2176 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2177 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2178 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2179 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2180 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2181 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2182 | #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2183 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2184 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2185 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2186 | #define AFIO_EXTICR1_EXTI0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2187 | #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2188 | #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2189 | #define AFIO_EXTICR1_EXTI1_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2190 | #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2191 | #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2192 | #define AFIO_EXTICR1_EXTI2_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2193 | #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2194 | #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2195 | #define AFIO_EXTICR1_EXTI3_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2196 | #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2197 | #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2198 | |
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0:01f31e923fe2 | 2199 | /*!< EXTI0 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2200 | #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2201 | #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2202 | #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2203 | #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2204 | #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2205 | #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2206 | #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2207 | #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2208 | #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2209 | #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2210 | #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2211 | #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2212 | #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2213 | #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2214 | #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2215 | #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2216 | #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2217 | #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2218 | #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2219 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2220 | /*!< EXTI1 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2221 | #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2222 | #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2223 | #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2224 | #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2225 | #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2226 | #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2227 | #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2228 | #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2229 | #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2230 | #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2231 | #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2232 | #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2233 | #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2234 | #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2235 | #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2236 | #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2237 | #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2238 | #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2239 | #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2240 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2241 | /*!< EXTI2 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2242 | #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2243 | #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2244 | #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2245 | #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2246 | #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2247 | #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2248 | #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2249 | #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2250 | #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2251 | #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2252 | #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2253 | #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2254 | #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2255 | #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2256 | #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2257 | #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2258 | #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2259 | #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2260 | #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2261 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2262 | /*!< EXTI3 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2263 | #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2264 | #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2265 | #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2266 | #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2267 | #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2268 | #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2269 | #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2270 | #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2271 | #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2272 | #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2273 | #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2274 | #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2275 | #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2276 | #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2277 | #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2278 | #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2279 | #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2280 | #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2281 | #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2282 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2283 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2284 | #define AFIO_EXTICR2_EXTI4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2285 | #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2286 | #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2287 | #define AFIO_EXTICR2_EXTI5_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2288 | #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2289 | #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2290 | #define AFIO_EXTICR2_EXTI6_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2291 | #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2292 | #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2293 | #define AFIO_EXTICR2_EXTI7_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2294 | #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2295 | #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2296 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2297 | /*!< EXTI4 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2298 | #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2299 | #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2300 | #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2301 | #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2302 | #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2303 | #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2304 | #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2305 | #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2306 | #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2307 | #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2308 | #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2309 | #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2310 | #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2311 | #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2312 | #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2313 | #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2314 | #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2315 | #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2316 | #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2317 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2318 | /* EXTI5 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2319 | #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2320 | #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2321 | #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2322 | #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2323 | #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2324 | #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2325 | #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2326 | #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2327 | #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2328 | #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2329 | #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2330 | #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2331 | #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2332 | #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2333 | #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2334 | #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2335 | #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2336 | #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2337 | #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2338 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2339 | /*!< EXTI6 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2340 | #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2341 | #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2342 | #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2343 | #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2344 | #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2345 | #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2346 | #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2347 | #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2348 | #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2349 | #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2350 | #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2351 | #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2352 | #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2353 | #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2354 | #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2355 | #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2356 | #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2357 | #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2358 | #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2359 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2360 | /*!< EXTI7 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2361 | #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2362 | #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2363 | #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2364 | #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2365 | #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2366 | #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2367 | #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2368 | #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2369 | #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2370 | #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2371 | #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2372 | #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2373 | #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2374 | #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2375 | #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2376 | #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2377 | #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2378 | #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2379 | #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2380 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2381 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2382 | #define AFIO_EXTICR3_EXTI8_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2383 | #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2384 | #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2385 | #define AFIO_EXTICR3_EXTI9_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2386 | #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2387 | #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2388 | #define AFIO_EXTICR3_EXTI10_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2389 | #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2390 | #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2391 | #define AFIO_EXTICR3_EXTI11_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2392 | #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2393 | #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2394 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2395 | /*!< EXTI8 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2396 | #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2397 | #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2398 | #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2399 | #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2400 | #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2401 | #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2402 | #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2403 | #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2404 | #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2405 | #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2406 | #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2407 | #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2408 | #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2409 | #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2410 | #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2411 | #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2412 | #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2413 | #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2414 | #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2415 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2416 | /*!< EXTI9 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2417 | #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2418 | #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2419 | #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2420 | #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2421 | #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2422 | #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2423 | #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2424 | #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2425 | #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2426 | #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2427 | #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2428 | #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2429 | #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2430 | #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2431 | #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2432 | #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2433 | #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2434 | #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2435 | #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2436 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2437 | /*!< EXTI10 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2438 | #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2439 | #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2440 | #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2441 | #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2442 | #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2443 | #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2444 | #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2445 | #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2446 | #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2447 | #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2448 | #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2449 | #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2450 | #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2451 | #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2452 | #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2453 | #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2454 | #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2455 | #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2456 | #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2457 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2458 | /*!< EXTI11 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2459 | #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2460 | #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2461 | #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2462 | #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2463 | #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2464 | #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2465 | #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2466 | #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2467 | #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2468 | #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2469 | #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2470 | #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2471 | #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2472 | #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2473 | #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2474 | #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2475 | #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2476 | #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2477 | #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2478 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2479 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2480 | #define AFIO_EXTICR4_EXTI12_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2481 | #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2482 | #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2483 | #define AFIO_EXTICR4_EXTI13_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2484 | #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2485 | #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2486 | #define AFIO_EXTICR4_EXTI14_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2487 | #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2488 | #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2489 | #define AFIO_EXTICR4_EXTI15_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2490 | #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2491 | #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2492 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2493 | /* EXTI12 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2494 | #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2495 | #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2496 | #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2497 | #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2498 | #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2499 | #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2500 | #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2501 | #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2502 | #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2503 | #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2504 | #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2505 | #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2506 | #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2507 | #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2508 | #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2509 | #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2510 | #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2511 | #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2512 | #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2513 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2514 | /* EXTI13 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2515 | #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2516 | #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2517 | #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2518 | #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2519 | #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2520 | #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2521 | #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2522 | #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2523 | #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2524 | #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2525 | #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2526 | #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2527 | #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2528 | #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2529 | #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2530 | #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2531 | #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2532 | #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2533 | #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2534 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2535 | /*!< EXTI14 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2536 | #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2537 | #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2538 | #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2539 | #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2540 | #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2541 | #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2542 | #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2543 | #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2544 | #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2545 | #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2546 | #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2547 | #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2548 | #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2549 | #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2550 | #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2551 | #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2552 | #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2553 | #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2554 | #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2555 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2556 | /*!< EXTI15 configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2557 | #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2558 | #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2559 | #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2560 | #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2561 | #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2562 | #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2563 | #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2564 | #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2565 | #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2566 | #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2567 | #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2568 | #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2569 | #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2570 | #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2571 | #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2572 | #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2573 | #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2574 | #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2575 | #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2576 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2577 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2578 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2579 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2580 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2581 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2582 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2583 | /* External Interrupt/Event Controller */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2584 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2585 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2586 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2587 | /******************* Bit definition for EXTI_IMR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2588 | #define EXTI_IMR_MR0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2589 | #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2590 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2591 | #define EXTI_IMR_MR1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2592 | #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2593 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2594 | #define EXTI_IMR_MR2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2595 | #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2596 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2597 | #define EXTI_IMR_MR3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2598 | #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2599 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2600 | #define EXTI_IMR_MR4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2601 | #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2602 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2603 | #define EXTI_IMR_MR5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2604 | #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2605 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2606 | #define EXTI_IMR_MR6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2607 | #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2608 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2609 | #define EXTI_IMR_MR7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2610 | #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2611 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2612 | #define EXTI_IMR_MR8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2613 | #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2614 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2615 | #define EXTI_IMR_MR9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2616 | #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2617 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2618 | #define EXTI_IMR_MR10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2619 | #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2620 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2621 | #define EXTI_IMR_MR11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2622 | #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2623 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2624 | #define EXTI_IMR_MR12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2625 | #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2626 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2627 | #define EXTI_IMR_MR13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2628 | #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2629 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2630 | #define EXTI_IMR_MR14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2631 | #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2632 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2633 | #define EXTI_IMR_MR15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2634 | #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2635 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2636 | #define EXTI_IMR_MR16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2637 | #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2638 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2639 | #define EXTI_IMR_MR17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2640 | #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2641 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2642 | #define EXTI_IMR_MR18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2643 | #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2644 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2645 | #define EXTI_IMR_MR19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2646 | #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2647 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2648 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2649 | /* References Defines */ |
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0:01f31e923fe2 | 2650 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
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0:01f31e923fe2 | 2651 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
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0:01f31e923fe2 | 2652 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
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0:01f31e923fe2 | 2653 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
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0:01f31e923fe2 | 2654 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
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0:01f31e923fe2 | 2655 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
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0:01f31e923fe2 | 2656 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
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0:01f31e923fe2 | 2657 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
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0:01f31e923fe2 | 2658 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
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0:01f31e923fe2 | 2659 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
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0:01f31e923fe2 | 2660 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
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0:01f31e923fe2 | 2661 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
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0:01f31e923fe2 | 2662 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
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0:01f31e923fe2 | 2663 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
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0:01f31e923fe2 | 2664 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
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0:01f31e923fe2 | 2665 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
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0:01f31e923fe2 | 2666 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
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0:01f31e923fe2 | 2667 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
| Pawel Zarembski |
0:01f31e923fe2 | 2668 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
| Pawel Zarembski |
0:01f31e923fe2 | 2669 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
| Pawel Zarembski |
0:01f31e923fe2 | 2670 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2671 | /******************* Bit definition for EXTI_EMR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2672 | #define EXTI_EMR_MR0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2673 | #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2674 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2675 | #define EXTI_EMR_MR1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2676 | #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2677 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2678 | #define EXTI_EMR_MR2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2679 | #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2680 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2681 | #define EXTI_EMR_MR3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2682 | #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2683 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2684 | #define EXTI_EMR_MR4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2685 | #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2686 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2687 | #define EXTI_EMR_MR5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2688 | #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2689 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2690 | #define EXTI_EMR_MR6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2691 | #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2692 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2693 | #define EXTI_EMR_MR7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2694 | #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2695 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2696 | #define EXTI_EMR_MR8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2697 | #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2698 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2699 | #define EXTI_EMR_MR9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2700 | #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2701 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2702 | #define EXTI_EMR_MR10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2703 | #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2704 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2705 | #define EXTI_EMR_MR11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2706 | #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2707 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2708 | #define EXTI_EMR_MR12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2709 | #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2710 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2711 | #define EXTI_EMR_MR13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2712 | #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2713 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2714 | #define EXTI_EMR_MR14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2715 | #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2716 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2717 | #define EXTI_EMR_MR15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2718 | #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2719 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2720 | #define EXTI_EMR_MR16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2721 | #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2722 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2723 | #define EXTI_EMR_MR17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2724 | #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2725 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2726 | #define EXTI_EMR_MR18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2727 | #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2728 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2729 | #define EXTI_EMR_MR19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2730 | #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2731 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2732 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2733 | /* References Defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2734 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
| Pawel Zarembski |
0:01f31e923fe2 | 2735 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
| Pawel Zarembski |
0:01f31e923fe2 | 2736 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
| Pawel Zarembski |
0:01f31e923fe2 | 2737 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
| Pawel Zarembski |
0:01f31e923fe2 | 2738 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
| Pawel Zarembski |
0:01f31e923fe2 | 2739 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
| Pawel Zarembski |
0:01f31e923fe2 | 2740 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
| Pawel Zarembski |
0:01f31e923fe2 | 2741 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
| Pawel Zarembski |
0:01f31e923fe2 | 2742 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
| Pawel Zarembski |
0:01f31e923fe2 | 2743 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
| Pawel Zarembski |
0:01f31e923fe2 | 2744 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
| Pawel Zarembski |
0:01f31e923fe2 | 2745 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
| Pawel Zarembski |
0:01f31e923fe2 | 2746 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
| Pawel Zarembski |
0:01f31e923fe2 | 2747 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
| Pawel Zarembski |
0:01f31e923fe2 | 2748 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
| Pawel Zarembski |
0:01f31e923fe2 | 2749 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
| Pawel Zarembski |
0:01f31e923fe2 | 2750 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
| Pawel Zarembski |
0:01f31e923fe2 | 2751 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
| Pawel Zarembski |
0:01f31e923fe2 | 2752 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
| Pawel Zarembski |
0:01f31e923fe2 | 2753 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
| Pawel Zarembski |
0:01f31e923fe2 | 2754 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2755 | /****************** Bit definition for EXTI_RTSR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2756 | #define EXTI_RTSR_TR0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2757 | #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2758 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2759 | #define EXTI_RTSR_TR1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2760 | #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2761 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2762 | #define EXTI_RTSR_TR2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2763 | #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2764 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2765 | #define EXTI_RTSR_TR3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2766 | #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2767 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2768 | #define EXTI_RTSR_TR4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2769 | #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2770 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2771 | #define EXTI_RTSR_TR5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2772 | #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2773 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2774 | #define EXTI_RTSR_TR6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2775 | #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2776 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2777 | #define EXTI_RTSR_TR7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2778 | #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2779 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2780 | #define EXTI_RTSR_TR8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2781 | #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2782 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2783 | #define EXTI_RTSR_TR9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2784 | #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2785 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2786 | #define EXTI_RTSR_TR10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2787 | #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2788 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2789 | #define EXTI_RTSR_TR11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2790 | #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2791 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2792 | #define EXTI_RTSR_TR12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2793 | #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2794 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2795 | #define EXTI_RTSR_TR13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2796 | #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2797 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2798 | #define EXTI_RTSR_TR14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2799 | #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2800 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2801 | #define EXTI_RTSR_TR15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2802 | #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2803 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2804 | #define EXTI_RTSR_TR16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2805 | #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2806 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2807 | #define EXTI_RTSR_TR17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2808 | #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2809 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2810 | #define EXTI_RTSR_TR18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2811 | #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2812 | #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2813 | #define EXTI_RTSR_TR19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2814 | #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2815 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2816 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2817 | /* References Defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2818 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
| Pawel Zarembski |
0:01f31e923fe2 | 2819 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
| Pawel Zarembski |
0:01f31e923fe2 | 2820 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
| Pawel Zarembski |
0:01f31e923fe2 | 2821 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
| Pawel Zarembski |
0:01f31e923fe2 | 2822 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
| Pawel Zarembski |
0:01f31e923fe2 | 2823 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
| Pawel Zarembski |
0:01f31e923fe2 | 2824 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
| Pawel Zarembski |
0:01f31e923fe2 | 2825 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
| Pawel Zarembski |
0:01f31e923fe2 | 2826 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
| Pawel Zarembski |
0:01f31e923fe2 | 2827 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
| Pawel Zarembski |
0:01f31e923fe2 | 2828 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
| Pawel Zarembski |
0:01f31e923fe2 | 2829 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
| Pawel Zarembski |
0:01f31e923fe2 | 2830 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
| Pawel Zarembski |
0:01f31e923fe2 | 2831 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
| Pawel Zarembski |
0:01f31e923fe2 | 2832 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
| Pawel Zarembski |
0:01f31e923fe2 | 2833 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
| Pawel Zarembski |
0:01f31e923fe2 | 2834 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
| Pawel Zarembski |
0:01f31e923fe2 | 2835 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
| Pawel Zarembski |
0:01f31e923fe2 | 2836 | #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 |
| Pawel Zarembski |
0:01f31e923fe2 | 2837 | #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 |
| Pawel Zarembski |
0:01f31e923fe2 | 2838 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2839 | /****************** Bit definition for EXTI_FTSR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 2840 | #define EXTI_FTSR_TR0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2841 | #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2842 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2843 | #define EXTI_FTSR_TR1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2844 | #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2845 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2846 | #define EXTI_FTSR_TR2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2847 | #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2848 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2849 | #define EXTI_FTSR_TR3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2850 | #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2851 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2852 | #define EXTI_FTSR_TR4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2853 | #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2854 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2855 | #define EXTI_FTSR_TR5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2856 | #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2857 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2858 | #define EXTI_FTSR_TR6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2859 | #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2860 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2861 | #define EXTI_FTSR_TR7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2862 | #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2863 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2864 | #define EXTI_FTSR_TR8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2865 | #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2866 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2867 | #define EXTI_FTSR_TR9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2868 | #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2869 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2870 | #define EXTI_FTSR_TR10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2871 | #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2872 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2873 | #define EXTI_FTSR_TR11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2874 | #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2875 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2876 | #define EXTI_FTSR_TR12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2877 | #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2878 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2879 | #define EXTI_FTSR_TR13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2880 | #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2881 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2882 | #define EXTI_FTSR_TR14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2883 | #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2884 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2885 | #define EXTI_FTSR_TR15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2886 | #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2887 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2888 | #define EXTI_FTSR_TR16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2889 | #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2890 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2891 | #define EXTI_FTSR_TR17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2892 | #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2893 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2894 | #define EXTI_FTSR_TR18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2895 | #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2896 | #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2897 | #define EXTI_FTSR_TR19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2898 | #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2899 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2900 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2901 | /* References Defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2902 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
| Pawel Zarembski |
0:01f31e923fe2 | 2903 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
| Pawel Zarembski |
0:01f31e923fe2 | 2904 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
| Pawel Zarembski |
0:01f31e923fe2 | 2905 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
| Pawel Zarembski |
0:01f31e923fe2 | 2906 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
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0:01f31e923fe2 | 2907 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
| Pawel Zarembski |
0:01f31e923fe2 | 2908 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
| Pawel Zarembski |
0:01f31e923fe2 | 2909 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
| Pawel Zarembski |
0:01f31e923fe2 | 2910 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
| Pawel Zarembski |
0:01f31e923fe2 | 2911 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
| Pawel Zarembski |
0:01f31e923fe2 | 2912 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
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0:01f31e923fe2 | 2913 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
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0:01f31e923fe2 | 2914 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
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0:01f31e923fe2 | 2915 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
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0:01f31e923fe2 | 2916 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
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0:01f31e923fe2 | 2917 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
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0:01f31e923fe2 | 2918 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
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0:01f31e923fe2 | 2919 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
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0:01f31e923fe2 | 2920 | #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 |
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0:01f31e923fe2 | 2921 | #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 |
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0:01f31e923fe2 | 2922 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2923 | /****************** Bit definition for EXTI_SWIER register ******************/ |
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0:01f31e923fe2 | 2924 | #define EXTI_SWIER_SWIER0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2925 | #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2926 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2927 | #define EXTI_SWIER_SWIER1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2928 | #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2929 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2930 | #define EXTI_SWIER_SWIER2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2931 | #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2932 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2933 | #define EXTI_SWIER_SWIER3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2934 | #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2935 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2936 | #define EXTI_SWIER_SWIER4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2937 | #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2938 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2939 | #define EXTI_SWIER_SWIER5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2940 | #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2941 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2942 | #define EXTI_SWIER_SWIER6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2943 | #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2944 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2945 | #define EXTI_SWIER_SWIER7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2946 | #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2947 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2948 | #define EXTI_SWIER_SWIER8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2949 | #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2950 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2951 | #define EXTI_SWIER_SWIER9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2952 | #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2953 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2954 | #define EXTI_SWIER_SWIER10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2955 | #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2956 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2957 | #define EXTI_SWIER_SWIER11_Pos (11U) |
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0:01f31e923fe2 | 2958 | #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2959 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2960 | #define EXTI_SWIER_SWIER12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2961 | #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2962 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2963 | #define EXTI_SWIER_SWIER13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2964 | #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2965 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2966 | #define EXTI_SWIER_SWIER14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2967 | #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2968 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2969 | #define EXTI_SWIER_SWIER15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2970 | #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2971 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2972 | #define EXTI_SWIER_SWIER16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2973 | #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2974 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2975 | #define EXTI_SWIER_SWIER17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2976 | #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2977 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2978 | #define EXTI_SWIER_SWIER18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2979 | #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2980 | #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2981 | #define EXTI_SWIER_SWIER19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 2982 | #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2983 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2984 | |
| Pawel Zarembski |
0:01f31e923fe2 | 2985 | /* References Defines */ |
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0:01f31e923fe2 | 2986 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
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0:01f31e923fe2 | 2987 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
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0:01f31e923fe2 | 2988 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
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0:01f31e923fe2 | 2989 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
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0:01f31e923fe2 | 2990 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
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0:01f31e923fe2 | 2991 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
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0:01f31e923fe2 | 2992 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
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0:01f31e923fe2 | 2993 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
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0:01f31e923fe2 | 2994 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
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0:01f31e923fe2 | 2995 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
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0:01f31e923fe2 | 2996 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
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0:01f31e923fe2 | 2997 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
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0:01f31e923fe2 | 2998 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
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0:01f31e923fe2 | 2999 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
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0:01f31e923fe2 | 3000 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
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0:01f31e923fe2 | 3001 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
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0:01f31e923fe2 | 3002 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
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0:01f31e923fe2 | 3003 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
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0:01f31e923fe2 | 3004 | #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 |
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0:01f31e923fe2 | 3005 | #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 |
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0:01f31e923fe2 | 3006 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3007 | /******************* Bit definition for EXTI_PR register ********************/ |
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0:01f31e923fe2 | 3008 | #define EXTI_PR_PR0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3009 | #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3010 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3011 | #define EXTI_PR_PR1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3012 | #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3013 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
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0:01f31e923fe2 | 3014 | #define EXTI_PR_PR2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3015 | #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3016 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
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0:01f31e923fe2 | 3017 | #define EXTI_PR_PR3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3018 | #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3019 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
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0:01f31e923fe2 | 3020 | #define EXTI_PR_PR4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3021 | #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3022 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
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0:01f31e923fe2 | 3023 | #define EXTI_PR_PR5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3024 | #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3025 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
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0:01f31e923fe2 | 3026 | #define EXTI_PR_PR6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3027 | #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3028 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
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0:01f31e923fe2 | 3029 | #define EXTI_PR_PR7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3030 | #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3031 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
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0:01f31e923fe2 | 3032 | #define EXTI_PR_PR8_Pos (8U) |
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0:01f31e923fe2 | 3033 | #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 3034 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
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0:01f31e923fe2 | 3035 | #define EXTI_PR_PR9_Pos (9U) |
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0:01f31e923fe2 | 3036 | #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 3037 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
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0:01f31e923fe2 | 3038 | #define EXTI_PR_PR10_Pos (10U) |
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0:01f31e923fe2 | 3039 | #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 3040 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
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0:01f31e923fe2 | 3041 | #define EXTI_PR_PR11_Pos (11U) |
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0:01f31e923fe2 | 3042 | #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 3043 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
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0:01f31e923fe2 | 3044 | #define EXTI_PR_PR12_Pos (12U) |
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0:01f31e923fe2 | 3045 | #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 3046 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
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0:01f31e923fe2 | 3047 | #define EXTI_PR_PR13_Pos (13U) |
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0:01f31e923fe2 | 3048 | #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 3049 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
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0:01f31e923fe2 | 3050 | #define EXTI_PR_PR14_Pos (14U) |
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0:01f31e923fe2 | 3051 | #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 3052 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
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0:01f31e923fe2 | 3053 | #define EXTI_PR_PR15_Pos (15U) |
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0:01f31e923fe2 | 3054 | #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 3055 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
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0:01f31e923fe2 | 3056 | #define EXTI_PR_PR16_Pos (16U) |
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0:01f31e923fe2 | 3057 | #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 3058 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
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0:01f31e923fe2 | 3059 | #define EXTI_PR_PR17_Pos (17U) |
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0:01f31e923fe2 | 3060 | #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 3061 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
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0:01f31e923fe2 | 3062 | #define EXTI_PR_PR18_Pos (18U) |
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0:01f31e923fe2 | 3063 | #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 3064 | #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
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0:01f31e923fe2 | 3065 | #define EXTI_PR_PR19_Pos (19U) |
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0:01f31e923fe2 | 3066 | #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 3067 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
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0:01f31e923fe2 | 3068 | |
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0:01f31e923fe2 | 3069 | /* References Defines */ |
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0:01f31e923fe2 | 3070 | #define EXTI_PR_PIF0 EXTI_PR_PR0 |
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0:01f31e923fe2 | 3071 | #define EXTI_PR_PIF1 EXTI_PR_PR1 |
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0:01f31e923fe2 | 3072 | #define EXTI_PR_PIF2 EXTI_PR_PR2 |
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0:01f31e923fe2 | 3073 | #define EXTI_PR_PIF3 EXTI_PR_PR3 |
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0:01f31e923fe2 | 3074 | #define EXTI_PR_PIF4 EXTI_PR_PR4 |
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0:01f31e923fe2 | 3075 | #define EXTI_PR_PIF5 EXTI_PR_PR5 |
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0:01f31e923fe2 | 3076 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
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0:01f31e923fe2 | 3077 | #define EXTI_PR_PIF7 EXTI_PR_PR7 |
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0:01f31e923fe2 | 3078 | #define EXTI_PR_PIF8 EXTI_PR_PR8 |
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0:01f31e923fe2 | 3079 | #define EXTI_PR_PIF9 EXTI_PR_PR9 |
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0:01f31e923fe2 | 3080 | #define EXTI_PR_PIF10 EXTI_PR_PR10 |
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0:01f31e923fe2 | 3081 | #define EXTI_PR_PIF11 EXTI_PR_PR11 |
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0:01f31e923fe2 | 3082 | #define EXTI_PR_PIF12 EXTI_PR_PR12 |
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0:01f31e923fe2 | 3083 | #define EXTI_PR_PIF13 EXTI_PR_PR13 |
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0:01f31e923fe2 | 3084 | #define EXTI_PR_PIF14 EXTI_PR_PR14 |
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0:01f31e923fe2 | 3085 | #define EXTI_PR_PIF15 EXTI_PR_PR15 |
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0:01f31e923fe2 | 3086 | #define EXTI_PR_PIF16 EXTI_PR_PR16 |
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0:01f31e923fe2 | 3087 | #define EXTI_PR_PIF17 EXTI_PR_PR17 |
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0:01f31e923fe2 | 3088 | #define EXTI_PR_PIF18 EXTI_PR_PR18 |
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0:01f31e923fe2 | 3089 | #define EXTI_PR_PIF19 EXTI_PR_PR19 |
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0:01f31e923fe2 | 3090 | |
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0:01f31e923fe2 | 3091 | /******************************************************************************/ |
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0:01f31e923fe2 | 3092 | /* */ |
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0:01f31e923fe2 | 3093 | /* DMA Controller */ |
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0:01f31e923fe2 | 3094 | /* */ |
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0:01f31e923fe2 | 3095 | /******************************************************************************/ |
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0:01f31e923fe2 | 3096 | |
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0:01f31e923fe2 | 3097 | /******************* Bit definition for DMA_ISR register ********************/ |
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0:01f31e923fe2 | 3098 | #define DMA_ISR_GIF1_Pos (0U) |
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0:01f31e923fe2 | 3099 | #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 3100 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
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0:01f31e923fe2 | 3101 | #define DMA_ISR_TCIF1_Pos (1U) |
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0:01f31e923fe2 | 3102 | #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 3103 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
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0:01f31e923fe2 | 3104 | #define DMA_ISR_HTIF1_Pos (2U) |
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0:01f31e923fe2 | 3105 | #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 3106 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
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0:01f31e923fe2 | 3107 | #define DMA_ISR_TEIF1_Pos (3U) |
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0:01f31e923fe2 | 3108 | #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 3109 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
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0:01f31e923fe2 | 3110 | #define DMA_ISR_GIF2_Pos (4U) |
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0:01f31e923fe2 | 3111 | #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 3112 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
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0:01f31e923fe2 | 3113 | #define DMA_ISR_TCIF2_Pos (5U) |
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0:01f31e923fe2 | 3114 | #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 3115 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
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0:01f31e923fe2 | 3116 | #define DMA_ISR_HTIF2_Pos (6U) |
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0:01f31e923fe2 | 3117 | #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 3118 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
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0:01f31e923fe2 | 3119 | #define DMA_ISR_TEIF2_Pos (7U) |
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0:01f31e923fe2 | 3120 | #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 3121 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
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0:01f31e923fe2 | 3122 | #define DMA_ISR_GIF3_Pos (8U) |
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0:01f31e923fe2 | 3123 | #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 3124 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
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0:01f31e923fe2 | 3125 | #define DMA_ISR_TCIF3_Pos (9U) |
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0:01f31e923fe2 | 3126 | #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 3127 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
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0:01f31e923fe2 | 3128 | #define DMA_ISR_HTIF3_Pos (10U) |
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0:01f31e923fe2 | 3129 | #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 3130 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
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0:01f31e923fe2 | 3131 | #define DMA_ISR_TEIF3_Pos (11U) |
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0:01f31e923fe2 | 3132 | #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 3133 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
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0:01f31e923fe2 | 3134 | #define DMA_ISR_GIF4_Pos (12U) |
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0:01f31e923fe2 | 3135 | #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 3136 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
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0:01f31e923fe2 | 3137 | #define DMA_ISR_TCIF4_Pos (13U) |
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0:01f31e923fe2 | 3138 | #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 3139 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
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0:01f31e923fe2 | 3140 | #define DMA_ISR_HTIF4_Pos (14U) |
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0:01f31e923fe2 | 3141 | #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 3142 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
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0:01f31e923fe2 | 3143 | #define DMA_ISR_TEIF4_Pos (15U) |
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0:01f31e923fe2 | 3144 | #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 3145 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
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0:01f31e923fe2 | 3146 | #define DMA_ISR_GIF5_Pos (16U) |
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0:01f31e923fe2 | 3147 | #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 3148 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
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0:01f31e923fe2 | 3149 | #define DMA_ISR_TCIF5_Pos (17U) |
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0:01f31e923fe2 | 3150 | #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 3151 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
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0:01f31e923fe2 | 3152 | #define DMA_ISR_HTIF5_Pos (18U) |
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0:01f31e923fe2 | 3153 | #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 3154 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
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0:01f31e923fe2 | 3155 | #define DMA_ISR_TEIF5_Pos (19U) |
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0:01f31e923fe2 | 3156 | #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 3157 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
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0:01f31e923fe2 | 3158 | #define DMA_ISR_GIF6_Pos (20U) |
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0:01f31e923fe2 | 3159 | #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 3160 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
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0:01f31e923fe2 | 3161 | #define DMA_ISR_TCIF6_Pos (21U) |
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0:01f31e923fe2 | 3162 | #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 3163 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
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0:01f31e923fe2 | 3164 | #define DMA_ISR_HTIF6_Pos (22U) |
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0:01f31e923fe2 | 3165 | #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 3166 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
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0:01f31e923fe2 | 3167 | #define DMA_ISR_TEIF6_Pos (23U) |
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0:01f31e923fe2 | 3168 | #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 3169 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
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0:01f31e923fe2 | 3170 | #define DMA_ISR_GIF7_Pos (24U) |
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0:01f31e923fe2 | 3171 | #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 3172 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
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0:01f31e923fe2 | 3173 | #define DMA_ISR_TCIF7_Pos (25U) |
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0:01f31e923fe2 | 3174 | #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 3175 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
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0:01f31e923fe2 | 3176 | #define DMA_ISR_HTIF7_Pos (26U) |
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0:01f31e923fe2 | 3177 | #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 3178 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
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0:01f31e923fe2 | 3179 | #define DMA_ISR_TEIF7_Pos (27U) |
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0:01f31e923fe2 | 3180 | #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 3181 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
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0:01f31e923fe2 | 3182 | |
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0:01f31e923fe2 | 3183 | /******************* Bit definition for DMA_IFCR register *******************/ |
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0:01f31e923fe2 | 3184 | #define DMA_IFCR_CGIF1_Pos (0U) |
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0:01f31e923fe2 | 3185 | #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 3186 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
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0:01f31e923fe2 | 3187 | #define DMA_IFCR_CTCIF1_Pos (1U) |
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0:01f31e923fe2 | 3188 | #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 3189 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
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0:01f31e923fe2 | 3190 | #define DMA_IFCR_CHTIF1_Pos (2U) |
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0:01f31e923fe2 | 3191 | #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 3192 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
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0:01f31e923fe2 | 3193 | #define DMA_IFCR_CTEIF1_Pos (3U) |
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0:01f31e923fe2 | 3194 | #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3195 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
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0:01f31e923fe2 | 3196 | #define DMA_IFCR_CGIF2_Pos (4U) |
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0:01f31e923fe2 | 3197 | #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 3198 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
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0:01f31e923fe2 | 3199 | #define DMA_IFCR_CTCIF2_Pos (5U) |
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0:01f31e923fe2 | 3200 | #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 3201 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
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0:01f31e923fe2 | 3202 | #define DMA_IFCR_CHTIF2_Pos (6U) |
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0:01f31e923fe2 | 3203 | #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 3204 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
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0:01f31e923fe2 | 3205 | #define DMA_IFCR_CTEIF2_Pos (7U) |
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0:01f31e923fe2 | 3206 | #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 3207 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
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0:01f31e923fe2 | 3208 | #define DMA_IFCR_CGIF3_Pos (8U) |
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0:01f31e923fe2 | 3209 | #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 3210 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
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0:01f31e923fe2 | 3211 | #define DMA_IFCR_CTCIF3_Pos (9U) |
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0:01f31e923fe2 | 3212 | #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3213 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
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0:01f31e923fe2 | 3214 | #define DMA_IFCR_CHTIF3_Pos (10U) |
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0:01f31e923fe2 | 3215 | #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3216 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
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0:01f31e923fe2 | 3217 | #define DMA_IFCR_CTEIF3_Pos (11U) |
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0:01f31e923fe2 | 3218 | #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 3219 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
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0:01f31e923fe2 | 3220 | #define DMA_IFCR_CGIF4_Pos (12U) |
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0:01f31e923fe2 | 3221 | #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 3222 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
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0:01f31e923fe2 | 3223 | #define DMA_IFCR_CTCIF4_Pos (13U) |
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0:01f31e923fe2 | 3224 | #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 3225 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
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0:01f31e923fe2 | 3226 | #define DMA_IFCR_CHTIF4_Pos (14U) |
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0:01f31e923fe2 | 3227 | #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 3228 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
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0:01f31e923fe2 | 3229 | #define DMA_IFCR_CTEIF4_Pos (15U) |
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0:01f31e923fe2 | 3230 | #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3231 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
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0:01f31e923fe2 | 3232 | #define DMA_IFCR_CGIF5_Pos (16U) |
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0:01f31e923fe2 | 3233 | #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 3234 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3235 | #define DMA_IFCR_CTCIF5_Pos (17U) |
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0:01f31e923fe2 | 3236 | #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3237 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3238 | #define DMA_IFCR_CHTIF5_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3239 | #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3240 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3241 | #define DMA_IFCR_CTEIF5_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3242 | #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3243 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3244 | #define DMA_IFCR_CGIF6_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3245 | #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3246 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
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0:01f31e923fe2 | 3247 | #define DMA_IFCR_CTCIF6_Pos (21U) |
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0:01f31e923fe2 | 3248 | #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3249 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3250 | #define DMA_IFCR_CHTIF6_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3251 | #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 3252 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3253 | #define DMA_IFCR_CTEIF6_Pos (23U) |
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0:01f31e923fe2 | 3254 | #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3255 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3256 | #define DMA_IFCR_CGIF7_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3257 | #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3258 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3259 | #define DMA_IFCR_CTCIF7_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3260 | #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3261 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3262 | #define DMA_IFCR_CHTIF7_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3263 | #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3264 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3265 | #define DMA_IFCR_CTEIF7_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3266 | #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3267 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3268 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3269 | /******************* Bit definition for DMA_CCR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3270 | #define DMA_CCR_EN_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3271 | #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3272 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3273 | #define DMA_CCR_TCIE_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3274 | #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3275 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3276 | #define DMA_CCR_HTIE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3277 | #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3278 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3279 | #define DMA_CCR_TEIE_Pos (3U) |
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0:01f31e923fe2 | 3280 | #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3281 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
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0:01f31e923fe2 | 3282 | #define DMA_CCR_DIR_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3283 | #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3284 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
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0:01f31e923fe2 | 3285 | #define DMA_CCR_CIRC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3286 | #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3287 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
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0:01f31e923fe2 | 3288 | #define DMA_CCR_PINC_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3289 | #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3290 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3291 | #define DMA_CCR_MINC_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3292 | #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3293 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3294 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3295 | #define DMA_CCR_PSIZE_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3296 | #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3297 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3298 | #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3299 | #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3300 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3301 | #define DMA_CCR_MSIZE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3302 | #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3303 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3304 | #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3305 | #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3306 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3307 | #define DMA_CCR_PL_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3308 | #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3309 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3310 | #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 3311 | #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 3312 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3313 | #define DMA_CCR_MEM2MEM_Pos (14U) |
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0:01f31e923fe2 | 3314 | #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3315 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3316 | |
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0:01f31e923fe2 | 3317 | /****************** Bit definition for DMA_CNDTR register ******************/ |
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0:01f31e923fe2 | 3318 | #define DMA_CNDTR_NDT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3319 | #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3320 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
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0:01f31e923fe2 | 3321 | |
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0:01f31e923fe2 | 3322 | /****************** Bit definition for DMA_CPAR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3323 | #define DMA_CPAR_PA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3324 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3325 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
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0:01f31e923fe2 | 3326 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3327 | /****************** Bit definition for DMA_CMAR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3328 | #define DMA_CMAR_MA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3329 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3330 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
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0:01f31e923fe2 | 3331 | |
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0:01f31e923fe2 | 3332 | /******************************************************************************/ |
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0:01f31e923fe2 | 3333 | /* */ |
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0:01f31e923fe2 | 3334 | /* Analog to Digital Converter (ADC) */ |
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0:01f31e923fe2 | 3335 | /* */ |
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0:01f31e923fe2 | 3336 | /******************************************************************************/ |
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0:01f31e923fe2 | 3337 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3338 | /* |
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0:01f31e923fe2 | 3339 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) |
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0:01f31e923fe2 | 3340 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3341 | #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ |
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0:01f31e923fe2 | 3342 | |
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0:01f31e923fe2 | 3343 | /******************** Bit definition for ADC_SR register ********************/ |
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0:01f31e923fe2 | 3344 | #define ADC_SR_AWD_Pos (0U) |
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0:01f31e923fe2 | 3345 | #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 3346 | #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ |
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0:01f31e923fe2 | 3347 | #define ADC_SR_EOS_Pos (1U) |
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0:01f31e923fe2 | 3348 | #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 3349 | #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3350 | #define ADC_SR_JEOS_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3351 | #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3352 | #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3353 | #define ADC_SR_JSTRT_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3354 | #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3355 | #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3356 | #define ADC_SR_STRT_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3357 | #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3358 | #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3359 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3360 | /* Legacy defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3361 | #define ADC_SR_EOC (ADC_SR_EOS) |
| Pawel Zarembski |
0:01f31e923fe2 | 3362 | #define ADC_SR_JEOC (ADC_SR_JEOS) |
| Pawel Zarembski |
0:01f31e923fe2 | 3363 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3364 | /******************* Bit definition for ADC_CR1 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3365 | #define ADC_CR1_AWDCH_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3366 | #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3367 | #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3368 | #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3369 | #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3370 | #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3371 | #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3372 | #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3373 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3374 | #define ADC_CR1_EOSIE_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3375 | #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3376 | #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3377 | #define ADC_CR1_AWDIE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3378 | #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3379 | #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3380 | #define ADC_CR1_JEOSIE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3381 | #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3382 | #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3383 | #define ADC_CR1_SCAN_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3384 | #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3385 | #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3386 | #define ADC_CR1_AWDSGL_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3387 | #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3388 | #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3389 | #define ADC_CR1_JAUTO_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3390 | #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3391 | #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3392 | #define ADC_CR1_DISCEN_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3393 | #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3394 | #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3395 | #define ADC_CR1_JDISCEN_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3396 | #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3397 | #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3398 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3399 | #define ADC_CR1_DISCNUM_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3400 | #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3401 | #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3402 | #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3403 | #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3404 | #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3405 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3406 | #define ADC_CR1_DUALMOD_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3407 | #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3408 | #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3409 | #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3410 | #define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3411 | #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3412 | #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3413 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3414 | #define ADC_CR1_JAWDEN_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3415 | #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3416 | #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3417 | #define ADC_CR1_AWDEN_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3418 | #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3419 | #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3420 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3421 | /* Legacy defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3422 | #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) |
| Pawel Zarembski |
0:01f31e923fe2 | 3423 | #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) |
| Pawel Zarembski |
0:01f31e923fe2 | 3424 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3425 | /******************* Bit definition for ADC_CR2 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3426 | #define ADC_CR2_ADON_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3427 | #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3428 | #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3429 | #define ADC_CR2_CONT_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3430 | #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3431 | #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3432 | #define ADC_CR2_CAL_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3433 | #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3434 | #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3435 | #define ADC_CR2_RSTCAL_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3436 | #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3437 | #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3438 | #define ADC_CR2_DMA_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3439 | #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3440 | #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3441 | #define ADC_CR2_ALIGN_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3442 | #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3443 | #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3444 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3445 | #define ADC_CR2_JEXTSEL_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3446 | #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3447 | #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3448 | #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3449 | #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3450 | #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3451 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3452 | #define ADC_CR2_JEXTTRIG_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3453 | #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3454 | #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3455 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3456 | #define ADC_CR2_EXTSEL_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3457 | #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3458 | #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3459 | #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3460 | #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3461 | #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3462 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3463 | #define ADC_CR2_EXTTRIG_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3464 | #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3465 | #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3466 | #define ADC_CR2_JSWSTART_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3467 | #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3468 | #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3469 | #define ADC_CR2_SWSTART_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3470 | #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3471 | #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3472 | #define ADC_CR2_TSVREFE_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3473 | #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3474 | #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3475 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3476 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3477 | #define ADC_SMPR1_SMP10_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3478 | #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3479 | #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3480 | #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3481 | #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3482 | #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3483 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3484 | #define ADC_SMPR1_SMP11_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3485 | #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3486 | #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3487 | #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3488 | #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3489 | #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3490 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3491 | #define ADC_SMPR1_SMP12_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3492 | #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3493 | #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3494 | #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3495 | #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3496 | #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3497 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3498 | #define ADC_SMPR1_SMP13_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3499 | #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3500 | #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3501 | #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3502 | #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3503 | #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3504 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3505 | #define ADC_SMPR1_SMP14_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3506 | #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3507 | #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3508 | #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3509 | #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3510 | #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3511 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3512 | #define ADC_SMPR1_SMP15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3513 | #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3514 | #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3515 | #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3516 | #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3517 | #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3518 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3519 | #define ADC_SMPR1_SMP16_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3520 | #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3521 | #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3522 | #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3523 | #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3524 | #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3525 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3526 | #define ADC_SMPR1_SMP17_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3527 | #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3528 | #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3529 | #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3530 | #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3531 | #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3532 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3533 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3534 | #define ADC_SMPR2_SMP0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3535 | #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3536 | #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3537 | #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3538 | #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3539 | #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3540 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3541 | #define ADC_SMPR2_SMP1_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3542 | #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3543 | #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3544 | #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3545 | #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3546 | #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3547 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3548 | #define ADC_SMPR2_SMP2_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3549 | #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3550 | #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3551 | #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3552 | #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3553 | #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3554 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3555 | #define ADC_SMPR2_SMP3_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3556 | #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3557 | #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3558 | #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3559 | #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3560 | #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3561 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3562 | #define ADC_SMPR2_SMP4_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3563 | #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3564 | #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3565 | #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3566 | #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3567 | #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3568 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3569 | #define ADC_SMPR2_SMP5_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3570 | #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3571 | #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3572 | #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3573 | #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3574 | #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3575 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3576 | #define ADC_SMPR2_SMP6_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3577 | #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3578 | #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3579 | #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3580 | #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3581 | #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3582 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3583 | #define ADC_SMPR2_SMP7_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3584 | #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3585 | #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3586 | #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3587 | #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3588 | #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3589 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3590 | #define ADC_SMPR2_SMP8_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3591 | #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3592 | #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3593 | #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3594 | #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3595 | #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3596 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3597 | #define ADC_SMPR2_SMP9_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3598 | #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3599 | #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3600 | #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3601 | #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3602 | #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3603 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3604 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3605 | #define ADC_JOFR1_JOFFSET1_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3606 | #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3607 | #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3608 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3609 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3610 | #define ADC_JOFR2_JOFFSET2_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3611 | #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3612 | #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3613 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3614 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3615 | #define ADC_JOFR3_JOFFSET3_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3616 | #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3617 | #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3618 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3619 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3620 | #define ADC_JOFR4_JOFFSET4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3621 | #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3622 | #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3623 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3624 | /******************* Bit definition for ADC_HTR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3625 | #define ADC_HTR_HT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3626 | #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3627 | #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3628 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3629 | /******************* Bit definition for ADC_LTR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3630 | #define ADC_LTR_LT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3631 | #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3632 | #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3633 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3634 | /******************* Bit definition for ADC_SQR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3635 | #define ADC_SQR1_SQ13_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3636 | #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3637 | #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3638 | #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3639 | #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3640 | #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3641 | #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3642 | #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3643 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3644 | #define ADC_SQR1_SQ14_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3645 | #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3646 | #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3647 | #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3648 | #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3649 | #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3650 | #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3651 | #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3652 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3653 | #define ADC_SQR1_SQ15_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3654 | #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3655 | #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3656 | #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3657 | #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3658 | #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3659 | #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3660 | #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3661 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3662 | #define ADC_SQR1_SQ16_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3663 | #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3664 | #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3665 | #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3666 | #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3667 | #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3668 | #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3669 | #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3670 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3671 | #define ADC_SQR1_L_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3672 | #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3673 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3674 | #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3675 | #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3676 | #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3677 | #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3678 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3679 | /******************* Bit definition for ADC_SQR2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3680 | #define ADC_SQR2_SQ7_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3681 | #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3682 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3683 | #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3684 | #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3685 | #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3686 | #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3687 | #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3688 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3689 | #define ADC_SQR2_SQ8_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3690 | #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3691 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3692 | #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3693 | #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3694 | #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3695 | #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3696 | #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3697 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3698 | #define ADC_SQR2_SQ9_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3699 | #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3700 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3701 | #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3702 | #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3703 | #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3704 | #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3705 | #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3706 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3707 | #define ADC_SQR2_SQ10_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3708 | #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3709 | #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3710 | #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3711 | #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3712 | #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3713 | #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3714 | #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3715 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3716 | #define ADC_SQR2_SQ11_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3717 | #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3718 | #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3719 | #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3720 | #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3721 | #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3722 | #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3723 | #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3724 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3725 | #define ADC_SQR2_SQ12_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3726 | #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3727 | #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3728 | #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3729 | #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3730 | #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3731 | #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3732 | #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3733 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3734 | /******************* Bit definition for ADC_SQR3 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3735 | #define ADC_SQR3_SQ1_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3736 | #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3737 | #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3738 | #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3739 | #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3740 | #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3741 | #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3742 | #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3743 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3744 | #define ADC_SQR3_SQ2_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3745 | #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3746 | #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3747 | #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3748 | #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3749 | #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3750 | #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3751 | #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3752 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3753 | #define ADC_SQR3_SQ3_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3754 | #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3755 | #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3756 | #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3757 | #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3758 | #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3759 | #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3760 | #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3761 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3762 | #define ADC_SQR3_SQ4_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3763 | #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3764 | #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3765 | #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3766 | #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3767 | #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3768 | #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3769 | #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3770 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3771 | #define ADC_SQR3_SQ5_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3772 | #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3773 | #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3774 | #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3775 | #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3776 | #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3777 | #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3778 | #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3779 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3780 | #define ADC_SQR3_SQ6_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3781 | #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3782 | #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3783 | #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3784 | #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3785 | #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3786 | #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3787 | #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3788 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3789 | /******************* Bit definition for ADC_JSQR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3790 | #define ADC_JSQR_JSQ1_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3791 | #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3792 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3793 | #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3794 | #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3795 | #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3796 | #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3797 | #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3798 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3799 | #define ADC_JSQR_JSQ2_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3800 | #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3801 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3802 | #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3803 | #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3804 | #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3805 | #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3806 | #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3807 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3808 | #define ADC_JSQR_JSQ3_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3809 | #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3810 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3811 | #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3812 | #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3813 | #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3814 | #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3815 | #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3816 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3817 | #define ADC_JSQR_JSQ4_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3818 | #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3819 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3820 | #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3821 | #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3822 | #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3823 | #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3824 | #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3825 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3826 | #define ADC_JSQR_JL_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3827 | #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3828 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3829 | #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3830 | #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3831 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3832 | /******************* Bit definition for ADC_JDR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3833 | #define ADC_JDR1_JDATA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3834 | #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3835 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3836 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3837 | /******************* Bit definition for ADC_JDR2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3838 | #define ADC_JDR2_JDATA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3839 | #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3840 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3841 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3842 | /******************* Bit definition for ADC_JDR3 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3843 | #define ADC_JDR3_JDATA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3844 | #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3845 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3846 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3847 | /******************* Bit definition for ADC_JDR4 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3848 | #define ADC_JDR4_JDATA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3849 | #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3850 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3851 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3852 | /******************** Bit definition for ADC_DR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3853 | #define ADC_DR_DATA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3854 | #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3855 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3856 | #define ADC_DR_ADC2DATA_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3857 | #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3858 | #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3859 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3860 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3861 | /*****************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3862 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3863 | /* Timers (TIM) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3864 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3865 | /*****************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3866 | /******************* Bit definition for TIM_CR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3867 | #define TIM_CR1_CEN_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3868 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3869 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3870 | #define TIM_CR1_UDIS_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3871 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3872 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3873 | #define TIM_CR1_URS_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3874 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3875 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3876 | #define TIM_CR1_OPM_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3877 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3878 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3879 | #define TIM_CR1_DIR_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3880 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3881 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3882 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3883 | #define TIM_CR1_CMS_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3884 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3885 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3886 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3887 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3888 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3889 | #define TIM_CR1_ARPE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3890 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3891 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3892 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3893 | #define TIM_CR1_CKD_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3894 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3895 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3896 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3897 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3898 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3899 | /******************* Bit definition for TIM_CR2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3900 | #define TIM_CR2_CCPC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3901 | #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3902 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3903 | #define TIM_CR2_CCUS_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3904 | #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3905 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3906 | #define TIM_CR2_CCDS_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3907 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3908 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3909 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3910 | #define TIM_CR2_MMS_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3911 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3912 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3913 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3914 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3915 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3916 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3917 | #define TIM_CR2_TI1S_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3918 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3919 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3920 | #define TIM_CR2_OIS1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3921 | #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3922 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3923 | #define TIM_CR2_OIS1N_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3924 | #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3925 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3926 | #define TIM_CR2_OIS2_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3927 | #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3928 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3929 | #define TIM_CR2_OIS2N_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3930 | #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3931 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3932 | #define TIM_CR2_OIS3_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3933 | #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3934 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3935 | #define TIM_CR2_OIS3N_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3936 | #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3937 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3938 | #define TIM_CR2_OIS4_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3939 | #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3940 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3941 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3942 | /******************* Bit definition for TIM_SMCR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 3943 | #define TIM_SMCR_SMS_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3944 | #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3945 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3946 | #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 3947 | #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 3948 | #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 3949 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3950 | #define TIM_SMCR_OCCS_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3951 | #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3952 | #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ |
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0:01f31e923fe2 | 3953 | |
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0:01f31e923fe2 | 3954 | #define TIM_SMCR_TS_Pos (4U) |
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0:01f31e923fe2 | 3955 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3956 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3957 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 3958 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3959 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 3960 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3961 | #define TIM_SMCR_MSM_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3962 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3963 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
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0:01f31e923fe2 | 3964 | |
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0:01f31e923fe2 | 3965 | #define TIM_SMCR_ETF_Pos (8U) |
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0:01f31e923fe2 | 3966 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
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0:01f31e923fe2 | 3967 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
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0:01f31e923fe2 | 3968 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 3969 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 3970 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 3971 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 3972 | |
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0:01f31e923fe2 | 3973 | #define TIM_SMCR_ETPS_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3974 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3975 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
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0:01f31e923fe2 | 3976 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 3977 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 3978 | |
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0:01f31e923fe2 | 3979 | #define TIM_SMCR_ECE_Pos (14U) |
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0:01f31e923fe2 | 3980 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3981 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
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0:01f31e923fe2 | 3982 | #define TIM_SMCR_ETP_Pos (15U) |
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0:01f31e923fe2 | 3983 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 3984 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
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0:01f31e923fe2 | 3985 | |
| Pawel Zarembski |
0:01f31e923fe2 | 3986 | /******************* Bit definition for TIM_DIER register ******************/ |
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0:01f31e923fe2 | 3987 | #define TIM_DIER_UIE_Pos (0U) |
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0:01f31e923fe2 | 3988 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3989 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
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0:01f31e923fe2 | 3990 | #define TIM_DIER_CC1IE_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3991 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3992 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3993 | #define TIM_DIER_CC2IE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3994 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3995 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
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0:01f31e923fe2 | 3996 | #define TIM_DIER_CC3IE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 3997 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3998 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
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0:01f31e923fe2 | 3999 | #define TIM_DIER_CC4IE_Pos (4U) |
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0:01f31e923fe2 | 4000 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 4001 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
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0:01f31e923fe2 | 4002 | #define TIM_DIER_COMIE_Pos (5U) |
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0:01f31e923fe2 | 4003 | #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 4004 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
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0:01f31e923fe2 | 4005 | #define TIM_DIER_TIE_Pos (6U) |
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0:01f31e923fe2 | 4006 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 4007 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
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0:01f31e923fe2 | 4008 | #define TIM_DIER_BIE_Pos (7U) |
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0:01f31e923fe2 | 4009 | #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 4010 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
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0:01f31e923fe2 | 4011 | #define TIM_DIER_UDE_Pos (8U) |
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0:01f31e923fe2 | 4012 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4013 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4014 | #define TIM_DIER_CC1DE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4015 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4016 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
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0:01f31e923fe2 | 4017 | #define TIM_DIER_CC2DE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4018 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4019 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4020 | #define TIM_DIER_CC3DE_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4021 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4022 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4023 | #define TIM_DIER_CC4DE_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4024 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4025 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4026 | #define TIM_DIER_COMDE_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4027 | #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4028 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4029 | #define TIM_DIER_TDE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4030 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4031 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4032 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4033 | /******************** Bit definition for TIM_SR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4034 | #define TIM_SR_UIF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4035 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4036 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4037 | #define TIM_SR_CC1IF_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4038 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4039 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4040 | #define TIM_SR_CC2IF_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4041 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4042 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4043 | #define TIM_SR_CC3IF_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4044 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4045 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4046 | #define TIM_SR_CC4IF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4047 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4048 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4049 | #define TIM_SR_COMIF_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4050 | #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4051 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4052 | #define TIM_SR_TIF_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4053 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4054 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4055 | #define TIM_SR_BIF_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4056 | #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4057 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4058 | #define TIM_SR_CC1OF_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4059 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4060 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4061 | #define TIM_SR_CC2OF_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4062 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4063 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4064 | #define TIM_SR_CC3OF_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4065 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4066 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4067 | #define TIM_SR_CC4OF_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4068 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4069 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4070 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4071 | /******************* Bit definition for TIM_EGR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4072 | #define TIM_EGR_UG_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4073 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4074 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4075 | #define TIM_EGR_CC1G_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4076 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4077 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4078 | #define TIM_EGR_CC2G_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4079 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4080 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4081 | #define TIM_EGR_CC3G_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4082 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4083 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4084 | #define TIM_EGR_CC4G_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4085 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4086 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4087 | #define TIM_EGR_COMG_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4088 | #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4089 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4090 | #define TIM_EGR_TG_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4091 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4092 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4093 | #define TIM_EGR_BG_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4094 | #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4095 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4096 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4097 | /****************** Bit definition for TIM_CCMR1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4098 | #define TIM_CCMR1_CC1S_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4099 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4100 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4101 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4102 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4103 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4104 | #define TIM_CCMR1_OC1FE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4105 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4106 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4107 | #define TIM_CCMR1_OC1PE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4108 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4109 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4110 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4111 | #define TIM_CCMR1_OC1M_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4112 | #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4113 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4114 | #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4115 | #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4116 | #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4117 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4118 | #define TIM_CCMR1_OC1CE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4119 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4120 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4121 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4122 | #define TIM_CCMR1_CC2S_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4123 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4124 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4125 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4126 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4127 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4128 | #define TIM_CCMR1_OC2FE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4129 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4130 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4131 | #define TIM_CCMR1_OC2PE_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4132 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4133 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4134 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4135 | #define TIM_CCMR1_OC2M_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4136 | #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4137 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4138 | #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4139 | #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4140 | #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4141 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4142 | #define TIM_CCMR1_OC2CE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4143 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4144 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4145 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4146 | /*---------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4147 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4148 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4149 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4150 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4151 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4152 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4153 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4154 | #define TIM_CCMR1_IC1F_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4155 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4156 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4157 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4158 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4159 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4160 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4161 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4162 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4163 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4164 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4165 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4166 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4167 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4168 | #define TIM_CCMR1_IC2F_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4169 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4170 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4171 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4172 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4173 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4174 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4175 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4176 | /****************** Bit definition for TIM_CCMR2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4177 | #define TIM_CCMR2_CC3S_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4178 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4179 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4180 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4181 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4182 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4183 | #define TIM_CCMR2_OC3FE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4184 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4185 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4186 | #define TIM_CCMR2_OC3PE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4187 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4188 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4189 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4190 | #define TIM_CCMR2_OC3M_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4191 | #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4192 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4193 | #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4194 | #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4195 | #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4196 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4197 | #define TIM_CCMR2_OC3CE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4198 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4199 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4200 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4201 | #define TIM_CCMR2_CC4S_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4202 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4203 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4204 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4205 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4206 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4207 | #define TIM_CCMR2_OC4FE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4208 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4209 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4210 | #define TIM_CCMR2_OC4PE_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4211 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4212 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4213 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4214 | #define TIM_CCMR2_OC4M_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4215 | #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4216 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4217 | #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4218 | #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4219 | #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4220 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4221 | #define TIM_CCMR2_OC4CE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4222 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4223 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4224 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4225 | /*---------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4226 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4227 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4228 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4229 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4230 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4231 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4232 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4233 | #define TIM_CCMR2_IC3F_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4234 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4235 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4236 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4237 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4238 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4239 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4240 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4241 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4242 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4243 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4244 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4245 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4246 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4247 | #define TIM_CCMR2_IC4F_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4248 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4249 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4250 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4251 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4252 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4253 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4254 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4255 | /******************* Bit definition for TIM_CCER register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4256 | #define TIM_CCER_CC1E_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4257 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4258 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4259 | #define TIM_CCER_CC1P_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4260 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4261 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4262 | #define TIM_CCER_CC1NE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4263 | #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4264 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4265 | #define TIM_CCER_CC1NP_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4266 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4267 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4268 | #define TIM_CCER_CC2E_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4269 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4270 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4271 | #define TIM_CCER_CC2P_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4272 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4273 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4274 | #define TIM_CCER_CC2NE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4275 | #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4276 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4277 | #define TIM_CCER_CC2NP_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4278 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4279 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4280 | #define TIM_CCER_CC3E_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4281 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4282 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4283 | #define TIM_CCER_CC3P_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4284 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4285 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4286 | #define TIM_CCER_CC3NE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4287 | #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4288 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4289 | #define TIM_CCER_CC3NP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4290 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4291 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4292 | #define TIM_CCER_CC4E_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4293 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4294 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4295 | #define TIM_CCER_CC4P_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4296 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4297 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4298 | #define TIM_CCER_CC4NP_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4299 | #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4300 | #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4301 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4302 | /******************* Bit definition for TIM_CNT register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4303 | #define TIM_CNT_CNT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4304 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4305 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4306 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4307 | /******************* Bit definition for TIM_PSC register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4308 | #define TIM_PSC_PSC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4309 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4310 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4311 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4312 | /******************* Bit definition for TIM_ARR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4313 | #define TIM_ARR_ARR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4314 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4315 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4316 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4317 | /******************* Bit definition for TIM_RCR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4318 | #define TIM_RCR_REP_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4319 | #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4320 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4321 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4322 | /******************* Bit definition for TIM_CCR1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4323 | #define TIM_CCR1_CCR1_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4324 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4325 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4326 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4327 | /******************* Bit definition for TIM_CCR2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4328 | #define TIM_CCR2_CCR2_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4329 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4330 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4331 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4332 | /******************* Bit definition for TIM_CCR3 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4333 | #define TIM_CCR3_CCR3_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4334 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4335 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4336 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4337 | /******************* Bit definition for TIM_CCR4 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4338 | #define TIM_CCR4_CCR4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4339 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4340 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4341 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4342 | /******************* Bit definition for TIM_BDTR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4343 | #define TIM_BDTR_DTG_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4344 | #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4345 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4346 | #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4347 | #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4348 | #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4349 | #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4350 | #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4351 | #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4352 | #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4353 | #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4354 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4355 | #define TIM_BDTR_LOCK_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4356 | #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4357 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4358 | #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4359 | #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4360 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4361 | #define TIM_BDTR_OSSI_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4362 | #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4363 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4364 | #define TIM_BDTR_OSSR_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4365 | #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4366 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4367 | #define TIM_BDTR_BKE_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4368 | #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4369 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4370 | #define TIM_BDTR_BKP_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4371 | #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4372 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4373 | #define TIM_BDTR_AOE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4374 | #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4375 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4376 | #define TIM_BDTR_MOE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4377 | #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4378 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4379 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4380 | /******************* Bit definition for TIM_DCR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4381 | #define TIM_DCR_DBA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4382 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4383 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4384 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4385 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4386 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4387 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4388 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4389 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4390 | #define TIM_DCR_DBL_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4391 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4392 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4393 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4394 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4395 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4396 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4397 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4398 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4399 | /******************* Bit definition for TIM_DMAR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4400 | #define TIM_DMAR_DMAB_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4401 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4402 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4403 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4404 | /******************* Bit definition for TIM_OR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4405 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4406 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4407 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4408 | /* Real-Time Clock */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4409 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4410 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4411 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4412 | /******************* Bit definition for RTC_CRH register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4413 | #define RTC_CRH_SECIE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4414 | #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4415 | #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4416 | #define RTC_CRH_ALRIE_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4417 | #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4418 | #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4419 | #define RTC_CRH_OWIE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4420 | #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4421 | #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4422 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4423 | /******************* Bit definition for RTC_CRL register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4424 | #define RTC_CRL_SECF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4425 | #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4426 | #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4427 | #define RTC_CRL_ALRF_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4428 | #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4429 | #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4430 | #define RTC_CRL_OWF_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4431 | #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4432 | #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4433 | #define RTC_CRL_RSF_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4434 | #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4435 | #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4436 | #define RTC_CRL_CNF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4437 | #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4438 | #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4439 | #define RTC_CRL_RTOFF_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4440 | #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4441 | #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4442 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4443 | /******************* Bit definition for RTC_PRLH register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4444 | #define RTC_PRLH_PRL_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4445 | #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4446 | #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4447 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4448 | /******************* Bit definition for RTC_PRLL register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4449 | #define RTC_PRLL_PRL_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4450 | #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4451 | #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4452 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4453 | /******************* Bit definition for RTC_DIVH register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4454 | #define RTC_DIVH_RTC_DIV_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4455 | #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4456 | #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4457 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4458 | /******************* Bit definition for RTC_DIVL register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4459 | #define RTC_DIVL_RTC_DIV_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4460 | #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4461 | #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4462 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4463 | /******************* Bit definition for RTC_CNTH register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4464 | #define RTC_CNTH_RTC_CNT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4465 | #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4466 | #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4467 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4468 | /******************* Bit definition for RTC_CNTL register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4469 | #define RTC_CNTL_RTC_CNT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4470 | #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4471 | #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4472 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4473 | /******************* Bit definition for RTC_ALRH register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4474 | #define RTC_ALRH_RTC_ALR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4475 | #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4476 | #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4477 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4478 | /******************* Bit definition for RTC_ALRL register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4479 | #define RTC_ALRL_RTC_ALR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4480 | #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4481 | #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4482 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4483 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4484 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4485 | /* Independent WATCHDOG (IWDG) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4486 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4487 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4488 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4489 | /******************* Bit definition for IWDG_KR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4490 | #define IWDG_KR_KEY_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4491 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4492 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4493 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4494 | /******************* Bit definition for IWDG_PR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4495 | #define IWDG_PR_PR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4496 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4497 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4498 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4499 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4500 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4501 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4502 | /******************* Bit definition for IWDG_RLR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4503 | #define IWDG_RLR_RL_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4504 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4505 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4506 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4507 | /******************* Bit definition for IWDG_SR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4508 | #define IWDG_SR_PVU_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4509 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4510 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4511 | #define IWDG_SR_RVU_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4512 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4513 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4514 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4515 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4516 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4517 | /* Window WATCHDOG (WWDG) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4518 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4519 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4520 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4521 | /******************* Bit definition for WWDG_CR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4522 | #define WWDG_CR_T_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4523 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4524 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4525 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4526 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4527 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4528 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4529 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4530 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4531 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4532 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4533 | /* Legacy defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4534 | #define WWDG_CR_T0 WWDG_CR_T_0 |
| Pawel Zarembski |
0:01f31e923fe2 | 4535 | #define WWDG_CR_T1 WWDG_CR_T_1 |
| Pawel Zarembski |
0:01f31e923fe2 | 4536 | #define WWDG_CR_T2 WWDG_CR_T_2 |
| Pawel Zarembski |
0:01f31e923fe2 | 4537 | #define WWDG_CR_T3 WWDG_CR_T_3 |
| Pawel Zarembski |
0:01f31e923fe2 | 4538 | #define WWDG_CR_T4 WWDG_CR_T_4 |
| Pawel Zarembski |
0:01f31e923fe2 | 4539 | #define WWDG_CR_T5 WWDG_CR_T_5 |
| Pawel Zarembski |
0:01f31e923fe2 | 4540 | #define WWDG_CR_T6 WWDG_CR_T_6 |
| Pawel Zarembski |
0:01f31e923fe2 | 4541 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4542 | #define WWDG_CR_WDGA_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4543 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4544 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4545 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4546 | /******************* Bit definition for WWDG_CFR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4547 | #define WWDG_CFR_W_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4548 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4549 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4550 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4551 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4552 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4553 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4554 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4555 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4556 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4557 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4558 | /* Legacy defines */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4559 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
| Pawel Zarembski |
0:01f31e923fe2 | 4560 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
| Pawel Zarembski |
0:01f31e923fe2 | 4561 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
| Pawel Zarembski |
0:01f31e923fe2 | 4562 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
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0:01f31e923fe2 | 4563 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
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0:01f31e923fe2 | 4564 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
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0:01f31e923fe2 | 4565 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
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0:01f31e923fe2 | 4566 | |
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0:01f31e923fe2 | 4567 | #define WWDG_CFR_WDGTB_Pos (7U) |
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0:01f31e923fe2 | 4568 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
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0:01f31e923fe2 | 4569 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ |
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0:01f31e923fe2 | 4570 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 4571 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 4572 | |
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0:01f31e923fe2 | 4573 | /* Legacy defines */ |
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0:01f31e923fe2 | 4574 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
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0:01f31e923fe2 | 4575 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
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0:01f31e923fe2 | 4576 | |
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0:01f31e923fe2 | 4577 | #define WWDG_CFR_EWI_Pos (9U) |
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0:01f31e923fe2 | 4578 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 4579 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ |
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0:01f31e923fe2 | 4580 | |
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0:01f31e923fe2 | 4581 | /******************* Bit definition for WWDG_SR register ********************/ |
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0:01f31e923fe2 | 4582 | #define WWDG_SR_EWIF_Pos (0U) |
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0:01f31e923fe2 | 4583 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 4584 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ |
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0:01f31e923fe2 | 4585 | |
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0:01f31e923fe2 | 4586 | |
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0:01f31e923fe2 | 4587 | /******************************************************************************/ |
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0:01f31e923fe2 | 4588 | /* */ |
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0:01f31e923fe2 | 4589 | /* SD host Interface */ |
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0:01f31e923fe2 | 4590 | /* */ |
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0:01f31e923fe2 | 4591 | /******************************************************************************/ |
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0:01f31e923fe2 | 4592 | |
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0:01f31e923fe2 | 4593 | /****************** Bit definition for SDIO_POWER register ******************/ |
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0:01f31e923fe2 | 4594 | #define SDIO_POWER_PWRCTRL_Pos (0U) |
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0:01f31e923fe2 | 4595 | #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ |
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0:01f31e923fe2 | 4596 | #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ |
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0:01f31e923fe2 | 4597 | #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ |
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0:01f31e923fe2 | 4598 | #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ |
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0:01f31e923fe2 | 4599 | |
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0:01f31e923fe2 | 4600 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
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0:01f31e923fe2 | 4601 | #define SDIO_CLKCR_CLKDIV_Pos (0U) |
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0:01f31e923fe2 | 4602 | #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ |
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0:01f31e923fe2 | 4603 | #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ |
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0:01f31e923fe2 | 4604 | #define SDIO_CLKCR_CLKEN_Pos (8U) |
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0:01f31e923fe2 | 4605 | #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 4606 | #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ |
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0:01f31e923fe2 | 4607 | #define SDIO_CLKCR_PWRSAV_Pos (9U) |
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0:01f31e923fe2 | 4608 | #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 4609 | #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ |
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0:01f31e923fe2 | 4610 | #define SDIO_CLKCR_BYPASS_Pos (10U) |
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0:01f31e923fe2 | 4611 | #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 4612 | #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ |
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0:01f31e923fe2 | 4613 | |
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0:01f31e923fe2 | 4614 | #define SDIO_CLKCR_WIDBUS_Pos (11U) |
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0:01f31e923fe2 | 4615 | #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ |
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0:01f31e923fe2 | 4616 | #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
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0:01f31e923fe2 | 4617 | #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ |
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0:01f31e923fe2 | 4618 | #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ |
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0:01f31e923fe2 | 4619 | |
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0:01f31e923fe2 | 4620 | #define SDIO_CLKCR_NEGEDGE_Pos (13U) |
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0:01f31e923fe2 | 4621 | #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 4622 | #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ |
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0:01f31e923fe2 | 4623 | #define SDIO_CLKCR_HWFC_EN_Pos (14U) |
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0:01f31e923fe2 | 4624 | #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 4625 | #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ |
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0:01f31e923fe2 | 4626 | |
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0:01f31e923fe2 | 4627 | /******************* Bit definition for SDIO_ARG register *******************/ |
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0:01f31e923fe2 | 4628 | #define SDIO_ARG_CMDARG_Pos (0U) |
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0:01f31e923fe2 | 4629 | #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4630 | #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ |
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0:01f31e923fe2 | 4631 | |
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0:01f31e923fe2 | 4632 | /******************* Bit definition for SDIO_CMD register *******************/ |
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0:01f31e923fe2 | 4633 | #define SDIO_CMD_CMDINDEX_Pos (0U) |
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0:01f31e923fe2 | 4634 | #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ |
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0:01f31e923fe2 | 4635 | #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ |
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0:01f31e923fe2 | 4636 | |
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0:01f31e923fe2 | 4637 | #define SDIO_CMD_WAITRESP_Pos (6U) |
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0:01f31e923fe2 | 4638 | #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ |
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0:01f31e923fe2 | 4639 | #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ |
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0:01f31e923fe2 | 4640 | #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ |
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0:01f31e923fe2 | 4641 | #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ |
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0:01f31e923fe2 | 4642 | |
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0:01f31e923fe2 | 4643 | #define SDIO_CMD_WAITINT_Pos (8U) |
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0:01f31e923fe2 | 4644 | #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 4645 | #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ |
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0:01f31e923fe2 | 4646 | #define SDIO_CMD_WAITPEND_Pos (9U) |
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0:01f31e923fe2 | 4647 | #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 4648 | #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
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0:01f31e923fe2 | 4649 | #define SDIO_CMD_CPSMEN_Pos (10U) |
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0:01f31e923fe2 | 4650 | #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 4651 | #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ |
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0:01f31e923fe2 | 4652 | #define SDIO_CMD_SDIOSUSPEND_Pos (11U) |
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0:01f31e923fe2 | 4653 | #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 4654 | #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ |
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0:01f31e923fe2 | 4655 | #define SDIO_CMD_ENCMDCOMPL_Pos (12U) |
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0:01f31e923fe2 | 4656 | #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 4657 | #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ |
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0:01f31e923fe2 | 4658 | #define SDIO_CMD_NIEN_Pos (13U) |
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0:01f31e923fe2 | 4659 | #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 4660 | #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ |
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0:01f31e923fe2 | 4661 | #define SDIO_CMD_CEATACMD_Pos (14U) |
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0:01f31e923fe2 | 4662 | #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 4663 | #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ |
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0:01f31e923fe2 | 4664 | |
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0:01f31e923fe2 | 4665 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
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0:01f31e923fe2 | 4666 | #define SDIO_RESPCMD_RESPCMD_Pos (0U) |
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0:01f31e923fe2 | 4667 | #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ |
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0:01f31e923fe2 | 4668 | #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ |
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0:01f31e923fe2 | 4669 | |
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0:01f31e923fe2 | 4670 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
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0:01f31e923fe2 | 4671 | #define SDIO_RESP0_CARDSTATUS0_Pos (0U) |
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0:01f31e923fe2 | 4672 | #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4673 | #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ |
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0:01f31e923fe2 | 4674 | |
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0:01f31e923fe2 | 4675 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
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0:01f31e923fe2 | 4676 | #define SDIO_RESP1_CARDSTATUS1_Pos (0U) |
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0:01f31e923fe2 | 4677 | #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4678 | #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ |
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0:01f31e923fe2 | 4679 | |
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0:01f31e923fe2 | 4680 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
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0:01f31e923fe2 | 4681 | #define SDIO_RESP2_CARDSTATUS2_Pos (0U) |
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0:01f31e923fe2 | 4682 | #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4683 | #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ |
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0:01f31e923fe2 | 4684 | |
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0:01f31e923fe2 | 4685 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
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0:01f31e923fe2 | 4686 | #define SDIO_RESP3_CARDSTATUS3_Pos (0U) |
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0:01f31e923fe2 | 4687 | #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4688 | #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ |
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0:01f31e923fe2 | 4689 | |
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0:01f31e923fe2 | 4690 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
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0:01f31e923fe2 | 4691 | #define SDIO_RESP4_CARDSTATUS4_Pos (0U) |
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0:01f31e923fe2 | 4692 | #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4693 | #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ |
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0:01f31e923fe2 | 4694 | |
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0:01f31e923fe2 | 4695 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
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0:01f31e923fe2 | 4696 | #define SDIO_DTIMER_DATATIME_Pos (0U) |
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0:01f31e923fe2 | 4697 | #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 4698 | #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ |
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0:01f31e923fe2 | 4699 | |
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0:01f31e923fe2 | 4700 | /****************** Bit definition for SDIO_DLEN register *******************/ |
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0:01f31e923fe2 | 4701 | #define SDIO_DLEN_DATALENGTH_Pos (0U) |
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0:01f31e923fe2 | 4702 | #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ |
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0:01f31e923fe2 | 4703 | #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ |
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0:01f31e923fe2 | 4704 | |
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0:01f31e923fe2 | 4705 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
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0:01f31e923fe2 | 4706 | #define SDIO_DCTRL_DTEN_Pos (0U) |
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0:01f31e923fe2 | 4707 | #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 4708 | #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ |
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0:01f31e923fe2 | 4709 | #define SDIO_DCTRL_DTDIR_Pos (1U) |
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0:01f31e923fe2 | 4710 | #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 4711 | #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ |
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0:01f31e923fe2 | 4712 | #define SDIO_DCTRL_DTMODE_Pos (2U) |
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0:01f31e923fe2 | 4713 | #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 4714 | #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ |
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0:01f31e923fe2 | 4715 | #define SDIO_DCTRL_DMAEN_Pos (3U) |
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0:01f31e923fe2 | 4716 | #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 4717 | #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ |
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0:01f31e923fe2 | 4718 | |
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0:01f31e923fe2 | 4719 | #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4720 | #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4721 | #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4722 | #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4723 | #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4724 | #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4725 | #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4726 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4727 | #define SDIO_DCTRL_RWSTART_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4728 | #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4729 | #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4730 | #define SDIO_DCTRL_RWSTOP_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4731 | #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4732 | #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4733 | #define SDIO_DCTRL_RWMOD_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4734 | #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4735 | #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4736 | #define SDIO_DCTRL_SDIOEN_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4737 | #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4738 | #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4739 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4740 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4741 | #define SDIO_DCOUNT_DATACOUNT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4742 | #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4743 | #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4744 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4745 | /****************** Bit definition for SDIO_STA register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4746 | #define SDIO_STA_CCRCFAIL_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4747 | #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4748 | #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4749 | #define SDIO_STA_DCRCFAIL_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4750 | #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4751 | #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4752 | #define SDIO_STA_CTIMEOUT_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4753 | #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4754 | #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4755 | #define SDIO_STA_DTIMEOUT_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4756 | #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4757 | #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4758 | #define SDIO_STA_TXUNDERR_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4759 | #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4760 | #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4761 | #define SDIO_STA_RXOVERR_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4762 | #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4763 | #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4764 | #define SDIO_STA_CMDREND_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4765 | #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4766 | #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4767 | #define SDIO_STA_CMDSENT_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4768 | #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4769 | #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4770 | #define SDIO_STA_DATAEND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4771 | #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4772 | #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4773 | #define SDIO_STA_STBITERR_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4774 | #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4775 | #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4776 | #define SDIO_STA_DBCKEND_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4777 | #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4778 | #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4779 | #define SDIO_STA_CMDACT_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4780 | #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4781 | #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4782 | #define SDIO_STA_TXACT_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4783 | #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4784 | #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4785 | #define SDIO_STA_RXACT_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4786 | #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4787 | #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4788 | #define SDIO_STA_TXFIFOHE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4789 | #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4790 | #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4791 | #define SDIO_STA_RXFIFOHF_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4792 | #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4793 | #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4794 | #define SDIO_STA_TXFIFOF_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4795 | #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4796 | #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4797 | #define SDIO_STA_RXFIFOF_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4798 | #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4799 | #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4800 | #define SDIO_STA_TXFIFOE_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4801 | #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4802 | #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4803 | #define SDIO_STA_RXFIFOE_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4804 | #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4805 | #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4806 | #define SDIO_STA_TXDAVL_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4807 | #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4808 | #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4809 | #define SDIO_STA_RXDAVL_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4810 | #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4811 | #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4812 | #define SDIO_STA_SDIOIT_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4813 | #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4814 | #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4815 | #define SDIO_STA_CEATAEND_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4816 | #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4817 | #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4818 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4819 | /******************* Bit definition for SDIO_ICR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4820 | #define SDIO_ICR_CCRCFAILC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4821 | #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4822 | #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4823 | #define SDIO_ICR_DCRCFAILC_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4824 | #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4825 | #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4826 | #define SDIO_ICR_CTIMEOUTC_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4827 | #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4828 | #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4829 | #define SDIO_ICR_DTIMEOUTC_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4830 | #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4831 | #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4832 | #define SDIO_ICR_TXUNDERRC_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4833 | #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4834 | #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4835 | #define SDIO_ICR_RXOVERRC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4836 | #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4837 | #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4838 | #define SDIO_ICR_CMDRENDC_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4839 | #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4840 | #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4841 | #define SDIO_ICR_CMDSENTC_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4842 | #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4843 | #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4844 | #define SDIO_ICR_DATAENDC_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4845 | #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4846 | #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4847 | #define SDIO_ICR_STBITERRC_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4848 | #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4849 | #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4850 | #define SDIO_ICR_DBCKENDC_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4851 | #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4852 | #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4853 | #define SDIO_ICR_SDIOITC_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4854 | #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4855 | #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4856 | #define SDIO_ICR_CEATAENDC_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4857 | #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4858 | #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4859 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4860 | /****************** Bit definition for SDIO_MASK register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4861 | #define SDIO_MASK_CCRCFAILIE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4862 | #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4863 | #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4864 | #define SDIO_MASK_DCRCFAILIE_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4865 | #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4866 | #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4867 | #define SDIO_MASK_CTIMEOUTIE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4868 | #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4869 | #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4870 | #define SDIO_MASK_DTIMEOUTIE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4871 | #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4872 | #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4873 | #define SDIO_MASK_TXUNDERRIE_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4874 | #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4875 | #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4876 | #define SDIO_MASK_RXOVERRIE_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4877 | #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4878 | #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4879 | #define SDIO_MASK_CMDRENDIE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4880 | #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4881 | #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4882 | #define SDIO_MASK_CMDSENTIE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4883 | #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4884 | #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4885 | #define SDIO_MASK_DATAENDIE_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4886 | #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4887 | #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ |
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0:01f31e923fe2 | 4888 | #define SDIO_MASK_STBITERRIE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4889 | #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4890 | #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ |
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0:01f31e923fe2 | 4891 | #define SDIO_MASK_DBCKENDIE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4892 | #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4893 | #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ |
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0:01f31e923fe2 | 4894 | #define SDIO_MASK_CMDACTIE_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4895 | #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4896 | #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4897 | #define SDIO_MASK_TXACTIE_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4898 | #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4899 | #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4900 | #define SDIO_MASK_RXACTIE_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4901 | #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4902 | #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4903 | #define SDIO_MASK_TXFIFOHEIE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4904 | #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4905 | #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4906 | #define SDIO_MASK_RXFIFOHFIE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4907 | #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4908 | #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4909 | #define SDIO_MASK_TXFIFOFIE_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4910 | #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4911 | #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4912 | #define SDIO_MASK_RXFIFOFIE_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4913 | #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4914 | #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4915 | #define SDIO_MASK_TXFIFOEIE_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4916 | #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4917 | #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4918 | #define SDIO_MASK_RXFIFOEIE_Pos (19U) |
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0:01f31e923fe2 | 4919 | #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4920 | #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4921 | #define SDIO_MASK_TXDAVLIE_Pos (20U) |
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0:01f31e923fe2 | 4922 | #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4923 | #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4924 | #define SDIO_MASK_RXDAVLIE_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4925 | #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4926 | #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4927 | #define SDIO_MASK_SDIOITIE_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4928 | #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4929 | #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4930 | #define SDIO_MASK_CEATAENDIE_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4931 | #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4932 | #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4933 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4934 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
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0:01f31e923fe2 | 4935 | #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4936 | #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4937 | #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4938 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4939 | /****************** Bit definition for SDIO_FIFO register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 4940 | #define SDIO_FIFO_FIFODATA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4941 | #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4942 | #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ |
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0:01f31e923fe2 | 4943 | |
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0:01f31e923fe2 | 4944 | /******************************************************************************/ |
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0:01f31e923fe2 | 4945 | /* */ |
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0:01f31e923fe2 | 4946 | /* USB Device FS */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4947 | /* */ |
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0:01f31e923fe2 | 4948 | /******************************************************************************/ |
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0:01f31e923fe2 | 4949 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4950 | /*!< Endpoint-specific registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4951 | #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ |
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0:01f31e923fe2 | 4952 | #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ |
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0:01f31e923fe2 | 4953 | #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ |
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0:01f31e923fe2 | 4954 | #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ |
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0:01f31e923fe2 | 4955 | #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ |
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0:01f31e923fe2 | 4956 | #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4957 | #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ |
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0:01f31e923fe2 | 4958 | #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ |
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0:01f31e923fe2 | 4959 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4960 | /* bit positions */ |
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0:01f31e923fe2 | 4961 | #define USB_EP_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4962 | #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4963 | #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4964 | #define USB_EP_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4965 | #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4966 | #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4967 | #define USB_EPRX_STAT_Pos (12U) |
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0:01f31e923fe2 | 4968 | #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4969 | #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4970 | #define USB_EP_SETUP_Pos (11U) |
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0:01f31e923fe2 | 4971 | #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4972 | #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ |
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0:01f31e923fe2 | 4973 | #define USB_EP_T_FIELD_Pos (9U) |
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0:01f31e923fe2 | 4974 | #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4975 | #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ |
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0:01f31e923fe2 | 4976 | #define USB_EP_KIND_Pos (8U) |
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0:01f31e923fe2 | 4977 | #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4978 | #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4979 | #define USB_EP_CTR_TX_Pos (7U) |
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0:01f31e923fe2 | 4980 | #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4981 | #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4982 | #define USB_EP_DTOG_TX_Pos (6U) |
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0:01f31e923fe2 | 4983 | #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4984 | #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4985 | #define USB_EPTX_STAT_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 4986 | #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4987 | #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4988 | #define USB_EPADDR_FIELD_Pos (0U) |
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0:01f31e923fe2 | 4989 | #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ |
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0:01f31e923fe2 | 4990 | #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ |
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0:01f31e923fe2 | 4991 | |
| Pawel Zarembski |
0:01f31e923fe2 | 4992 | /* EndPoint REGister MASK (no toggle fields) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4993 | #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
| Pawel Zarembski |
0:01f31e923fe2 | 4994 | /*!< EP_TYPE[1:0] EndPoint TYPE */ |
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0:01f31e923fe2 | 4995 | #define USB_EP_TYPE_MASK_Pos (9U) |
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0:01f31e923fe2 | 4996 | #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4997 | #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ |
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0:01f31e923fe2 | 4998 | #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */ |
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0:01f31e923fe2 | 4999 | #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */ |
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0:01f31e923fe2 | 5000 | #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */ |
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0:01f31e923fe2 | 5001 | #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */ |
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0:01f31e923fe2 | 5002 | #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
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0:01f31e923fe2 | 5003 | |
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0:01f31e923fe2 | 5004 | #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5005 | /*!< STAT_TX[1:0] STATus for TX transfer */ |
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0:01f31e923fe2 | 5006 | #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */ |
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0:01f31e923fe2 | 5007 | #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5008 | #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5009 | #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */ |
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0:01f31e923fe2 | 5010 | #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5011 | #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */ |
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0:01f31e923fe2 | 5012 | #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
| Pawel Zarembski |
0:01f31e923fe2 | 5013 | /*!< STAT_RX[1:0] STATus for RX transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5014 | #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5015 | #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5016 | #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5017 | #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5018 | #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5019 | #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5020 | #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
| Pawel Zarembski |
0:01f31e923fe2 | 5021 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5022 | /******************* Bit definition for USB_EP0R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5023 | #define USB_EP0R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5024 | #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5025 | #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5026 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5027 | #define USB_EP0R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5028 | #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5029 | #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5030 | #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5031 | #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5032 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5033 | #define USB_EP0R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5034 | #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5035 | #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5036 | #define USB_EP0R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5037 | #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5038 | #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5039 | #define USB_EP0R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5040 | #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5041 | #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5042 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5043 | #define USB_EP0R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5044 | #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5045 | #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5046 | #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5047 | #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5048 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5049 | #define USB_EP0R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5050 | #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5051 | #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5052 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5053 | #define USB_EP0R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5054 | #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5055 | #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5056 | #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5057 | #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5058 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5059 | #define USB_EP0R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5060 | #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5061 | #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5062 | #define USB_EP0R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5063 | #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5064 | #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5065 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5066 | /******************* Bit definition for USB_EP1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5067 | #define USB_EP1R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5068 | #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5069 | #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5070 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5071 | #define USB_EP1R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5072 | #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5073 | #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5074 | #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5075 | #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5076 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5077 | #define USB_EP1R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5078 | #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5079 | #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5080 | #define USB_EP1R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5081 | #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5082 | #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5083 | #define USB_EP1R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5084 | #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5085 | #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5086 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5087 | #define USB_EP1R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5088 | #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5089 | #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5090 | #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5091 | #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5092 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5093 | #define USB_EP1R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5094 | #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5095 | #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5096 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5097 | #define USB_EP1R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5098 | #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5099 | #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5100 | #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5101 | #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5102 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5103 | #define USB_EP1R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5104 | #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5105 | #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5106 | #define USB_EP1R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5107 | #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5108 | #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5109 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5110 | /******************* Bit definition for USB_EP2R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5111 | #define USB_EP2R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5112 | #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5113 | #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5114 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5115 | #define USB_EP2R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5116 | #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5117 | #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5118 | #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5119 | #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5120 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5121 | #define USB_EP2R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5122 | #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5123 | #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5124 | #define USB_EP2R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5125 | #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5126 | #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5127 | #define USB_EP2R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5128 | #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5129 | #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5130 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5131 | #define USB_EP2R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5132 | #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5133 | #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5134 | #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5135 | #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5136 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5137 | #define USB_EP2R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5138 | #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5139 | #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5140 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5141 | #define USB_EP2R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5142 | #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5143 | #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5144 | #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5145 | #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5146 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5147 | #define USB_EP2R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5148 | #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5149 | #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5150 | #define USB_EP2R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5151 | #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5152 | #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5153 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5154 | /******************* Bit definition for USB_EP3R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5155 | #define USB_EP3R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5156 | #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5157 | #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5158 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5159 | #define USB_EP3R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5160 | #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5161 | #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5162 | #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5163 | #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5164 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5165 | #define USB_EP3R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5166 | #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5167 | #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5168 | #define USB_EP3R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5169 | #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5170 | #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5171 | #define USB_EP3R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5172 | #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5173 | #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5174 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5175 | #define USB_EP3R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5176 | #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5177 | #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5178 | #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5179 | #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5180 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5181 | #define USB_EP3R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5182 | #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5183 | #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5184 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5185 | #define USB_EP3R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5186 | #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5187 | #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5188 | #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5189 | #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5190 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5191 | #define USB_EP3R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5192 | #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5193 | #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5194 | #define USB_EP3R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5195 | #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5196 | #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5197 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5198 | /******************* Bit definition for USB_EP4R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5199 | #define USB_EP4R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5200 | #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5201 | #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5202 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5203 | #define USB_EP4R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5204 | #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5205 | #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5206 | #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5207 | #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5208 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5209 | #define USB_EP4R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5210 | #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5211 | #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5212 | #define USB_EP4R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5213 | #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5214 | #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5215 | #define USB_EP4R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5216 | #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5217 | #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5218 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5219 | #define USB_EP4R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5220 | #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5221 | #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5222 | #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5223 | #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5224 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5225 | #define USB_EP4R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5226 | #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5227 | #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5228 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5229 | #define USB_EP4R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5230 | #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5231 | #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5232 | #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5233 | #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5234 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5235 | #define USB_EP4R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5236 | #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5237 | #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5238 | #define USB_EP4R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5239 | #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5240 | #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5241 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5242 | /******************* Bit definition for USB_EP5R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5243 | #define USB_EP5R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5244 | #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5245 | #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5246 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5247 | #define USB_EP5R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5248 | #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5249 | #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5250 | #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5251 | #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5252 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5253 | #define USB_EP5R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5254 | #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5255 | #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5256 | #define USB_EP5R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5257 | #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5258 | #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5259 | #define USB_EP5R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5260 | #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5261 | #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5262 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5263 | #define USB_EP5R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5264 | #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5265 | #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5266 | #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5267 | #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5268 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5269 | #define USB_EP5R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5270 | #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5271 | #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5272 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5273 | #define USB_EP5R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5274 | #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5275 | #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5276 | #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5277 | #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5278 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5279 | #define USB_EP5R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5280 | #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5281 | #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5282 | #define USB_EP5R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5283 | #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5284 | #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5285 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5286 | /******************* Bit definition for USB_EP6R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5287 | #define USB_EP6R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5288 | #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5289 | #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5290 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5291 | #define USB_EP6R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5292 | #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5293 | #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5294 | #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5295 | #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5296 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5297 | #define USB_EP6R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5298 | #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5299 | #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5300 | #define USB_EP6R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5301 | #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5302 | #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5303 | #define USB_EP6R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5304 | #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5305 | #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5306 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5307 | #define USB_EP6R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5308 | #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5309 | #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5310 | #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5311 | #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5312 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5313 | #define USB_EP6R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5314 | #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5315 | #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5316 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5317 | #define USB_EP6R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5318 | #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5319 | #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5320 | #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5321 | #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5322 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5323 | #define USB_EP6R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5324 | #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5325 | #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5326 | #define USB_EP6R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5327 | #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5328 | #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5329 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5330 | /******************* Bit definition for USB_EP7R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5331 | #define USB_EP7R_EA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5332 | #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5333 | #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5334 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5335 | #define USB_EP7R_STAT_TX_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5336 | #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5337 | #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5338 | #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5339 | #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5340 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5341 | #define USB_EP7R_DTOG_TX_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5342 | #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5343 | #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5344 | #define USB_EP7R_CTR_TX_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5345 | #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5346 | #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5347 | #define USB_EP7R_EP_KIND_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5348 | #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5349 | #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5350 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5351 | #define USB_EP7R_EP_TYPE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5352 | #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5353 | #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5354 | #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5355 | #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5356 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5357 | #define USB_EP7R_SETUP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5358 | #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5359 | #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5360 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5361 | #define USB_EP7R_STAT_RX_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5362 | #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5363 | #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5364 | #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5365 | #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5366 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5367 | #define USB_EP7R_DTOG_RX_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5368 | #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5369 | #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5370 | #define USB_EP7R_CTR_RX_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5371 | #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5372 | #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5373 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5374 | /*!< Common registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5375 | /******************* Bit definition for USB_CNTR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5376 | #define USB_CNTR_FRES_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5377 | #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5378 | #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5379 | #define USB_CNTR_PDWN_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5380 | #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5381 | #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5382 | #define USB_CNTR_LP_MODE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5383 | #define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5384 | #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5385 | #define USB_CNTR_FSUSP_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5386 | #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5387 | #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5388 | #define USB_CNTR_RESUME_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5389 | #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5390 | #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5391 | #define USB_CNTR_ESOFM_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5392 | #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5393 | #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5394 | #define USB_CNTR_SOFM_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5395 | #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5396 | #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5397 | #define USB_CNTR_RESETM_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5398 | #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5399 | #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5400 | #define USB_CNTR_SUSPM_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5401 | #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5402 | #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5403 | #define USB_CNTR_WKUPM_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5404 | #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5405 | #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5406 | #define USB_CNTR_ERRM_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5407 | #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5408 | #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5409 | #define USB_CNTR_PMAOVRM_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5410 | #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5411 | #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5412 | #define USB_CNTR_CTRM_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5413 | #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5414 | #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5415 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5416 | /******************* Bit definition for USB_ISTR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5417 | #define USB_ISTR_EP_ID_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5418 | #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5419 | #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5420 | #define USB_ISTR_DIR_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5421 | #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5422 | #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5423 | #define USB_ISTR_ESOF_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5424 | #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5425 | #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5426 | #define USB_ISTR_SOF_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5427 | #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5428 | #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5429 | #define USB_ISTR_RESET_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5430 | #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5431 | #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5432 | #define USB_ISTR_SUSP_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5433 | #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5434 | #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5435 | #define USB_ISTR_WKUP_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5436 | #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5437 | #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5438 | #define USB_ISTR_ERR_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5439 | #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5440 | #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5441 | #define USB_ISTR_PMAOVR_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5442 | #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5443 | #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5444 | #define USB_ISTR_CTR_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5445 | #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5446 | #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5447 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5448 | /******************* Bit definition for USB_FNR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5449 | #define USB_FNR_FN_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5450 | #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5451 | #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5452 | #define USB_FNR_LSOF_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5453 | #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5454 | #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5455 | #define USB_FNR_LCK_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5456 | #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5457 | #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5458 | #define USB_FNR_RXDM_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5459 | #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5460 | #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5461 | #define USB_FNR_RXDP_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5462 | #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5463 | #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5464 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5465 | /****************** Bit definition for USB_DADDR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5466 | #define USB_DADDR_ADD_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5467 | #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5468 | #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5469 | #define USB_DADDR_ADD0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5470 | #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5471 | #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5472 | #define USB_DADDR_ADD1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5473 | #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5474 | #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5475 | #define USB_DADDR_ADD2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5476 | #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5477 | #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5478 | #define USB_DADDR_ADD3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5479 | #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5480 | #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5481 | #define USB_DADDR_ADD4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5482 | #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5483 | #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5484 | #define USB_DADDR_ADD5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5485 | #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5486 | #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5487 | #define USB_DADDR_ADD6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5488 | #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5489 | #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5490 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5491 | #define USB_DADDR_EF_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5492 | #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5493 | #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5494 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5495 | /****************** Bit definition for USB_BTABLE register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5496 | #define USB_BTABLE_BTABLE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5497 | #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5498 | #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5499 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5500 | /*!< Buffer descriptor table */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5501 | /***************** Bit definition for USB_ADDR0_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5502 | #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5503 | #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5504 | #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5505 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5506 | /***************** Bit definition for USB_ADDR1_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5507 | #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5508 | #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5509 | #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5510 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5511 | /***************** Bit definition for USB_ADDR2_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5512 | #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5513 | #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5514 | #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5515 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5516 | /***************** Bit definition for USB_ADDR3_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5517 | #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5518 | #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5519 | #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5520 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5521 | /***************** Bit definition for USB_ADDR4_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5522 | #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5523 | #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5524 | #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5525 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5526 | /***************** Bit definition for USB_ADDR5_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5527 | #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5528 | #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5529 | #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5530 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5531 | /***************** Bit definition for USB_ADDR6_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5532 | #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5533 | #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5534 | #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5535 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5536 | /***************** Bit definition for USB_ADDR7_TX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5537 | #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5538 | #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5539 | #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5540 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5541 | /*----------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5542 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5543 | /***************** Bit definition for USB_COUNT0_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5544 | #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5545 | #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5546 | #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5547 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5548 | /***************** Bit definition for USB_COUNT1_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5549 | #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5550 | #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5551 | #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5552 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5553 | /***************** Bit definition for USB_COUNT2_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5554 | #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5555 | #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5556 | #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5557 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5558 | /***************** Bit definition for USB_COUNT3_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5559 | #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5560 | #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5561 | #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5562 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5563 | /***************** Bit definition for USB_COUNT4_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5564 | #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5565 | #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5566 | #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5567 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5568 | /***************** Bit definition for USB_COUNT5_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5569 | #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5570 | #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5571 | #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5572 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5573 | /***************** Bit definition for USB_COUNT6_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5574 | #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5575 | #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5576 | #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5577 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5578 | /***************** Bit definition for USB_COUNT7_TX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5579 | #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5580 | #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5581 | #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5582 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5583 | /*----------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5584 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5585 | /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5586 | #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5587 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5588 | /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5589 | #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5590 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5591 | /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5592 | #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5593 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5594 | /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5595 | #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5596 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5597 | /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5598 | #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5599 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5600 | /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5601 | #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5602 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5603 | /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5604 | #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5605 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5606 | /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5607 | #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5608 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5609 | /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5610 | #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5611 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5612 | /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5613 | #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5614 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5615 | /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5616 | #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5617 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5618 | /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5619 | #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5620 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5621 | /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5622 | #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5623 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5624 | /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5625 | #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5626 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5627 | /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5628 | #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5629 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5630 | /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5631 | #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5632 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5633 | /*----------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5634 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5635 | /***************** Bit definition for USB_ADDR0_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5636 | #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5637 | #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5638 | #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5639 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5640 | /***************** Bit definition for USB_ADDR1_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5641 | #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5642 | #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5643 | #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5644 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5645 | /***************** Bit definition for USB_ADDR2_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5646 | #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5647 | #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5648 | #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5649 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5650 | /***************** Bit definition for USB_ADDR3_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5651 | #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5652 | #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5653 | #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5654 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5655 | /***************** Bit definition for USB_ADDR4_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5656 | #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5657 | #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5658 | #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5659 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5660 | /***************** Bit definition for USB_ADDR5_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5661 | #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5662 | #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5663 | #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5664 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5665 | /***************** Bit definition for USB_ADDR6_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5666 | #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5667 | #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5668 | #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5669 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5670 | /***************** Bit definition for USB_ADDR7_RX register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5671 | #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5672 | #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5673 | #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5674 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5675 | /*----------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5676 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5677 | /***************** Bit definition for USB_COUNT0_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5678 | #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5679 | #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5680 | #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5681 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5682 | #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5683 | #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5684 | #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5685 | #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5686 | #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5687 | #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5688 | #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5689 | #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5690 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5691 | #define USB_COUNT0_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5692 | #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5693 | #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5694 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5695 | /***************** Bit definition for USB_COUNT1_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5696 | #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5697 | #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5698 | #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5699 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5700 | #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5701 | #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5702 | #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5703 | #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5704 | #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5705 | #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5706 | #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5707 | #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5708 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5709 | #define USB_COUNT1_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5710 | #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5711 | #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5712 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5713 | /***************** Bit definition for USB_COUNT2_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5714 | #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5715 | #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5716 | #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5717 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5718 | #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5719 | #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5720 | #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5721 | #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5722 | #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5723 | #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5724 | #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5725 | #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5726 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5727 | #define USB_COUNT2_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5728 | #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5729 | #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5730 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5731 | /***************** Bit definition for USB_COUNT3_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5732 | #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5733 | #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5734 | #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5735 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5736 | #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5737 | #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5738 | #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5739 | #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5740 | #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5741 | #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5742 | #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5743 | #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5744 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5745 | #define USB_COUNT3_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5746 | #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5747 | #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5748 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5749 | /***************** Bit definition for USB_COUNT4_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5750 | #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5751 | #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5752 | #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5753 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5754 | #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5755 | #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5756 | #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5757 | #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5758 | #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5759 | #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5760 | #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5761 | #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5762 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5763 | #define USB_COUNT4_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5764 | #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5765 | #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5766 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5767 | /***************** Bit definition for USB_COUNT5_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5768 | #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5769 | #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5770 | #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5771 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5772 | #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5773 | #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5774 | #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5775 | #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5776 | #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5777 | #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5778 | #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5779 | #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5780 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5781 | #define USB_COUNT5_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5782 | #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5783 | #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5784 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5785 | /***************** Bit definition for USB_COUNT6_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5786 | #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5787 | #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5788 | #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5789 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5790 | #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5791 | #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5792 | #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5793 | #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5794 | #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5795 | #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5796 | #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5797 | #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5798 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5799 | #define USB_COUNT6_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5800 | #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5801 | #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5802 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5803 | /***************** Bit definition for USB_COUNT7_RX register ****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5804 | #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5805 | #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5806 | #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5807 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5808 | #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5809 | #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5810 | #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5811 | #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5812 | #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5813 | #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5814 | #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5815 | #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5816 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5817 | #define USB_COUNT7_RX_BLSIZE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 5818 | #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5819 | #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5820 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5821 | /*----------------------------------------------------------------------------*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5822 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5823 | /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5824 | #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5825 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5826 | #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5827 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5828 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5829 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5830 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5831 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5832 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5833 | #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5834 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5835 | /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5836 | #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5837 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5838 | #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5839 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5840 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5841 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5842 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5843 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5844 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5845 | #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5846 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5847 | /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5848 | #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5849 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5850 | #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5851 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5852 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5853 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5854 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5855 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5856 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5857 | #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5858 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5859 | /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5860 | #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5861 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5862 | #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5863 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5864 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5865 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5866 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5867 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5868 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5869 | #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5870 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5871 | /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5872 | #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5873 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5874 | #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5875 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5876 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5877 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5878 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5879 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5880 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5881 | #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5882 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5883 | /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5884 | #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5885 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5886 | #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5887 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5888 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5889 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5890 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5891 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5892 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5893 | #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5894 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5895 | /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5896 | #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5897 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5898 | #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5899 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5900 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5901 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5902 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5903 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5904 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5905 | #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5906 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5907 | /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5908 | #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5909 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5910 | #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5911 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5912 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5913 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5914 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5915 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5916 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5917 | #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5918 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5919 | /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 5920 | #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5921 | |
| Pawel Zarembski |
0:01f31e923fe2 | 5922 | #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5923 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5924 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5925 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5926 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5927 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 5928 | |
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0:01f31e923fe2 | 5929 | #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
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0:01f31e923fe2 | 5930 | |
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0:01f31e923fe2 | 5931 | /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
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0:01f31e923fe2 | 5932 | #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
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0:01f31e923fe2 | 5933 | |
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0:01f31e923fe2 | 5934 | #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
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0:01f31e923fe2 | 5935 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
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0:01f31e923fe2 | 5936 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5937 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5938 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5939 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 5940 | |
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0:01f31e923fe2 | 5941 | #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
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0:01f31e923fe2 | 5942 | |
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0:01f31e923fe2 | 5943 | /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
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0:01f31e923fe2 | 5944 | #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
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0:01f31e923fe2 | 5945 | |
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0:01f31e923fe2 | 5946 | #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
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0:01f31e923fe2 | 5947 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
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0:01f31e923fe2 | 5948 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5949 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5950 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5951 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 5952 | |
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0:01f31e923fe2 | 5953 | #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
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0:01f31e923fe2 | 5954 | |
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0:01f31e923fe2 | 5955 | /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
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0:01f31e923fe2 | 5956 | #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
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0:01f31e923fe2 | 5957 | |
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0:01f31e923fe2 | 5958 | #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
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0:01f31e923fe2 | 5959 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
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0:01f31e923fe2 | 5960 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5961 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5962 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5963 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 5964 | |
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0:01f31e923fe2 | 5965 | #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
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0:01f31e923fe2 | 5966 | |
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0:01f31e923fe2 | 5967 | /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
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0:01f31e923fe2 | 5968 | #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
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0:01f31e923fe2 | 5969 | |
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0:01f31e923fe2 | 5970 | #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
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0:01f31e923fe2 | 5971 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
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0:01f31e923fe2 | 5972 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5973 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5974 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5975 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 5976 | |
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0:01f31e923fe2 | 5977 | #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
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0:01f31e923fe2 | 5978 | |
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0:01f31e923fe2 | 5979 | /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
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0:01f31e923fe2 | 5980 | #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
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0:01f31e923fe2 | 5981 | |
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0:01f31e923fe2 | 5982 | #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
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0:01f31e923fe2 | 5983 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
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0:01f31e923fe2 | 5984 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5985 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5986 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5987 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 5988 | |
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0:01f31e923fe2 | 5989 | #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
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0:01f31e923fe2 | 5990 | |
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0:01f31e923fe2 | 5991 | /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
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0:01f31e923fe2 | 5992 | #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
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0:01f31e923fe2 | 5993 | |
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0:01f31e923fe2 | 5994 | #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
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0:01f31e923fe2 | 5995 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
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0:01f31e923fe2 | 5996 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
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0:01f31e923fe2 | 5997 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 5998 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 5999 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 6000 | |
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0:01f31e923fe2 | 6001 | #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
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0:01f31e923fe2 | 6002 | |
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0:01f31e923fe2 | 6003 | /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
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0:01f31e923fe2 | 6004 | #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
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0:01f31e923fe2 | 6005 | |
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0:01f31e923fe2 | 6006 | #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
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0:01f31e923fe2 | 6007 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
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0:01f31e923fe2 | 6008 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
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0:01f31e923fe2 | 6009 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
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0:01f31e923fe2 | 6010 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
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0:01f31e923fe2 | 6011 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
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0:01f31e923fe2 | 6012 | |
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0:01f31e923fe2 | 6013 | #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
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0:01f31e923fe2 | 6014 | |
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0:01f31e923fe2 | 6015 | /******************************************************************************/ |
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0:01f31e923fe2 | 6016 | /* */ |
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0:01f31e923fe2 | 6017 | /* Controller Area Network */ |
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0:01f31e923fe2 | 6018 | /* */ |
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0:01f31e923fe2 | 6019 | /******************************************************************************/ |
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0:01f31e923fe2 | 6020 | |
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0:01f31e923fe2 | 6021 | /*!< CAN control and status registers */ |
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0:01f31e923fe2 | 6022 | /******************* Bit definition for CAN_MCR register ********************/ |
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0:01f31e923fe2 | 6023 | #define CAN_MCR_INRQ_Pos (0U) |
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0:01f31e923fe2 | 6024 | #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 6025 | #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */ |
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0:01f31e923fe2 | 6026 | #define CAN_MCR_SLEEP_Pos (1U) |
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0:01f31e923fe2 | 6027 | #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 6028 | #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */ |
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0:01f31e923fe2 | 6029 | #define CAN_MCR_TXFP_Pos (2U) |
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0:01f31e923fe2 | 6030 | #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 6031 | #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */ |
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0:01f31e923fe2 | 6032 | #define CAN_MCR_RFLM_Pos (3U) |
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0:01f31e923fe2 | 6033 | #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 6034 | #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */ |
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0:01f31e923fe2 | 6035 | #define CAN_MCR_NART_Pos (4U) |
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0:01f31e923fe2 | 6036 | #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 6037 | #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */ |
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0:01f31e923fe2 | 6038 | #define CAN_MCR_AWUM_Pos (5U) |
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0:01f31e923fe2 | 6039 | #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 6040 | #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */ |
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0:01f31e923fe2 | 6041 | #define CAN_MCR_ABOM_Pos (6U) |
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0:01f31e923fe2 | 6042 | #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 6043 | #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */ |
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0:01f31e923fe2 | 6044 | #define CAN_MCR_TTCM_Pos (7U) |
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0:01f31e923fe2 | 6045 | #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 6046 | #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */ |
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0:01f31e923fe2 | 6047 | #define CAN_MCR_RESET_Pos (15U) |
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0:01f31e923fe2 | 6048 | #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 6049 | #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */ |
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0:01f31e923fe2 | 6050 | #define CAN_MCR_DBF_Pos (16U) |
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0:01f31e923fe2 | 6051 | #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 6052 | #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */ |
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0:01f31e923fe2 | 6053 | |
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0:01f31e923fe2 | 6054 | /******************* Bit definition for CAN_MSR register ********************/ |
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0:01f31e923fe2 | 6055 | #define CAN_MSR_INAK_Pos (0U) |
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0:01f31e923fe2 | 6056 | #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 6057 | #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */ |
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0:01f31e923fe2 | 6058 | #define CAN_MSR_SLAK_Pos (1U) |
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0:01f31e923fe2 | 6059 | #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 6060 | #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */ |
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0:01f31e923fe2 | 6061 | #define CAN_MSR_ERRI_Pos (2U) |
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0:01f31e923fe2 | 6062 | #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 6063 | #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */ |
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0:01f31e923fe2 | 6064 | #define CAN_MSR_WKUI_Pos (3U) |
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0:01f31e923fe2 | 6065 | #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 6066 | #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */ |
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0:01f31e923fe2 | 6067 | #define CAN_MSR_SLAKI_Pos (4U) |
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0:01f31e923fe2 | 6068 | #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 6069 | #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */ |
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0:01f31e923fe2 | 6070 | #define CAN_MSR_TXM_Pos (8U) |
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0:01f31e923fe2 | 6071 | #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 6072 | #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */ |
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0:01f31e923fe2 | 6073 | #define CAN_MSR_RXM_Pos (9U) |
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0:01f31e923fe2 | 6074 | #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 6075 | #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */ |
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0:01f31e923fe2 | 6076 | #define CAN_MSR_SAMP_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6077 | #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6078 | #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6079 | #define CAN_MSR_RX_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6080 | #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6081 | #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6082 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6083 | /******************* Bit definition for CAN_TSR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6084 | #define CAN_TSR_RQCP0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6085 | #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6086 | #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6087 | #define CAN_TSR_TXOK0_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6088 | #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6089 | #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6090 | #define CAN_TSR_ALST0_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6091 | #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6092 | #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6093 | #define CAN_TSR_TERR0_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6094 | #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6095 | #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6096 | #define CAN_TSR_ABRQ0_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6097 | #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6098 | #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6099 | #define CAN_TSR_RQCP1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6100 | #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6101 | #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6102 | #define CAN_TSR_TXOK1_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6103 | #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6104 | #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6105 | #define CAN_TSR_ALST1_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6106 | #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6107 | #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6108 | #define CAN_TSR_TERR1_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6109 | #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6110 | #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6111 | #define CAN_TSR_ABRQ1_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6112 | #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6113 | #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6114 | #define CAN_TSR_RQCP2_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6115 | #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6116 | #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6117 | #define CAN_TSR_TXOK2_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6118 | #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6119 | #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6120 | #define CAN_TSR_ALST2_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6121 | #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6122 | #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6123 | #define CAN_TSR_TERR2_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6124 | #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6125 | #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6126 | #define CAN_TSR_ABRQ2_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6127 | #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6128 | #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6129 | #define CAN_TSR_CODE_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6130 | #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6131 | #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6132 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6133 | #define CAN_TSR_TME_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6134 | #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6135 | #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6136 | #define CAN_TSR_TME0_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6137 | #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6138 | #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6139 | #define CAN_TSR_TME1_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6140 | #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6141 | #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6142 | #define CAN_TSR_TME2_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6143 | #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6144 | #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6145 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6146 | #define CAN_TSR_LOW_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6147 | #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6148 | #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6149 | #define CAN_TSR_LOW0_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6150 | #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6151 | #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6152 | #define CAN_TSR_LOW1_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6153 | #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6154 | #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6155 | #define CAN_TSR_LOW2_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6156 | #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6157 | #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6158 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6159 | /******************* Bit definition for CAN_RF0R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6160 | #define CAN_RF0R_FMP0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6161 | #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6162 | #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6163 | #define CAN_RF0R_FULL0_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6164 | #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6165 | #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6166 | #define CAN_RF0R_FOVR0_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6167 | #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6168 | #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6169 | #define CAN_RF0R_RFOM0_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6170 | #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6171 | #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6172 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6173 | /******************* Bit definition for CAN_RF1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6174 | #define CAN_RF1R_FMP1_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6175 | #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6176 | #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6177 | #define CAN_RF1R_FULL1_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6178 | #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6179 | #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6180 | #define CAN_RF1R_FOVR1_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6181 | #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6182 | #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6183 | #define CAN_RF1R_RFOM1_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6184 | #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6185 | #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6186 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6187 | /******************** Bit definition for CAN_IER register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6188 | #define CAN_IER_TMEIE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6189 | #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6190 | #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6191 | #define CAN_IER_FMPIE0_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6192 | #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6193 | #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6194 | #define CAN_IER_FFIE0_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6195 | #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6196 | #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6197 | #define CAN_IER_FOVIE0_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6198 | #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6199 | #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6200 | #define CAN_IER_FMPIE1_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6201 | #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6202 | #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6203 | #define CAN_IER_FFIE1_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6204 | #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6205 | #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6206 | #define CAN_IER_FOVIE1_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6207 | #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6208 | #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6209 | #define CAN_IER_EWGIE_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6210 | #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6211 | #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6212 | #define CAN_IER_EPVIE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6213 | #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6214 | #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6215 | #define CAN_IER_BOFIE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6216 | #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6217 | #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6218 | #define CAN_IER_LECIE_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6219 | #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6220 | #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6221 | #define CAN_IER_ERRIE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6222 | #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6223 | #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6224 | #define CAN_IER_WKUIE_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6225 | #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6226 | #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6227 | #define CAN_IER_SLKIE_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6228 | #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6229 | #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6230 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6231 | /******************** Bit definition for CAN_ESR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6232 | #define CAN_ESR_EWGF_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6233 | #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6234 | #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6235 | #define CAN_ESR_EPVF_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6236 | #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6237 | #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6238 | #define CAN_ESR_BOFF_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6239 | #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6240 | #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6241 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6242 | #define CAN_ESR_LEC_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6243 | #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6244 | #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6245 | #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6246 | #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6247 | #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6248 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6249 | #define CAN_ESR_TEC_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6250 | #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6251 | #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6252 | #define CAN_ESR_REC_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6253 | #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6254 | #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6255 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6256 | /******************* Bit definition for CAN_BTR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6257 | #define CAN_BTR_BRP_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6258 | #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6259 | #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6260 | #define CAN_BTR_TS1_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6261 | #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6262 | #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6263 | #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6264 | #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6265 | #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6266 | #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6267 | #define CAN_BTR_TS2_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6268 | #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6269 | #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6270 | #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6271 | #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6272 | #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6273 | #define CAN_BTR_SJW_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6274 | #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6275 | #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6276 | #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6277 | #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6278 | #define CAN_BTR_LBKM_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6279 | #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6280 | #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6281 | #define CAN_BTR_SILM_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6282 | #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6283 | #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6284 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6285 | /*!< Mailbox registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6286 | /****************** Bit definition for CAN_TI0R register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6287 | #define CAN_TI0R_TXRQ_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6288 | #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6289 | #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6290 | #define CAN_TI0R_RTR_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6291 | #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6292 | #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6293 | #define CAN_TI0R_IDE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6294 | #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6295 | #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6296 | #define CAN_TI0R_EXID_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6297 | #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6298 | #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6299 | #define CAN_TI0R_STID_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6300 | #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6301 | #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6302 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6303 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6304 | #define CAN_TDT0R_DLC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6305 | #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6306 | #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6307 | #define CAN_TDT0R_TGT_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6308 | #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6309 | #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6310 | #define CAN_TDT0R_TIME_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6311 | #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6312 | #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6313 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6314 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6315 | #define CAN_TDL0R_DATA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6316 | #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6317 | #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6318 | #define CAN_TDL0R_DATA1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6319 | #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6320 | #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6321 | #define CAN_TDL0R_DATA2_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6322 | #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6323 | #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6324 | #define CAN_TDL0R_DATA3_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6325 | #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6326 | #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6327 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6328 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6329 | #define CAN_TDH0R_DATA4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6330 | #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6331 | #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6332 | #define CAN_TDH0R_DATA5_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6333 | #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6334 | #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6335 | #define CAN_TDH0R_DATA6_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6336 | #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6337 | #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6338 | #define CAN_TDH0R_DATA7_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6339 | #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6340 | #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6341 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6342 | /******************* Bit definition for CAN_TI1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6343 | #define CAN_TI1R_TXRQ_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6344 | #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6345 | #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6346 | #define CAN_TI1R_RTR_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6347 | #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6348 | #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6349 | #define CAN_TI1R_IDE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6350 | #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6351 | #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6352 | #define CAN_TI1R_EXID_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6353 | #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6354 | #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6355 | #define CAN_TI1R_STID_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6356 | #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6357 | #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6358 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6359 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6360 | #define CAN_TDT1R_DLC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6361 | #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6362 | #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6363 | #define CAN_TDT1R_TGT_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6364 | #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6365 | #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6366 | #define CAN_TDT1R_TIME_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6367 | #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6368 | #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6369 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6370 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6371 | #define CAN_TDL1R_DATA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6372 | #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6373 | #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6374 | #define CAN_TDL1R_DATA1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6375 | #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6376 | #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6377 | #define CAN_TDL1R_DATA2_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6378 | #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6379 | #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6380 | #define CAN_TDL1R_DATA3_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6381 | #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6382 | #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6383 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6384 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6385 | #define CAN_TDH1R_DATA4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6386 | #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6387 | #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6388 | #define CAN_TDH1R_DATA5_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6389 | #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6390 | #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6391 | #define CAN_TDH1R_DATA6_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6392 | #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6393 | #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6394 | #define CAN_TDH1R_DATA7_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6395 | #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6396 | #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6397 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6398 | /******************* Bit definition for CAN_TI2R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6399 | #define CAN_TI2R_TXRQ_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6400 | #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6401 | #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6402 | #define CAN_TI2R_RTR_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6403 | #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6404 | #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6405 | #define CAN_TI2R_IDE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6406 | #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6407 | #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6408 | #define CAN_TI2R_EXID_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6409 | #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6410 | #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6411 | #define CAN_TI2R_STID_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6412 | #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6413 | #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6414 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6415 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6416 | #define CAN_TDT2R_DLC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6417 | #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6418 | #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6419 | #define CAN_TDT2R_TGT_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6420 | #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6421 | #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6422 | #define CAN_TDT2R_TIME_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6423 | #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6424 | #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6425 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6426 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6427 | #define CAN_TDL2R_DATA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6428 | #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6429 | #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6430 | #define CAN_TDL2R_DATA1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6431 | #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6432 | #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6433 | #define CAN_TDL2R_DATA2_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6434 | #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6435 | #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6436 | #define CAN_TDL2R_DATA3_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6437 | #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6438 | #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6439 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6440 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6441 | #define CAN_TDH2R_DATA4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6442 | #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6443 | #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6444 | #define CAN_TDH2R_DATA5_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6445 | #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6446 | #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6447 | #define CAN_TDH2R_DATA6_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6448 | #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6449 | #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6450 | #define CAN_TDH2R_DATA7_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6451 | #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6452 | #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6453 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6454 | /******************* Bit definition for CAN_RI0R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6455 | #define CAN_RI0R_RTR_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6456 | #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6457 | #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6458 | #define CAN_RI0R_IDE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6459 | #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6460 | #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6461 | #define CAN_RI0R_EXID_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6462 | #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6463 | #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6464 | #define CAN_RI0R_STID_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6465 | #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6466 | #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6467 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6468 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6469 | #define CAN_RDT0R_DLC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6470 | #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6471 | #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6472 | #define CAN_RDT0R_FMI_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6473 | #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6474 | #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6475 | #define CAN_RDT0R_TIME_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6476 | #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6477 | #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6478 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6479 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6480 | #define CAN_RDL0R_DATA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6481 | #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6482 | #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6483 | #define CAN_RDL0R_DATA1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6484 | #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6485 | #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6486 | #define CAN_RDL0R_DATA2_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6487 | #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6488 | #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6489 | #define CAN_RDL0R_DATA3_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6490 | #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6491 | #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6492 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6493 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6494 | #define CAN_RDH0R_DATA4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6495 | #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6496 | #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6497 | #define CAN_RDH0R_DATA5_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6498 | #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6499 | #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6500 | #define CAN_RDH0R_DATA6_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6501 | #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6502 | #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6503 | #define CAN_RDH0R_DATA7_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6504 | #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6505 | #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6506 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6507 | /******************* Bit definition for CAN_RI1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6508 | #define CAN_RI1R_RTR_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6509 | #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6510 | #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6511 | #define CAN_RI1R_IDE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6512 | #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6513 | #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6514 | #define CAN_RI1R_EXID_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6515 | #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6516 | #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6517 | #define CAN_RI1R_STID_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6518 | #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6519 | #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6520 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6521 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6522 | #define CAN_RDT1R_DLC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6523 | #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6524 | #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6525 | #define CAN_RDT1R_FMI_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6526 | #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6527 | #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6528 | #define CAN_RDT1R_TIME_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6529 | #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6530 | #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6531 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6532 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6533 | #define CAN_RDL1R_DATA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6534 | #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6535 | #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6536 | #define CAN_RDL1R_DATA1_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6537 | #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6538 | #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6539 | #define CAN_RDL1R_DATA2_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6540 | #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6541 | #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6542 | #define CAN_RDL1R_DATA3_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6543 | #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6544 | #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6545 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6546 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6547 | #define CAN_RDH1R_DATA4_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6548 | #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6549 | #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6550 | #define CAN_RDH1R_DATA5_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6551 | #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6552 | #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6553 | #define CAN_RDH1R_DATA6_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6554 | #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6555 | #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6556 | #define CAN_RDH1R_DATA7_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6557 | #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6558 | #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6559 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6560 | /*!< CAN filter registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6561 | /******************* Bit definition for CAN_FMR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6562 | #define CAN_FMR_FINIT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6563 | #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6564 | #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6565 | #define CAN_FMR_CAN2SB_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6566 | #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6567 | #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6568 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6569 | /******************* Bit definition for CAN_FM1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6570 | #define CAN_FM1R_FBM_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6571 | #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6572 | #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6573 | #define CAN_FM1R_FBM0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6574 | #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6575 | #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6576 | #define CAN_FM1R_FBM1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6577 | #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6578 | #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6579 | #define CAN_FM1R_FBM2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6580 | #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6581 | #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6582 | #define CAN_FM1R_FBM3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6583 | #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6584 | #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6585 | #define CAN_FM1R_FBM4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6586 | #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6587 | #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6588 | #define CAN_FM1R_FBM5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6589 | #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6590 | #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6591 | #define CAN_FM1R_FBM6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6592 | #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6593 | #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6594 | #define CAN_FM1R_FBM7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6595 | #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6596 | #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6597 | #define CAN_FM1R_FBM8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6598 | #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6599 | #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6600 | #define CAN_FM1R_FBM9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6601 | #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6602 | #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6603 | #define CAN_FM1R_FBM10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6604 | #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6605 | #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6606 | #define CAN_FM1R_FBM11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6607 | #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6608 | #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6609 | #define CAN_FM1R_FBM12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6610 | #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6611 | #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6612 | #define CAN_FM1R_FBM13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6613 | #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6614 | #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6615 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6616 | /******************* Bit definition for CAN_FS1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6617 | #define CAN_FS1R_FSC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6618 | #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6619 | #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6620 | #define CAN_FS1R_FSC0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6621 | #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6622 | #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6623 | #define CAN_FS1R_FSC1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6624 | #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6625 | #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6626 | #define CAN_FS1R_FSC2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6627 | #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6628 | #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6629 | #define CAN_FS1R_FSC3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6630 | #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6631 | #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6632 | #define CAN_FS1R_FSC4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6633 | #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6634 | #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6635 | #define CAN_FS1R_FSC5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6636 | #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6637 | #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6638 | #define CAN_FS1R_FSC6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6639 | #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6640 | #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6641 | #define CAN_FS1R_FSC7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6642 | #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6643 | #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6644 | #define CAN_FS1R_FSC8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6645 | #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6646 | #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6647 | #define CAN_FS1R_FSC9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6648 | #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6649 | #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6650 | #define CAN_FS1R_FSC10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6651 | #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6652 | #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6653 | #define CAN_FS1R_FSC11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6654 | #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6655 | #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6656 | #define CAN_FS1R_FSC12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6657 | #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6658 | #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6659 | #define CAN_FS1R_FSC13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6660 | #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6661 | #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6662 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6663 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6664 | #define CAN_FFA1R_FFA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6665 | #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6666 | #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6667 | #define CAN_FFA1R_FFA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6668 | #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6669 | #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6670 | #define CAN_FFA1R_FFA1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6671 | #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6672 | #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6673 | #define CAN_FFA1R_FFA2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6674 | #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6675 | #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6676 | #define CAN_FFA1R_FFA3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6677 | #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6678 | #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6679 | #define CAN_FFA1R_FFA4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6680 | #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6681 | #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6682 | #define CAN_FFA1R_FFA5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6683 | #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6684 | #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6685 | #define CAN_FFA1R_FFA6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6686 | #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6687 | #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6688 | #define CAN_FFA1R_FFA7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6689 | #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6690 | #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6691 | #define CAN_FFA1R_FFA8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6692 | #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6693 | #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6694 | #define CAN_FFA1R_FFA9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6695 | #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6696 | #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6697 | #define CAN_FFA1R_FFA10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6698 | #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6699 | #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6700 | #define CAN_FFA1R_FFA11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6701 | #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6702 | #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6703 | #define CAN_FFA1R_FFA12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6704 | #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6705 | #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6706 | #define CAN_FFA1R_FFA13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6707 | #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6708 | #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6709 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6710 | /******************* Bit definition for CAN_FA1R register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6711 | #define CAN_FA1R_FACT_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6712 | #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6713 | #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6714 | #define CAN_FA1R_FACT0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6715 | #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6716 | #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6717 | #define CAN_FA1R_FACT1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6718 | #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6719 | #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6720 | #define CAN_FA1R_FACT2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6721 | #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6722 | #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6723 | #define CAN_FA1R_FACT3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6724 | #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6725 | #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6726 | #define CAN_FA1R_FACT4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6727 | #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6728 | #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6729 | #define CAN_FA1R_FACT5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6730 | #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6731 | #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6732 | #define CAN_FA1R_FACT6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6733 | #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6734 | #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6735 | #define CAN_FA1R_FACT7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6736 | #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6737 | #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6738 | #define CAN_FA1R_FACT8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6739 | #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6740 | #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6741 | #define CAN_FA1R_FACT9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6742 | #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6743 | #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6744 | #define CAN_FA1R_FACT10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6745 | #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6746 | #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6747 | #define CAN_FA1R_FACT11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6748 | #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6749 | #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6750 | #define CAN_FA1R_FACT12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6751 | #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6752 | #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6753 | #define CAN_FA1R_FACT13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6754 | #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6755 | #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6756 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6757 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6758 | #define CAN_F0R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6759 | #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6760 | #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6761 | #define CAN_F0R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6762 | #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6763 | #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6764 | #define CAN_F0R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6765 | #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6766 | #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6767 | #define CAN_F0R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6768 | #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6769 | #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6770 | #define CAN_F0R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6771 | #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6772 | #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6773 | #define CAN_F0R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6774 | #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6775 | #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6776 | #define CAN_F0R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6777 | #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6778 | #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6779 | #define CAN_F0R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6780 | #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6781 | #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6782 | #define CAN_F0R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6783 | #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6784 | #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6785 | #define CAN_F0R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6786 | #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6787 | #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6788 | #define CAN_F0R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6789 | #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6790 | #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6791 | #define CAN_F0R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6792 | #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6793 | #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6794 | #define CAN_F0R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6795 | #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6796 | #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6797 | #define CAN_F0R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6798 | #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6799 | #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6800 | #define CAN_F0R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6801 | #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6802 | #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6803 | #define CAN_F0R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6804 | #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6805 | #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6806 | #define CAN_F0R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6807 | #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6808 | #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6809 | #define CAN_F0R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6810 | #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6811 | #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6812 | #define CAN_F0R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6813 | #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6814 | #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6815 | #define CAN_F0R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6816 | #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6817 | #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6818 | #define CAN_F0R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6819 | #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6820 | #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6821 | #define CAN_F0R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6822 | #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6823 | #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6824 | #define CAN_F0R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6825 | #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6826 | #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6827 | #define CAN_F0R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6828 | #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6829 | #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6830 | #define CAN_F0R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6831 | #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6832 | #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6833 | #define CAN_F0R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6834 | #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6835 | #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6836 | #define CAN_F0R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6837 | #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6838 | #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6839 | #define CAN_F0R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6840 | #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6841 | #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6842 | #define CAN_F0R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6843 | #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6844 | #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6845 | #define CAN_F0R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6846 | #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6847 | #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6848 | #define CAN_F0R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6849 | #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6850 | #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6851 | #define CAN_F0R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6852 | #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6853 | #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6854 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6855 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6856 | #define CAN_F1R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6857 | #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6858 | #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6859 | #define CAN_F1R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6860 | #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6861 | #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6862 | #define CAN_F1R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6863 | #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6864 | #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6865 | #define CAN_F1R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6866 | #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6867 | #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6868 | #define CAN_F1R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6869 | #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6870 | #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6871 | #define CAN_F1R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6872 | #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6873 | #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6874 | #define CAN_F1R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6875 | #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6876 | #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6877 | #define CAN_F1R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6878 | #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6879 | #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6880 | #define CAN_F1R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6881 | #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6882 | #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6883 | #define CAN_F1R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6884 | #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6885 | #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6886 | #define CAN_F1R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6887 | #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6888 | #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6889 | #define CAN_F1R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6890 | #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6891 | #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6892 | #define CAN_F1R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6893 | #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6894 | #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6895 | #define CAN_F1R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6896 | #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6897 | #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6898 | #define CAN_F1R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6899 | #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6900 | #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6901 | #define CAN_F1R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6902 | #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6903 | #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6904 | #define CAN_F1R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6905 | #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6906 | #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6907 | #define CAN_F1R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6908 | #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6909 | #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6910 | #define CAN_F1R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6911 | #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6912 | #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6913 | #define CAN_F1R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6914 | #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6915 | #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6916 | #define CAN_F1R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6917 | #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6918 | #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6919 | #define CAN_F1R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6920 | #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6921 | #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6922 | #define CAN_F1R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6923 | #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6924 | #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6925 | #define CAN_F1R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6926 | #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6927 | #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6928 | #define CAN_F1R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6929 | #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6930 | #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6931 | #define CAN_F1R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6932 | #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6933 | #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6934 | #define CAN_F1R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6935 | #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6936 | #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6937 | #define CAN_F1R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6938 | #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6939 | #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6940 | #define CAN_F1R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6941 | #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6942 | #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6943 | #define CAN_F1R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6944 | #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6945 | #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6946 | #define CAN_F1R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6947 | #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6948 | #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6949 | #define CAN_F1R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6950 | #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6951 | #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6952 | |
| Pawel Zarembski |
0:01f31e923fe2 | 6953 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 6954 | #define CAN_F2R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6955 | #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6956 | #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6957 | #define CAN_F2R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6958 | #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6959 | #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6960 | #define CAN_F2R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6961 | #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6962 | #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6963 | #define CAN_F2R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6964 | #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6965 | #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6966 | #define CAN_F2R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6967 | #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6968 | #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6969 | #define CAN_F2R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6970 | #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6971 | #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6972 | #define CAN_F2R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6973 | #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6974 | #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6975 | #define CAN_F2R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6976 | #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6977 | #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6978 | #define CAN_F2R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6979 | #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6980 | #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6981 | #define CAN_F2R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6982 | #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6983 | #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6984 | #define CAN_F2R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6985 | #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6986 | #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6987 | #define CAN_F2R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6988 | #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6989 | #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6990 | #define CAN_F2R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6991 | #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6992 | #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6993 | #define CAN_F2R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6994 | #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6995 | #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6996 | #define CAN_F2R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 6997 | #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6998 | #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6999 | #define CAN_F2R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7000 | #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7001 | #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7002 | #define CAN_F2R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7003 | #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7004 | #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7005 | #define CAN_F2R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7006 | #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7007 | #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7008 | #define CAN_F2R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7009 | #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7010 | #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7011 | #define CAN_F2R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7012 | #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7013 | #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7014 | #define CAN_F2R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7015 | #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7016 | #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7017 | #define CAN_F2R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7018 | #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7019 | #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7020 | #define CAN_F2R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7021 | #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7022 | #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7023 | #define CAN_F2R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7024 | #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7025 | #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7026 | #define CAN_F2R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7027 | #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7028 | #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7029 | #define CAN_F2R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7030 | #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7031 | #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7032 | #define CAN_F2R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7033 | #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7034 | #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7035 | #define CAN_F2R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7036 | #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7037 | #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7038 | #define CAN_F2R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7039 | #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7040 | #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7041 | #define CAN_F2R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7042 | #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7043 | #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7044 | #define CAN_F2R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7045 | #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7046 | #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7047 | #define CAN_F2R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7048 | #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7049 | #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7050 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7051 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7052 | #define CAN_F3R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7053 | #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7054 | #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7055 | #define CAN_F3R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7056 | #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7057 | #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7058 | #define CAN_F3R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7059 | #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7060 | #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7061 | #define CAN_F3R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7062 | #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7063 | #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7064 | #define CAN_F3R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7065 | #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7066 | #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7067 | #define CAN_F3R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7068 | #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7069 | #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7070 | #define CAN_F3R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7071 | #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7072 | #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7073 | #define CAN_F3R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7074 | #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7075 | #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7076 | #define CAN_F3R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7077 | #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7078 | #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7079 | #define CAN_F3R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7080 | #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7081 | #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7082 | #define CAN_F3R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7083 | #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7084 | #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7085 | #define CAN_F3R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7086 | #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7087 | #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7088 | #define CAN_F3R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7089 | #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7090 | #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7091 | #define CAN_F3R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7092 | #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7093 | #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7094 | #define CAN_F3R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7095 | #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7096 | #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7097 | #define CAN_F3R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7098 | #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7099 | #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7100 | #define CAN_F3R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7101 | #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7102 | #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7103 | #define CAN_F3R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7104 | #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7105 | #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7106 | #define CAN_F3R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7107 | #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7108 | #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7109 | #define CAN_F3R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7110 | #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7111 | #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7112 | #define CAN_F3R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7113 | #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7114 | #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7115 | #define CAN_F3R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7116 | #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7117 | #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7118 | #define CAN_F3R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7119 | #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7120 | #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7121 | #define CAN_F3R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7122 | #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7123 | #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7124 | #define CAN_F3R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7125 | #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7126 | #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7127 | #define CAN_F3R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7128 | #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7129 | #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7130 | #define CAN_F3R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7131 | #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7132 | #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7133 | #define CAN_F3R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7134 | #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7135 | #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7136 | #define CAN_F3R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7137 | #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7138 | #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7139 | #define CAN_F3R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7140 | #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7141 | #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7142 | #define CAN_F3R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7143 | #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7144 | #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7145 | #define CAN_F3R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7146 | #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7147 | #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */ |
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0:01f31e923fe2 | 7148 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7149 | /******************* Bit definition for CAN_F4R1 register *******************/ |
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0:01f31e923fe2 | 7150 | #define CAN_F4R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7151 | #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7152 | #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7153 | #define CAN_F4R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7154 | #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7155 | #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7156 | #define CAN_F4R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7157 | #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7158 | #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7159 | #define CAN_F4R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7160 | #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7161 | #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7162 | #define CAN_F4R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7163 | #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7164 | #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */ |
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0:01f31e923fe2 | 7165 | #define CAN_F4R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7166 | #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7167 | #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */ |
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0:01f31e923fe2 | 7168 | #define CAN_F4R1_FB6_Pos (6U) |
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0:01f31e923fe2 | 7169 | #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7170 | #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7171 | #define CAN_F4R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7172 | #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7173 | #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */ |
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0:01f31e923fe2 | 7174 | #define CAN_F4R1_FB8_Pos (8U) |
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0:01f31e923fe2 | 7175 | #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7176 | #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */ |
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0:01f31e923fe2 | 7177 | #define CAN_F4R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7178 | #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7179 | #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */ |
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0:01f31e923fe2 | 7180 | #define CAN_F4R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7181 | #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7182 | #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7183 | #define CAN_F4R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7184 | #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7185 | #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7186 | #define CAN_F4R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7187 | #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7188 | #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7189 | #define CAN_F4R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7190 | #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7191 | #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7192 | #define CAN_F4R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7193 | #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7194 | #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7195 | #define CAN_F4R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7196 | #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7197 | #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7198 | #define CAN_F4R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7199 | #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7200 | #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7201 | #define CAN_F4R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7202 | #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7203 | #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7204 | #define CAN_F4R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7205 | #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7206 | #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7207 | #define CAN_F4R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7208 | #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7209 | #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7210 | #define CAN_F4R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7211 | #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7212 | #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7213 | #define CAN_F4R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7214 | #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7215 | #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7216 | #define CAN_F4R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7217 | #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7218 | #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7219 | #define CAN_F4R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7220 | #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7221 | #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7222 | #define CAN_F4R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7223 | #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7224 | #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7225 | #define CAN_F4R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7226 | #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7227 | #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7228 | #define CAN_F4R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7229 | #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7230 | #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7231 | #define CAN_F4R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7232 | #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7233 | #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7234 | #define CAN_F4R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7235 | #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7236 | #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7237 | #define CAN_F4R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7238 | #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7239 | #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7240 | #define CAN_F4R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7241 | #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7242 | #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7243 | #define CAN_F4R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7244 | #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7245 | #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7246 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7247 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7248 | #define CAN_F5R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7249 | #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7250 | #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7251 | #define CAN_F5R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7252 | #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7253 | #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7254 | #define CAN_F5R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7255 | #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7256 | #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7257 | #define CAN_F5R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7258 | #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7259 | #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7260 | #define CAN_F5R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7261 | #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7262 | #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7263 | #define CAN_F5R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7264 | #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7265 | #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7266 | #define CAN_F5R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7267 | #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7268 | #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7269 | #define CAN_F5R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7270 | #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7271 | #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7272 | #define CAN_F5R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7273 | #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7274 | #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7275 | #define CAN_F5R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7276 | #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7277 | #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7278 | #define CAN_F5R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7279 | #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7280 | #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7281 | #define CAN_F5R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7282 | #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7283 | #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7284 | #define CAN_F5R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7285 | #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7286 | #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7287 | #define CAN_F5R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7288 | #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7289 | #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7290 | #define CAN_F5R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7291 | #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7292 | #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7293 | #define CAN_F5R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7294 | #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7295 | #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7296 | #define CAN_F5R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7297 | #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7298 | #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7299 | #define CAN_F5R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7300 | #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7301 | #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7302 | #define CAN_F5R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7303 | #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7304 | #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7305 | #define CAN_F5R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7306 | #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7307 | #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7308 | #define CAN_F5R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7309 | #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7310 | #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7311 | #define CAN_F5R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7312 | #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7313 | #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7314 | #define CAN_F5R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7315 | #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7316 | #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7317 | #define CAN_F5R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7318 | #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7319 | #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7320 | #define CAN_F5R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7321 | #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7322 | #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7323 | #define CAN_F5R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7324 | #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7325 | #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7326 | #define CAN_F5R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7327 | #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7328 | #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7329 | #define CAN_F5R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7330 | #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7331 | #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7332 | #define CAN_F5R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7333 | #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7334 | #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7335 | #define CAN_F5R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7336 | #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7337 | #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7338 | #define CAN_F5R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7339 | #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7340 | #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7341 | #define CAN_F5R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7342 | #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7343 | #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7344 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7345 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7346 | #define CAN_F6R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7347 | #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7348 | #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7349 | #define CAN_F6R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7350 | #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7351 | #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7352 | #define CAN_F6R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7353 | #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7354 | #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7355 | #define CAN_F6R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7356 | #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7357 | #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7358 | #define CAN_F6R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7359 | #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7360 | #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7361 | #define CAN_F6R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7362 | #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7363 | #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7364 | #define CAN_F6R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7365 | #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7366 | #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7367 | #define CAN_F6R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7368 | #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7369 | #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7370 | #define CAN_F6R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7371 | #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7372 | #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7373 | #define CAN_F6R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7374 | #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7375 | #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7376 | #define CAN_F6R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7377 | #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7378 | #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7379 | #define CAN_F6R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7380 | #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7381 | #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7382 | #define CAN_F6R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7383 | #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7384 | #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7385 | #define CAN_F6R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7386 | #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7387 | #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7388 | #define CAN_F6R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7389 | #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7390 | #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7391 | #define CAN_F6R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7392 | #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7393 | #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7394 | #define CAN_F6R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7395 | #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7396 | #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7397 | #define CAN_F6R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7398 | #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7399 | #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7400 | #define CAN_F6R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7401 | #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7402 | #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7403 | #define CAN_F6R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7404 | #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7405 | #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7406 | #define CAN_F6R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7407 | #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7408 | #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7409 | #define CAN_F6R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7410 | #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7411 | #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7412 | #define CAN_F6R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7413 | #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7414 | #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7415 | #define CAN_F6R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7416 | #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7417 | #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7418 | #define CAN_F6R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7419 | #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7420 | #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7421 | #define CAN_F6R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7422 | #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7423 | #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7424 | #define CAN_F6R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7425 | #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7426 | #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7427 | #define CAN_F6R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7428 | #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7429 | #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7430 | #define CAN_F6R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7431 | #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7432 | #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7433 | #define CAN_F6R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7434 | #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7435 | #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7436 | #define CAN_F6R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7437 | #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7438 | #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7439 | #define CAN_F6R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7440 | #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7441 | #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7442 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7443 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7444 | #define CAN_F7R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7445 | #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7446 | #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7447 | #define CAN_F7R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7448 | #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7449 | #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7450 | #define CAN_F7R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7451 | #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7452 | #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7453 | #define CAN_F7R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7454 | #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7455 | #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7456 | #define CAN_F7R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7457 | #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7458 | #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7459 | #define CAN_F7R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7460 | #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7461 | #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7462 | #define CAN_F7R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7463 | #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7464 | #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7465 | #define CAN_F7R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7466 | #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7467 | #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7468 | #define CAN_F7R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7469 | #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7470 | #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7471 | #define CAN_F7R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7472 | #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7473 | #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7474 | #define CAN_F7R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7475 | #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7476 | #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7477 | #define CAN_F7R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7478 | #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7479 | #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7480 | #define CAN_F7R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7481 | #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7482 | #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7483 | #define CAN_F7R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7484 | #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7485 | #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7486 | #define CAN_F7R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7487 | #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7488 | #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7489 | #define CAN_F7R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7490 | #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7491 | #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7492 | #define CAN_F7R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7493 | #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7494 | #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7495 | #define CAN_F7R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7496 | #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7497 | #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7498 | #define CAN_F7R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7499 | #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7500 | #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7501 | #define CAN_F7R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7502 | #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7503 | #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7504 | #define CAN_F7R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7505 | #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7506 | #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7507 | #define CAN_F7R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7508 | #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7509 | #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7510 | #define CAN_F7R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7511 | #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7512 | #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7513 | #define CAN_F7R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7514 | #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7515 | #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7516 | #define CAN_F7R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7517 | #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7518 | #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7519 | #define CAN_F7R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7520 | #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7521 | #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7522 | #define CAN_F7R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7523 | #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7524 | #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7525 | #define CAN_F7R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7526 | #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7527 | #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7528 | #define CAN_F7R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7529 | #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7530 | #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7531 | #define CAN_F7R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7532 | #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7533 | #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7534 | #define CAN_F7R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7535 | #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7536 | #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7537 | #define CAN_F7R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7538 | #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7539 | #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7540 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7541 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7542 | #define CAN_F8R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7543 | #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7544 | #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7545 | #define CAN_F8R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7546 | #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7547 | #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7548 | #define CAN_F8R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7549 | #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7550 | #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7551 | #define CAN_F8R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7552 | #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7553 | #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7554 | #define CAN_F8R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7555 | #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7556 | #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7557 | #define CAN_F8R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7558 | #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7559 | #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7560 | #define CAN_F8R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7561 | #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7562 | #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7563 | #define CAN_F8R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7564 | #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7565 | #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7566 | #define CAN_F8R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7567 | #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7568 | #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7569 | #define CAN_F8R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7570 | #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7571 | #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7572 | #define CAN_F8R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7573 | #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7574 | #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7575 | #define CAN_F8R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7576 | #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7577 | #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7578 | #define CAN_F8R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7579 | #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7580 | #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7581 | #define CAN_F8R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7582 | #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7583 | #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7584 | #define CAN_F8R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7585 | #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7586 | #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7587 | #define CAN_F8R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7588 | #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7589 | #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7590 | #define CAN_F8R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7591 | #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7592 | #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7593 | #define CAN_F8R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7594 | #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7595 | #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7596 | #define CAN_F8R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7597 | #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7598 | #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7599 | #define CAN_F8R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7600 | #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7601 | #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7602 | #define CAN_F8R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7603 | #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7604 | #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7605 | #define CAN_F8R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7606 | #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7607 | #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7608 | #define CAN_F8R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7609 | #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7610 | #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7611 | #define CAN_F8R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7612 | #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7613 | #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7614 | #define CAN_F8R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7615 | #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7616 | #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7617 | #define CAN_F8R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7618 | #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7619 | #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7620 | #define CAN_F8R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7621 | #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7622 | #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7623 | #define CAN_F8R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7624 | #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7625 | #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7626 | #define CAN_F8R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7627 | #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7628 | #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7629 | #define CAN_F8R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7630 | #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7631 | #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7632 | #define CAN_F8R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7633 | #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7634 | #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7635 | #define CAN_F8R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7636 | #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7637 | #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7638 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7639 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7640 | #define CAN_F9R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7641 | #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7642 | #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7643 | #define CAN_F9R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7644 | #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7645 | #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7646 | #define CAN_F9R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7647 | #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7648 | #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7649 | #define CAN_F9R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7650 | #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7651 | #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7652 | #define CAN_F9R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7653 | #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7654 | #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7655 | #define CAN_F9R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7656 | #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7657 | #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7658 | #define CAN_F9R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7659 | #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7660 | #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7661 | #define CAN_F9R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7662 | #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7663 | #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7664 | #define CAN_F9R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7665 | #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7666 | #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7667 | #define CAN_F9R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7668 | #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7669 | #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7670 | #define CAN_F9R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7671 | #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7672 | #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7673 | #define CAN_F9R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7674 | #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7675 | #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7676 | #define CAN_F9R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7677 | #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7678 | #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7679 | #define CAN_F9R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7680 | #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7681 | #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7682 | #define CAN_F9R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7683 | #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7684 | #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7685 | #define CAN_F9R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7686 | #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7687 | #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7688 | #define CAN_F9R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7689 | #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7690 | #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7691 | #define CAN_F9R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7692 | #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7693 | #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7694 | #define CAN_F9R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7695 | #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7696 | #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7697 | #define CAN_F9R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7698 | #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7699 | #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7700 | #define CAN_F9R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7701 | #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7702 | #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7703 | #define CAN_F9R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7704 | #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7705 | #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7706 | #define CAN_F9R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7707 | #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7708 | #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7709 | #define CAN_F9R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7710 | #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7711 | #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7712 | #define CAN_F9R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7713 | #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7714 | #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7715 | #define CAN_F9R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7716 | #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7717 | #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7718 | #define CAN_F9R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7719 | #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7720 | #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7721 | #define CAN_F9R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7722 | #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7723 | #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7724 | #define CAN_F9R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7725 | #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7726 | #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7727 | #define CAN_F9R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7728 | #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7729 | #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7730 | #define CAN_F9R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7731 | #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7732 | #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7733 | #define CAN_F9R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7734 | #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7735 | #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7736 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7737 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7738 | #define CAN_F10R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7739 | #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7740 | #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7741 | #define CAN_F10R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7742 | #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7743 | #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7744 | #define CAN_F10R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7745 | #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7746 | #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7747 | #define CAN_F10R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7748 | #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7749 | #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7750 | #define CAN_F10R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7751 | #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7752 | #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7753 | #define CAN_F10R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7754 | #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7755 | #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7756 | #define CAN_F10R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7757 | #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7758 | #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7759 | #define CAN_F10R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7760 | #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7761 | #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7762 | #define CAN_F10R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7763 | #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7764 | #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7765 | #define CAN_F10R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7766 | #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7767 | #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7768 | #define CAN_F10R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7769 | #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7770 | #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7771 | #define CAN_F10R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7772 | #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7773 | #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7774 | #define CAN_F10R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7775 | #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7776 | #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7777 | #define CAN_F10R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7778 | #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7779 | #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7780 | #define CAN_F10R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7781 | #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7782 | #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7783 | #define CAN_F10R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7784 | #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7785 | #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7786 | #define CAN_F10R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7787 | #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7788 | #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7789 | #define CAN_F10R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7790 | #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7791 | #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7792 | #define CAN_F10R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7793 | #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7794 | #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7795 | #define CAN_F10R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7796 | #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7797 | #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7798 | #define CAN_F10R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7799 | #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7800 | #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7801 | #define CAN_F10R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7802 | #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7803 | #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7804 | #define CAN_F10R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7805 | #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7806 | #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7807 | #define CAN_F10R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7808 | #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7809 | #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7810 | #define CAN_F10R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7811 | #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7812 | #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7813 | #define CAN_F10R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7814 | #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7815 | #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7816 | #define CAN_F10R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7817 | #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7818 | #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7819 | #define CAN_F10R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7820 | #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7821 | #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7822 | #define CAN_F10R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7823 | #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7824 | #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7825 | #define CAN_F10R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7826 | #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7827 | #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7828 | #define CAN_F10R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7829 | #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7830 | #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7831 | #define CAN_F10R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7832 | #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7833 | #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7834 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7835 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7836 | #define CAN_F11R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7837 | #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7838 | #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7839 | #define CAN_F11R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7840 | #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7841 | #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7842 | #define CAN_F11R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7843 | #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7844 | #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7845 | #define CAN_F11R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7846 | #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7847 | #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7848 | #define CAN_F11R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7849 | #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7850 | #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7851 | #define CAN_F11R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7852 | #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7853 | #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7854 | #define CAN_F11R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7855 | #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7856 | #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7857 | #define CAN_F11R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7858 | #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7859 | #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7860 | #define CAN_F11R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7861 | #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7862 | #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7863 | #define CAN_F11R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7864 | #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7865 | #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7866 | #define CAN_F11R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7867 | #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7868 | #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7869 | #define CAN_F11R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7870 | #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7871 | #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7872 | #define CAN_F11R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7873 | #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7874 | #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7875 | #define CAN_F11R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7876 | #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7877 | #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7878 | #define CAN_F11R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7879 | #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7880 | #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7881 | #define CAN_F11R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7882 | #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7883 | #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7884 | #define CAN_F11R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7885 | #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7886 | #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7887 | #define CAN_F11R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7888 | #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7889 | #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7890 | #define CAN_F11R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7891 | #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7892 | #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7893 | #define CAN_F11R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7894 | #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7895 | #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7896 | #define CAN_F11R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7897 | #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7898 | #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7899 | #define CAN_F11R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7900 | #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7901 | #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7902 | #define CAN_F11R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7903 | #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7904 | #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7905 | #define CAN_F11R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7906 | #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7907 | #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7908 | #define CAN_F11R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7909 | #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7910 | #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7911 | #define CAN_F11R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7912 | #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7913 | #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7914 | #define CAN_F11R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7915 | #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7916 | #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7917 | #define CAN_F11R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7918 | #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7919 | #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7920 | #define CAN_F11R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7921 | #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7922 | #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7923 | #define CAN_F11R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7924 | #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7925 | #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7926 | #define CAN_F11R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7927 | #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7928 | #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7929 | #define CAN_F11R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7930 | #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7931 | #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7932 | |
| Pawel Zarembski |
0:01f31e923fe2 | 7933 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 7934 | #define CAN_F12R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7935 | #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7936 | #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7937 | #define CAN_F12R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7938 | #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7939 | #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7940 | #define CAN_F12R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7941 | #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7942 | #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7943 | #define CAN_F12R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7944 | #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7945 | #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7946 | #define CAN_F12R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7947 | #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7948 | #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7949 | #define CAN_F12R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7950 | #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7951 | #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7952 | #define CAN_F12R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7953 | #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7954 | #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7955 | #define CAN_F12R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7956 | #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7957 | #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7958 | #define CAN_F12R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7959 | #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7960 | #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7961 | #define CAN_F12R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7962 | #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7963 | #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7964 | #define CAN_F12R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7965 | #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7966 | #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7967 | #define CAN_F12R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7968 | #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7969 | #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7970 | #define CAN_F12R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7971 | #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7972 | #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7973 | #define CAN_F12R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7974 | #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7975 | #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7976 | #define CAN_F12R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7977 | #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7978 | #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7979 | #define CAN_F12R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7980 | #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7981 | #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7982 | #define CAN_F12R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7983 | #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7984 | #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7985 | #define CAN_F12R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7986 | #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7987 | #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7988 | #define CAN_F12R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7989 | #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7990 | #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7991 | #define CAN_F12R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7992 | #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7993 | #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7994 | #define CAN_F12R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7995 | #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7996 | #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7997 | #define CAN_F12R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 7998 | #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7999 | #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8000 | #define CAN_F12R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8001 | #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8002 | #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8003 | #define CAN_F12R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8004 | #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8005 | #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8006 | #define CAN_F12R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8007 | #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8008 | #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8009 | #define CAN_F12R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8010 | #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8011 | #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8012 | #define CAN_F12R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8013 | #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8014 | #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8015 | #define CAN_F12R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8016 | #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8017 | #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8018 | #define CAN_F12R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8019 | #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8020 | #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8021 | #define CAN_F12R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8022 | #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8023 | #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8024 | #define CAN_F12R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8025 | #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8026 | #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8027 | #define CAN_F12R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8028 | #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8029 | #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8030 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8031 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8032 | #define CAN_F13R1_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8033 | #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8034 | #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8035 | #define CAN_F13R1_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8036 | #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8037 | #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8038 | #define CAN_F13R1_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8039 | #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8040 | #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8041 | #define CAN_F13R1_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8042 | #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8043 | #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8044 | #define CAN_F13R1_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8045 | #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8046 | #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8047 | #define CAN_F13R1_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8048 | #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8049 | #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8050 | #define CAN_F13R1_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8051 | #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8052 | #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8053 | #define CAN_F13R1_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8054 | #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8055 | #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8056 | #define CAN_F13R1_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8057 | #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8058 | #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8059 | #define CAN_F13R1_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8060 | #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8061 | #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8062 | #define CAN_F13R1_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8063 | #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8064 | #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8065 | #define CAN_F13R1_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8066 | #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8067 | #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8068 | #define CAN_F13R1_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8069 | #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8070 | #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8071 | #define CAN_F13R1_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8072 | #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8073 | #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8074 | #define CAN_F13R1_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8075 | #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8076 | #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8077 | #define CAN_F13R1_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8078 | #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8079 | #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8080 | #define CAN_F13R1_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8081 | #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8082 | #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8083 | #define CAN_F13R1_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8084 | #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8085 | #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8086 | #define CAN_F13R1_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8087 | #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8088 | #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8089 | #define CAN_F13R1_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8090 | #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8091 | #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8092 | #define CAN_F13R1_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8093 | #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8094 | #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8095 | #define CAN_F13R1_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8096 | #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8097 | #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8098 | #define CAN_F13R1_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8099 | #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8100 | #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8101 | #define CAN_F13R1_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8102 | #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8103 | #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8104 | #define CAN_F13R1_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8105 | #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8106 | #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8107 | #define CAN_F13R1_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8108 | #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8109 | #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8110 | #define CAN_F13R1_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8111 | #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8112 | #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8113 | #define CAN_F13R1_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8114 | #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8115 | #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8116 | #define CAN_F13R1_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8117 | #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8118 | #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8119 | #define CAN_F13R1_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8120 | #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8121 | #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8122 | #define CAN_F13R1_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8123 | #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8124 | #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8125 | #define CAN_F13R1_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8126 | #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8127 | #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8128 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8129 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8130 | #define CAN_F0R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8131 | #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8132 | #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8133 | #define CAN_F0R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8134 | #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8135 | #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8136 | #define CAN_F0R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8137 | #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8138 | #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8139 | #define CAN_F0R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8140 | #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8141 | #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8142 | #define CAN_F0R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8143 | #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8144 | #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8145 | #define CAN_F0R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8146 | #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8147 | #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8148 | #define CAN_F0R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8149 | #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8150 | #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8151 | #define CAN_F0R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8152 | #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8153 | #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8154 | #define CAN_F0R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8155 | #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8156 | #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8157 | #define CAN_F0R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8158 | #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8159 | #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8160 | #define CAN_F0R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8161 | #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8162 | #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8163 | #define CAN_F0R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8164 | #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8165 | #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8166 | #define CAN_F0R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8167 | #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8168 | #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8169 | #define CAN_F0R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8170 | #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8171 | #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8172 | #define CAN_F0R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8173 | #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8174 | #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8175 | #define CAN_F0R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8176 | #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8177 | #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8178 | #define CAN_F0R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8179 | #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8180 | #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8181 | #define CAN_F0R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8182 | #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8183 | #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8184 | #define CAN_F0R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8185 | #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8186 | #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8187 | #define CAN_F0R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8188 | #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8189 | #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8190 | #define CAN_F0R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8191 | #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8192 | #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8193 | #define CAN_F0R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8194 | #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8195 | #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8196 | #define CAN_F0R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8197 | #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8198 | #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8199 | #define CAN_F0R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8200 | #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8201 | #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8202 | #define CAN_F0R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8203 | #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8204 | #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8205 | #define CAN_F0R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8206 | #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8207 | #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8208 | #define CAN_F0R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8209 | #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8210 | #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8211 | #define CAN_F0R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8212 | #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8213 | #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8214 | #define CAN_F0R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8215 | #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8216 | #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8217 | #define CAN_F0R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8218 | #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8219 | #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8220 | #define CAN_F0R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8221 | #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8222 | #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8223 | #define CAN_F0R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8224 | #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8225 | #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8226 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8227 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8228 | #define CAN_F1R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8229 | #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8230 | #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8231 | #define CAN_F1R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8232 | #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8233 | #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8234 | #define CAN_F1R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8235 | #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8236 | #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8237 | #define CAN_F1R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8238 | #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8239 | #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8240 | #define CAN_F1R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8241 | #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8242 | #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8243 | #define CAN_F1R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8244 | #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8245 | #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8246 | #define CAN_F1R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8247 | #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8248 | #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8249 | #define CAN_F1R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8250 | #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8251 | #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8252 | #define CAN_F1R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8253 | #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8254 | #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8255 | #define CAN_F1R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8256 | #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8257 | #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8258 | #define CAN_F1R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8259 | #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8260 | #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8261 | #define CAN_F1R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8262 | #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8263 | #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8264 | #define CAN_F1R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8265 | #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8266 | #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8267 | #define CAN_F1R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8268 | #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8269 | #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8270 | #define CAN_F1R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8271 | #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8272 | #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8273 | #define CAN_F1R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8274 | #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8275 | #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8276 | #define CAN_F1R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8277 | #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8278 | #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8279 | #define CAN_F1R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8280 | #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8281 | #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8282 | #define CAN_F1R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8283 | #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8284 | #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8285 | #define CAN_F1R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8286 | #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8287 | #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8288 | #define CAN_F1R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8289 | #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8290 | #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8291 | #define CAN_F1R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8292 | #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8293 | #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8294 | #define CAN_F1R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8295 | #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8296 | #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8297 | #define CAN_F1R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8298 | #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8299 | #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8300 | #define CAN_F1R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8301 | #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8302 | #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8303 | #define CAN_F1R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8304 | #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8305 | #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8306 | #define CAN_F1R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8307 | #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8308 | #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8309 | #define CAN_F1R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8310 | #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8311 | #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8312 | #define CAN_F1R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8313 | #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8314 | #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8315 | #define CAN_F1R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8316 | #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8317 | #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8318 | #define CAN_F1R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8319 | #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8320 | #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8321 | #define CAN_F1R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8322 | #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8323 | #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8324 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8325 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8326 | #define CAN_F2R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8327 | #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8328 | #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8329 | #define CAN_F2R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8330 | #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8331 | #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8332 | #define CAN_F2R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8333 | #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8334 | #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8335 | #define CAN_F2R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8336 | #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8337 | #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8338 | #define CAN_F2R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8339 | #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8340 | #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8341 | #define CAN_F2R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8342 | #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8343 | #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8344 | #define CAN_F2R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8345 | #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8346 | #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8347 | #define CAN_F2R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8348 | #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8349 | #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8350 | #define CAN_F2R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8351 | #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8352 | #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8353 | #define CAN_F2R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8354 | #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8355 | #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8356 | #define CAN_F2R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8357 | #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8358 | #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8359 | #define CAN_F2R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8360 | #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8361 | #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8362 | #define CAN_F2R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8363 | #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8364 | #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8365 | #define CAN_F2R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8366 | #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8367 | #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8368 | #define CAN_F2R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8369 | #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8370 | #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8371 | #define CAN_F2R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8372 | #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8373 | #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8374 | #define CAN_F2R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8375 | #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8376 | #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8377 | #define CAN_F2R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8378 | #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8379 | #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8380 | #define CAN_F2R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8381 | #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8382 | #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8383 | #define CAN_F2R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8384 | #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8385 | #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8386 | #define CAN_F2R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8387 | #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8388 | #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8389 | #define CAN_F2R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8390 | #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8391 | #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8392 | #define CAN_F2R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8393 | #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8394 | #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8395 | #define CAN_F2R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8396 | #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8397 | #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8398 | #define CAN_F2R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8399 | #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8400 | #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8401 | #define CAN_F2R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8402 | #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8403 | #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8404 | #define CAN_F2R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8405 | #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8406 | #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8407 | #define CAN_F2R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8408 | #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8409 | #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8410 | #define CAN_F2R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8411 | #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8412 | #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8413 | #define CAN_F2R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8414 | #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8415 | #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8416 | #define CAN_F2R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8417 | #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8418 | #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8419 | #define CAN_F2R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8420 | #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8421 | #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8422 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8423 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8424 | #define CAN_F3R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8425 | #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8426 | #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8427 | #define CAN_F3R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8428 | #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8429 | #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8430 | #define CAN_F3R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8431 | #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8432 | #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8433 | #define CAN_F3R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8434 | #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8435 | #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8436 | #define CAN_F3R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8437 | #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8438 | #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8439 | #define CAN_F3R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8440 | #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8441 | #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8442 | #define CAN_F3R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8443 | #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8444 | #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8445 | #define CAN_F3R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8446 | #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8447 | #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8448 | #define CAN_F3R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8449 | #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8450 | #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8451 | #define CAN_F3R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8452 | #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8453 | #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8454 | #define CAN_F3R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8455 | #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8456 | #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8457 | #define CAN_F3R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8458 | #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8459 | #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8460 | #define CAN_F3R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8461 | #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8462 | #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8463 | #define CAN_F3R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8464 | #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8465 | #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8466 | #define CAN_F3R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8467 | #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8468 | #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8469 | #define CAN_F3R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8470 | #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8471 | #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8472 | #define CAN_F3R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8473 | #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8474 | #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8475 | #define CAN_F3R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8476 | #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8477 | #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8478 | #define CAN_F3R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8479 | #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8480 | #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8481 | #define CAN_F3R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8482 | #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8483 | #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8484 | #define CAN_F3R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8485 | #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8486 | #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8487 | #define CAN_F3R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8488 | #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8489 | #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8490 | #define CAN_F3R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8491 | #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8492 | #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8493 | #define CAN_F3R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8494 | #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8495 | #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8496 | #define CAN_F3R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8497 | #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8498 | #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8499 | #define CAN_F3R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8500 | #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8501 | #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8502 | #define CAN_F3R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8503 | #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8504 | #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8505 | #define CAN_F3R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8506 | #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8507 | #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8508 | #define CAN_F3R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8509 | #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8510 | #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8511 | #define CAN_F3R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8512 | #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8513 | #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8514 | #define CAN_F3R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8515 | #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8516 | #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8517 | #define CAN_F3R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8518 | #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8519 | #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8520 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8521 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8522 | #define CAN_F4R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8523 | #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8524 | #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8525 | #define CAN_F4R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8526 | #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8527 | #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8528 | #define CAN_F4R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8529 | #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8530 | #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8531 | #define CAN_F4R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8532 | #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8533 | #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8534 | #define CAN_F4R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8535 | #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8536 | #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8537 | #define CAN_F4R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8538 | #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8539 | #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8540 | #define CAN_F4R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8541 | #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8542 | #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8543 | #define CAN_F4R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8544 | #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8545 | #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8546 | #define CAN_F4R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8547 | #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8548 | #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8549 | #define CAN_F4R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8550 | #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8551 | #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8552 | #define CAN_F4R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8553 | #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8554 | #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8555 | #define CAN_F4R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8556 | #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8557 | #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8558 | #define CAN_F4R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8559 | #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8560 | #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8561 | #define CAN_F4R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8562 | #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8563 | #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8564 | #define CAN_F4R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8565 | #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8566 | #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8567 | #define CAN_F4R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8568 | #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8569 | #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8570 | #define CAN_F4R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8571 | #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8572 | #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8573 | #define CAN_F4R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8574 | #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8575 | #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8576 | #define CAN_F4R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8577 | #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8578 | #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8579 | #define CAN_F4R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8580 | #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8581 | #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8582 | #define CAN_F4R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8583 | #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8584 | #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8585 | #define CAN_F4R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8586 | #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8587 | #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8588 | #define CAN_F4R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8589 | #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8590 | #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8591 | #define CAN_F4R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8592 | #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8593 | #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8594 | #define CAN_F4R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8595 | #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8596 | #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8597 | #define CAN_F4R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8598 | #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8599 | #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8600 | #define CAN_F4R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8601 | #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8602 | #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8603 | #define CAN_F4R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8604 | #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8605 | #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8606 | #define CAN_F4R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8607 | #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8608 | #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8609 | #define CAN_F4R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8610 | #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8611 | #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8612 | #define CAN_F4R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8613 | #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8614 | #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8615 | #define CAN_F4R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8616 | #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8617 | #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8618 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8619 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8620 | #define CAN_F5R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8621 | #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8622 | #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8623 | #define CAN_F5R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8624 | #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8625 | #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8626 | #define CAN_F5R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8627 | #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8628 | #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8629 | #define CAN_F5R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8630 | #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8631 | #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8632 | #define CAN_F5R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8633 | #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8634 | #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8635 | #define CAN_F5R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8636 | #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8637 | #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8638 | #define CAN_F5R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8639 | #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8640 | #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8641 | #define CAN_F5R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8642 | #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8643 | #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8644 | #define CAN_F5R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8645 | #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8646 | #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8647 | #define CAN_F5R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8648 | #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8649 | #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8650 | #define CAN_F5R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8651 | #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8652 | #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8653 | #define CAN_F5R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8654 | #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8655 | #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8656 | #define CAN_F5R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8657 | #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8658 | #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8659 | #define CAN_F5R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8660 | #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8661 | #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8662 | #define CAN_F5R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8663 | #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8664 | #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8665 | #define CAN_F5R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8666 | #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8667 | #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8668 | #define CAN_F5R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8669 | #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8670 | #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8671 | #define CAN_F5R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8672 | #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8673 | #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8674 | #define CAN_F5R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8675 | #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8676 | #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8677 | #define CAN_F5R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8678 | #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8679 | #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8680 | #define CAN_F5R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8681 | #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8682 | #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8683 | #define CAN_F5R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8684 | #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8685 | #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8686 | #define CAN_F5R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8687 | #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8688 | #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8689 | #define CAN_F5R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8690 | #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8691 | #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8692 | #define CAN_F5R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8693 | #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8694 | #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8695 | #define CAN_F5R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8696 | #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8697 | #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8698 | #define CAN_F5R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8699 | #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8700 | #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8701 | #define CAN_F5R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8702 | #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8703 | #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8704 | #define CAN_F5R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8705 | #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8706 | #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8707 | #define CAN_F5R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8708 | #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8709 | #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8710 | #define CAN_F5R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8711 | #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8712 | #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8713 | #define CAN_F5R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8714 | #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8715 | #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8716 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8717 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8718 | #define CAN_F6R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8719 | #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8720 | #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8721 | #define CAN_F6R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8722 | #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8723 | #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8724 | #define CAN_F6R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8725 | #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8726 | #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8727 | #define CAN_F6R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8728 | #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8729 | #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8730 | #define CAN_F6R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8731 | #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8732 | #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8733 | #define CAN_F6R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8734 | #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8735 | #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8736 | #define CAN_F6R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8737 | #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8738 | #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8739 | #define CAN_F6R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8740 | #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8741 | #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8742 | #define CAN_F6R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8743 | #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8744 | #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8745 | #define CAN_F6R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8746 | #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8747 | #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8748 | #define CAN_F6R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8749 | #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8750 | #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8751 | #define CAN_F6R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8752 | #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8753 | #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8754 | #define CAN_F6R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8755 | #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8756 | #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8757 | #define CAN_F6R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8758 | #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8759 | #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8760 | #define CAN_F6R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8761 | #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8762 | #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8763 | #define CAN_F6R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8764 | #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8765 | #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8766 | #define CAN_F6R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8767 | #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8768 | #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8769 | #define CAN_F6R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8770 | #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8771 | #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8772 | #define CAN_F6R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8773 | #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8774 | #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8775 | #define CAN_F6R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8776 | #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8777 | #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8778 | #define CAN_F6R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8779 | #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8780 | #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8781 | #define CAN_F6R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8782 | #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8783 | #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8784 | #define CAN_F6R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8785 | #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8786 | #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8787 | #define CAN_F6R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8788 | #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8789 | #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8790 | #define CAN_F6R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8791 | #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8792 | #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8793 | #define CAN_F6R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8794 | #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8795 | #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8796 | #define CAN_F6R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8797 | #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8798 | #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8799 | #define CAN_F6R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8800 | #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8801 | #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8802 | #define CAN_F6R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8803 | #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8804 | #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8805 | #define CAN_F6R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8806 | #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8807 | #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8808 | #define CAN_F6R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8809 | #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8810 | #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8811 | #define CAN_F6R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8812 | #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8813 | #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8814 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8815 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8816 | #define CAN_F7R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8817 | #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8818 | #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8819 | #define CAN_F7R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8820 | #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8821 | #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8822 | #define CAN_F7R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8823 | #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8824 | #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8825 | #define CAN_F7R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8826 | #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8827 | #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8828 | #define CAN_F7R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8829 | #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8830 | #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8831 | #define CAN_F7R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8832 | #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8833 | #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8834 | #define CAN_F7R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8835 | #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8836 | #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8837 | #define CAN_F7R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8838 | #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8839 | #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8840 | #define CAN_F7R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8841 | #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8842 | #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8843 | #define CAN_F7R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8844 | #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8845 | #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8846 | #define CAN_F7R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8847 | #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8848 | #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8849 | #define CAN_F7R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8850 | #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8851 | #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8852 | #define CAN_F7R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8853 | #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8854 | #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8855 | #define CAN_F7R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8856 | #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8857 | #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8858 | #define CAN_F7R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8859 | #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8860 | #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8861 | #define CAN_F7R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8862 | #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8863 | #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8864 | #define CAN_F7R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8865 | #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8866 | #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8867 | #define CAN_F7R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8868 | #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8869 | #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8870 | #define CAN_F7R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8871 | #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8872 | #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8873 | #define CAN_F7R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8874 | #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8875 | #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8876 | #define CAN_F7R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8877 | #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8878 | #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8879 | #define CAN_F7R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8880 | #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8881 | #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8882 | #define CAN_F7R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8883 | #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8884 | #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8885 | #define CAN_F7R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8886 | #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8887 | #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8888 | #define CAN_F7R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8889 | #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8890 | #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8891 | #define CAN_F7R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8892 | #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8893 | #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8894 | #define CAN_F7R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8895 | #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8896 | #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8897 | #define CAN_F7R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8898 | #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8899 | #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8900 | #define CAN_F7R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8901 | #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8902 | #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8903 | #define CAN_F7R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8904 | #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8905 | #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8906 | #define CAN_F7R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8907 | #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8908 | #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8909 | #define CAN_F7R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8910 | #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8911 | #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8912 | |
| Pawel Zarembski |
0:01f31e923fe2 | 8913 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 8914 | #define CAN_F8R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8915 | #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8916 | #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8917 | #define CAN_F8R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8918 | #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8919 | #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8920 | #define CAN_F8R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8921 | #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8922 | #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8923 | #define CAN_F8R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8924 | #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8925 | #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8926 | #define CAN_F8R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8927 | #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8928 | #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8929 | #define CAN_F8R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8930 | #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8931 | #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8932 | #define CAN_F8R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8933 | #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8934 | #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8935 | #define CAN_F8R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8936 | #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8937 | #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8938 | #define CAN_F8R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8939 | #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8940 | #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8941 | #define CAN_F8R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8942 | #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8943 | #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8944 | #define CAN_F8R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8945 | #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8946 | #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8947 | #define CAN_F8R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8948 | #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8949 | #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8950 | #define CAN_F8R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8951 | #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8952 | #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8953 | #define CAN_F8R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8954 | #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8955 | #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8956 | #define CAN_F8R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8957 | #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8958 | #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8959 | #define CAN_F8R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8960 | #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8961 | #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8962 | #define CAN_F8R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8963 | #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8964 | #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8965 | #define CAN_F8R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8966 | #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8967 | #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8968 | #define CAN_F8R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8969 | #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8970 | #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8971 | #define CAN_F8R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8972 | #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8973 | #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8974 | #define CAN_F8R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8975 | #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8976 | #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8977 | #define CAN_F8R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8978 | #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8979 | #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8980 | #define CAN_F8R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8981 | #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8982 | #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8983 | #define CAN_F8R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8984 | #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8985 | #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8986 | #define CAN_F8R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8987 | #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8988 | #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8989 | #define CAN_F8R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8990 | #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8991 | #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8992 | #define CAN_F8R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8993 | #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8994 | #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8995 | #define CAN_F8R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8996 | #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8997 | #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8998 | #define CAN_F8R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 8999 | #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9000 | #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9001 | #define CAN_F8R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9002 | #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9003 | #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9004 | #define CAN_F8R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9005 | #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9006 | #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9007 | #define CAN_F8R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9008 | #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9009 | #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9010 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9011 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9012 | #define CAN_F9R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9013 | #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9014 | #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9015 | #define CAN_F9R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9016 | #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9017 | #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9018 | #define CAN_F9R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9019 | #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9020 | #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9021 | #define CAN_F9R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9022 | #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9023 | #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9024 | #define CAN_F9R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9025 | #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9026 | #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9027 | #define CAN_F9R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9028 | #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9029 | #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9030 | #define CAN_F9R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9031 | #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9032 | #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9033 | #define CAN_F9R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9034 | #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9035 | #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9036 | #define CAN_F9R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9037 | #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9038 | #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9039 | #define CAN_F9R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9040 | #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9041 | #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9042 | #define CAN_F9R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9043 | #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9044 | #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9045 | #define CAN_F9R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9046 | #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9047 | #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9048 | #define CAN_F9R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9049 | #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9050 | #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9051 | #define CAN_F9R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9052 | #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9053 | #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9054 | #define CAN_F9R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9055 | #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9056 | #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9057 | #define CAN_F9R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9058 | #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9059 | #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9060 | #define CAN_F9R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9061 | #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9062 | #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9063 | #define CAN_F9R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9064 | #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9065 | #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9066 | #define CAN_F9R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9067 | #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9068 | #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9069 | #define CAN_F9R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9070 | #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9071 | #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9072 | #define CAN_F9R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9073 | #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9074 | #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9075 | #define CAN_F9R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9076 | #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9077 | #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9078 | #define CAN_F9R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9079 | #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9080 | #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9081 | #define CAN_F9R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9082 | #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9083 | #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9084 | #define CAN_F9R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9085 | #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9086 | #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9087 | #define CAN_F9R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9088 | #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9089 | #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9090 | #define CAN_F9R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9091 | #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9092 | #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9093 | #define CAN_F9R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9094 | #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9095 | #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9096 | #define CAN_F9R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9097 | #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9098 | #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9099 | #define CAN_F9R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9100 | #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9101 | #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9102 | #define CAN_F9R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9103 | #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9104 | #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9105 | #define CAN_F9R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9106 | #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9107 | #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9108 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9109 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9110 | #define CAN_F10R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9111 | #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9112 | #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9113 | #define CAN_F10R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9114 | #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9115 | #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9116 | #define CAN_F10R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9117 | #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9118 | #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9119 | #define CAN_F10R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9120 | #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9121 | #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9122 | #define CAN_F10R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9123 | #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9124 | #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9125 | #define CAN_F10R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9126 | #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9127 | #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9128 | #define CAN_F10R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9129 | #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9130 | #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9131 | #define CAN_F10R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9132 | #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9133 | #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9134 | #define CAN_F10R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9135 | #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9136 | #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9137 | #define CAN_F10R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9138 | #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9139 | #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9140 | #define CAN_F10R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9141 | #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9142 | #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9143 | #define CAN_F10R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9144 | #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9145 | #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9146 | #define CAN_F10R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9147 | #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9148 | #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9149 | #define CAN_F10R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9150 | #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9151 | #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9152 | #define CAN_F10R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9153 | #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9154 | #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9155 | #define CAN_F10R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9156 | #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9157 | #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9158 | #define CAN_F10R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9159 | #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9160 | #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9161 | #define CAN_F10R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9162 | #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9163 | #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9164 | #define CAN_F10R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9165 | #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9166 | #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9167 | #define CAN_F10R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9168 | #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9169 | #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9170 | #define CAN_F10R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9171 | #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9172 | #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9173 | #define CAN_F10R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9174 | #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9175 | #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9176 | #define CAN_F10R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9177 | #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9178 | #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9179 | #define CAN_F10R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9180 | #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9181 | #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9182 | #define CAN_F10R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9183 | #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9184 | #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9185 | #define CAN_F10R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9186 | #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9187 | #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9188 | #define CAN_F10R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9189 | #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9190 | #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9191 | #define CAN_F10R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9192 | #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9193 | #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9194 | #define CAN_F10R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9195 | #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9196 | #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9197 | #define CAN_F10R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9198 | #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9199 | #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9200 | #define CAN_F10R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9201 | #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9202 | #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9203 | #define CAN_F10R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9204 | #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9205 | #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9206 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9207 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9208 | #define CAN_F11R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9209 | #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9210 | #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9211 | #define CAN_F11R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9212 | #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9213 | #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9214 | #define CAN_F11R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9215 | #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9216 | #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9217 | #define CAN_F11R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9218 | #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9219 | #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9220 | #define CAN_F11R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9221 | #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9222 | #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9223 | #define CAN_F11R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9224 | #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9225 | #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9226 | #define CAN_F11R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9227 | #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9228 | #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9229 | #define CAN_F11R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9230 | #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9231 | #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9232 | #define CAN_F11R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9233 | #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9234 | #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9235 | #define CAN_F11R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9236 | #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9237 | #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9238 | #define CAN_F11R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9239 | #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9240 | #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9241 | #define CAN_F11R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9242 | #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9243 | #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9244 | #define CAN_F11R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9245 | #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9246 | #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9247 | #define CAN_F11R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9248 | #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9249 | #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9250 | #define CAN_F11R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9251 | #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9252 | #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9253 | #define CAN_F11R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9254 | #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9255 | #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9256 | #define CAN_F11R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9257 | #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9258 | #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9259 | #define CAN_F11R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9260 | #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9261 | #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9262 | #define CAN_F11R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9263 | #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9264 | #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9265 | #define CAN_F11R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9266 | #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9267 | #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9268 | #define CAN_F11R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9269 | #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9270 | #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9271 | #define CAN_F11R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9272 | #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9273 | #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9274 | #define CAN_F11R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9275 | #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9276 | #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9277 | #define CAN_F11R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9278 | #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9279 | #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9280 | #define CAN_F11R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9281 | #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9282 | #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9283 | #define CAN_F11R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9284 | #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9285 | #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9286 | #define CAN_F11R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9287 | #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9288 | #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9289 | #define CAN_F11R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9290 | #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9291 | #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9292 | #define CAN_F11R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9293 | #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9294 | #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9295 | #define CAN_F11R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9296 | #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9297 | #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9298 | #define CAN_F11R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9299 | #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9300 | #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9301 | #define CAN_F11R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9302 | #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9303 | #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9304 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9305 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9306 | #define CAN_F12R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9307 | #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9308 | #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9309 | #define CAN_F12R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9310 | #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9311 | #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9312 | #define CAN_F12R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9313 | #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9314 | #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9315 | #define CAN_F12R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9316 | #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9317 | #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9318 | #define CAN_F12R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9319 | #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9320 | #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9321 | #define CAN_F12R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9322 | #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9323 | #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9324 | #define CAN_F12R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9325 | #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9326 | #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9327 | #define CAN_F12R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9328 | #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9329 | #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9330 | #define CAN_F12R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9331 | #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9332 | #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9333 | #define CAN_F12R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9334 | #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9335 | #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9336 | #define CAN_F12R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9337 | #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9338 | #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9339 | #define CAN_F12R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9340 | #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9341 | #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9342 | #define CAN_F12R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9343 | #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9344 | #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9345 | #define CAN_F12R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9346 | #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9347 | #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9348 | #define CAN_F12R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9349 | #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9350 | #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9351 | #define CAN_F12R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9352 | #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9353 | #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9354 | #define CAN_F12R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9355 | #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9356 | #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9357 | #define CAN_F12R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9358 | #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9359 | #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9360 | #define CAN_F12R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9361 | #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9362 | #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9363 | #define CAN_F12R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9364 | #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9365 | #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9366 | #define CAN_F12R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9367 | #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9368 | #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9369 | #define CAN_F12R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9370 | #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9371 | #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9372 | #define CAN_F12R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9373 | #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9374 | #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9375 | #define CAN_F12R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9376 | #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9377 | #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9378 | #define CAN_F12R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9379 | #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9380 | #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9381 | #define CAN_F12R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9382 | #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9383 | #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9384 | #define CAN_F12R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9385 | #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9386 | #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9387 | #define CAN_F12R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9388 | #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9389 | #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9390 | #define CAN_F12R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9391 | #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9392 | #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9393 | #define CAN_F12R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9394 | #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9395 | #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9396 | #define CAN_F12R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9397 | #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9398 | #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9399 | #define CAN_F12R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9400 | #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9401 | #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9402 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9403 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9404 | #define CAN_F13R2_FB0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9405 | #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9406 | #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9407 | #define CAN_F13R2_FB1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9408 | #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9409 | #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9410 | #define CAN_F13R2_FB2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9411 | #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9412 | #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9413 | #define CAN_F13R2_FB3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9414 | #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9415 | #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9416 | #define CAN_F13R2_FB4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9417 | #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9418 | #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9419 | #define CAN_F13R2_FB5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9420 | #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9421 | #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9422 | #define CAN_F13R2_FB6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9423 | #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9424 | #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9425 | #define CAN_F13R2_FB7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9426 | #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9427 | #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9428 | #define CAN_F13R2_FB8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9429 | #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9430 | #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9431 | #define CAN_F13R2_FB9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9432 | #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9433 | #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9434 | #define CAN_F13R2_FB10_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9435 | #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9436 | #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9437 | #define CAN_F13R2_FB11_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9438 | #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9439 | #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9440 | #define CAN_F13R2_FB12_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9441 | #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9442 | #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9443 | #define CAN_F13R2_FB13_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9444 | #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9445 | #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9446 | #define CAN_F13R2_FB14_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9447 | #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9448 | #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9449 | #define CAN_F13R2_FB15_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9450 | #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9451 | #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9452 | #define CAN_F13R2_FB16_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9453 | #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9454 | #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9455 | #define CAN_F13R2_FB17_Pos (17U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9456 | #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9457 | #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9458 | #define CAN_F13R2_FB18_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9459 | #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9460 | #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9461 | #define CAN_F13R2_FB19_Pos (19U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9462 | #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9463 | #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9464 | #define CAN_F13R2_FB20_Pos (20U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9465 | #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9466 | #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9467 | #define CAN_F13R2_FB21_Pos (21U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9468 | #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9469 | #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9470 | #define CAN_F13R2_FB22_Pos (22U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9471 | #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9472 | #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9473 | #define CAN_F13R2_FB23_Pos (23U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9474 | #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9475 | #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9476 | #define CAN_F13R2_FB24_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9477 | #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9478 | #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9479 | #define CAN_F13R2_FB25_Pos (25U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9480 | #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9481 | #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9482 | #define CAN_F13R2_FB26_Pos (26U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9483 | #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9484 | #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9485 | #define CAN_F13R2_FB27_Pos (27U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9486 | #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9487 | #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9488 | #define CAN_F13R2_FB28_Pos (28U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9489 | #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9490 | #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9491 | #define CAN_F13R2_FB29_Pos (29U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9492 | #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9493 | #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9494 | #define CAN_F13R2_FB30_Pos (30U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9495 | #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9496 | #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9497 | #define CAN_F13R2_FB31_Pos (31U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9498 | #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9499 | #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9500 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9501 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9502 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9503 | /* Serial Peripheral Interface */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9504 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9505 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9506 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9507 | /******************* Bit definition for SPI_CR1 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9508 | #define SPI_CR1_CPHA_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9509 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9510 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9511 | #define SPI_CR1_CPOL_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9512 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9513 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9514 | #define SPI_CR1_MSTR_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9515 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9516 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9517 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9518 | #define SPI_CR1_BR_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9519 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9520 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9521 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9522 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9523 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9524 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9525 | #define SPI_CR1_SPE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9526 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9527 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9528 | #define SPI_CR1_LSBFIRST_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9529 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9530 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9531 | #define SPI_CR1_SSI_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9532 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9533 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9534 | #define SPI_CR1_SSM_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9535 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9536 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9537 | #define SPI_CR1_RXONLY_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9538 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9539 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9540 | #define SPI_CR1_DFF_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9541 | #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9542 | #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9543 | #define SPI_CR1_CRCNEXT_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9544 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9545 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9546 | #define SPI_CR1_CRCEN_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9547 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9548 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9549 | #define SPI_CR1_BIDIOE_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9550 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9551 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9552 | #define SPI_CR1_BIDIMODE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9553 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9554 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9555 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9556 | /******************* Bit definition for SPI_CR2 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9557 | #define SPI_CR2_RXDMAEN_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9558 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9559 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9560 | #define SPI_CR2_TXDMAEN_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9561 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9562 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9563 | #define SPI_CR2_SSOE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9564 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9565 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9566 | #define SPI_CR2_ERRIE_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9567 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9568 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9569 | #define SPI_CR2_RXNEIE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9570 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9571 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9572 | #define SPI_CR2_TXEIE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9573 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9574 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9575 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9576 | /******************** Bit definition for SPI_SR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9577 | #define SPI_SR_RXNE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9578 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9579 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9580 | #define SPI_SR_TXE_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9581 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9582 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9583 | #define SPI_SR_CHSIDE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9584 | #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9585 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9586 | #define SPI_SR_UDR_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9587 | #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9588 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9589 | #define SPI_SR_CRCERR_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9590 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9591 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9592 | #define SPI_SR_MODF_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9593 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9594 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9595 | #define SPI_SR_OVR_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9596 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9597 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9598 | #define SPI_SR_BSY_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9599 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9600 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9601 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9602 | /******************** Bit definition for SPI_DR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9603 | #define SPI_DR_DR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9604 | #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9605 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9606 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9607 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9608 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9609 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9610 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9611 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9612 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9613 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9614 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9615 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9616 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9617 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9618 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9619 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9620 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9621 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9622 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9623 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9624 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9625 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9626 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9627 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9628 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9629 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9630 | /* Inter-integrated Circuit Interface */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9631 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9632 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9633 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9634 | /******************* Bit definition for I2C_CR1 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9635 | #define I2C_CR1_PE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9636 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9637 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9638 | #define I2C_CR1_SMBUS_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9639 | #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9640 | #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9641 | #define I2C_CR1_SMBTYPE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9642 | #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9643 | #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9644 | #define I2C_CR1_ENARP_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9645 | #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9646 | #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9647 | #define I2C_CR1_ENPEC_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9648 | #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9649 | #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9650 | #define I2C_CR1_ENGC_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9651 | #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9652 | #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9653 | #define I2C_CR1_NOSTRETCH_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9654 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9655 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9656 | #define I2C_CR1_START_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9657 | #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9658 | #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9659 | #define I2C_CR1_STOP_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9660 | #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9661 | #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9662 | #define I2C_CR1_ACK_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9663 | #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9664 | #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9665 | #define I2C_CR1_POS_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9666 | #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9667 | #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9668 | #define I2C_CR1_PEC_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9669 | #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9670 | #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9671 | #define I2C_CR1_ALERT_Pos (13U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9672 | #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9673 | #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9674 | #define I2C_CR1_SWRST_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9675 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9676 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9677 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9678 | /******************* Bit definition for I2C_CR2 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9679 | #define I2C_CR2_FREQ_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9680 | #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9681 | #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9682 | #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9683 | #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9684 | #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9685 | #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9686 | #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9687 | #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9688 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9689 | #define I2C_CR2_ITERREN_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9690 | #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9691 | #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9692 | #define I2C_CR2_ITEVTEN_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9693 | #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9694 | #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9695 | #define I2C_CR2_ITBUFEN_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9696 | #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9697 | #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9698 | #define I2C_CR2_DMAEN_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9699 | #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9700 | #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9701 | #define I2C_CR2_LAST_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9702 | #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9703 | #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9704 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9705 | /******************* Bit definition for I2C_OAR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9706 | #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9707 | #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9708 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9709 | #define I2C_OAR1_ADD0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9710 | #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9711 | #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9712 | #define I2C_OAR1_ADD1_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9713 | #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9714 | #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9715 | #define I2C_OAR1_ADD2_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9716 | #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9717 | #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9718 | #define I2C_OAR1_ADD3_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9719 | #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9720 | #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9721 | #define I2C_OAR1_ADD4_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9722 | #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9723 | #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9724 | #define I2C_OAR1_ADD5_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9725 | #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9726 | #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9727 | #define I2C_OAR1_ADD6_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9728 | #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9729 | #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9730 | #define I2C_OAR1_ADD7_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9731 | #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9732 | #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9733 | #define I2C_OAR1_ADD8_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9734 | #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9735 | #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9736 | #define I2C_OAR1_ADD9_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9737 | #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9738 | #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9739 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9740 | #define I2C_OAR1_ADDMODE_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9741 | #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9742 | #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9743 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9744 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9745 | #define I2C_OAR2_ENDUAL_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9746 | #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9747 | #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9748 | #define I2C_OAR2_ADD2_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9749 | #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9750 | #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9751 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9752 | /******************* Bit definition for I2C_SR1 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9753 | #define I2C_SR1_SB_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9754 | #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9755 | #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9756 | #define I2C_SR1_ADDR_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9757 | #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9758 | #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9759 | #define I2C_SR1_BTF_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9760 | #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9761 | #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9762 | #define I2C_SR1_ADD10_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9763 | #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9764 | #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9765 | #define I2C_SR1_STOPF_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9766 | #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9767 | #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9768 | #define I2C_SR1_RXNE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9769 | #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9770 | #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9771 | #define I2C_SR1_TXE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9772 | #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9773 | #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9774 | #define I2C_SR1_BERR_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9775 | #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9776 | #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9777 | #define I2C_SR1_ARLO_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9778 | #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9779 | #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9780 | #define I2C_SR1_AF_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9781 | #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9782 | #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9783 | #define I2C_SR1_OVR_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9784 | #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9785 | #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9786 | #define I2C_SR1_PECERR_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9787 | #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9788 | #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9789 | #define I2C_SR1_TIMEOUT_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9790 | #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9791 | #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9792 | #define I2C_SR1_SMBALERT_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9793 | #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9794 | #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9795 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9796 | /******************* Bit definition for I2C_SR2 register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9797 | #define I2C_SR2_MSL_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9798 | #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9799 | #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9800 | #define I2C_SR2_BUSY_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9801 | #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9802 | #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9803 | #define I2C_SR2_TRA_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9804 | #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9805 | #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9806 | #define I2C_SR2_GENCALL_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9807 | #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9808 | #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9809 | #define I2C_SR2_SMBDEFAULT_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9810 | #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9811 | #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9812 | #define I2C_SR2_SMBHOST_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9813 | #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9814 | #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9815 | #define I2C_SR2_DUALF_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9816 | #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9817 | #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9818 | #define I2C_SR2_PEC_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9819 | #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9820 | #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9821 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9822 | /******************* Bit definition for I2C_CCR register ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9823 | #define I2C_CCR_CCR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9824 | #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9825 | #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9826 | #define I2C_CCR_DUTY_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9827 | #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9828 | #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9829 | #define I2C_CCR_FS_Pos (15U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9830 | #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9831 | #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9832 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9833 | /****************** Bit definition for I2C_TRISE register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9834 | #define I2C_TRISE_TRISE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9835 | #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9836 | #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9837 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9838 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9839 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9840 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9841 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9842 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9843 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9844 | /******************* Bit definition for USART_SR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9845 | #define USART_SR_PE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9846 | #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9847 | #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9848 | #define USART_SR_FE_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9849 | #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9850 | #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9851 | #define USART_SR_NE_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9852 | #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9853 | #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9854 | #define USART_SR_ORE_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9855 | #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9856 | #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9857 | #define USART_SR_IDLE_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9858 | #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9859 | #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9860 | #define USART_SR_RXNE_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9861 | #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9862 | #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9863 | #define USART_SR_TC_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9864 | #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9865 | #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9866 | #define USART_SR_TXE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9867 | #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9868 | #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9869 | #define USART_SR_LBD_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9870 | #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9871 | #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9872 | #define USART_SR_CTS_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9873 | #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9874 | #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9875 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9876 | /******************* Bit definition for USART_DR register *******************/ |
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0:01f31e923fe2 | 9877 | #define USART_DR_DR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9878 | #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9879 | #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9880 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9881 | /****************** Bit definition for USART_BRR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9882 | #define USART_BRR_DIV_Fraction_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9883 | #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9884 | #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9885 | #define USART_BRR_DIV_Mantissa_Pos (4U) |
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0:01f31e923fe2 | 9886 | #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9887 | #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9888 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9889 | /****************** Bit definition for USART_CR1 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9890 | #define USART_CR1_SBK_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9891 | #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9892 | #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9893 | #define USART_CR1_RWU_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9894 | #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 9895 | #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ |
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0:01f31e923fe2 | 9896 | #define USART_CR1_RE_Pos (2U) |
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0:01f31e923fe2 | 9897 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9898 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
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0:01f31e923fe2 | 9899 | #define USART_CR1_TE_Pos (3U) |
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0:01f31e923fe2 | 9900 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9901 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
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0:01f31e923fe2 | 9902 | #define USART_CR1_IDLEIE_Pos (4U) |
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0:01f31e923fe2 | 9903 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9904 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
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0:01f31e923fe2 | 9905 | #define USART_CR1_RXNEIE_Pos (5U) |
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0:01f31e923fe2 | 9906 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9907 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9908 | #define USART_CR1_TCIE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9909 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9910 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9911 | #define USART_CR1_TXEIE_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9912 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9913 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9914 | #define USART_CR1_PEIE_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9915 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9916 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9917 | #define USART_CR1_PS_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9918 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9919 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
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0:01f31e923fe2 | 9920 | #define USART_CR1_PCE_Pos (10U) |
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0:01f31e923fe2 | 9921 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9922 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9923 | #define USART_CR1_WAKE_Pos (11U) |
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0:01f31e923fe2 | 9924 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9925 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9926 | #define USART_CR1_M_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9927 | #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9928 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9929 | #define USART_CR1_UE_Pos (13U) |
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0:01f31e923fe2 | 9930 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9931 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9932 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9933 | /****************** Bit definition for USART_CR2 register *******************/ |
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0:01f31e923fe2 | 9934 | #define USART_CR2_ADD_Pos (0U) |
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0:01f31e923fe2 | 9935 | #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9936 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9937 | #define USART_CR2_LBDL_Pos (5U) |
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0:01f31e923fe2 | 9938 | #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9939 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9940 | #define USART_CR2_LBDIE_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9941 | #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9942 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9943 | #define USART_CR2_LBCL_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9944 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9945 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
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0:01f31e923fe2 | 9946 | #define USART_CR2_CPHA_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9947 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9948 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9949 | #define USART_CR2_CPOL_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9950 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9951 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9952 | #define USART_CR2_CLKEN_Pos (11U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9953 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9954 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9955 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9956 | #define USART_CR2_STOP_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9957 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9958 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9959 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9960 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9961 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9962 | #define USART_CR2_LINEN_Pos (14U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9963 | #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9964 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9965 | |
| Pawel Zarembski |
0:01f31e923fe2 | 9966 | /****************** Bit definition for USART_CR3 register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 9967 | #define USART_CR3_EIE_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9968 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9969 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9970 | #define USART_CR3_IREN_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9971 | #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9972 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9973 | #define USART_CR3_IRLP_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9974 | #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9975 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9976 | #define USART_CR3_HDSEL_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9977 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9978 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9979 | #define USART_CR3_NACK_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9980 | #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9981 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9982 | #define USART_CR3_SCEN_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9983 | #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9984 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9985 | #define USART_CR3_DMAR_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9986 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9987 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9988 | #define USART_CR3_DMAT_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9989 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9990 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9991 | #define USART_CR3_RTSE_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9992 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9993 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9994 | #define USART_CR3_CTSE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9995 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9996 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9997 | #define USART_CR3_CTSIE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 9998 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9999 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10000 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10001 | /****************** Bit definition for USART_GTPR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10002 | #define USART_GTPR_PSC_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10003 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10004 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10005 | #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10006 | #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10007 | #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10008 | #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10009 | #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10010 | #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10011 | #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10012 | #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10013 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10014 | #define USART_GTPR_GT_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10015 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10016 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10017 | |
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0:01f31e923fe2 | 10018 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10019 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10020 | /* Debug MCU */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10021 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10022 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10023 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10024 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10025 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
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0:01f31e923fe2 | 10026 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
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0:01f31e923fe2 | 10027 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
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0:01f31e923fe2 | 10028 | |
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0:01f31e923fe2 | 10029 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
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0:01f31e923fe2 | 10030 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
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0:01f31e923fe2 | 10031 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
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0:01f31e923fe2 | 10032 | #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 10033 | #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
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0:01f31e923fe2 | 10034 | #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
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0:01f31e923fe2 | 10035 | #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
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0:01f31e923fe2 | 10036 | #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
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0:01f31e923fe2 | 10037 | #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
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0:01f31e923fe2 | 10038 | #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
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0:01f31e923fe2 | 10039 | #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
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0:01f31e923fe2 | 10040 | #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
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0:01f31e923fe2 | 10041 | #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
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0:01f31e923fe2 | 10042 | #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
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0:01f31e923fe2 | 10043 | #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
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0:01f31e923fe2 | 10044 | #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
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0:01f31e923fe2 | 10045 | #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
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0:01f31e923fe2 | 10046 | #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
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0:01f31e923fe2 | 10047 | #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
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0:01f31e923fe2 | 10048 | |
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0:01f31e923fe2 | 10049 | /****************** Bit definition for DBGMCU_CR register *******************/ |
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0:01f31e923fe2 | 10050 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
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0:01f31e923fe2 | 10051 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 10052 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ |
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0:01f31e923fe2 | 10053 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
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0:01f31e923fe2 | 10054 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 10055 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
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0:01f31e923fe2 | 10056 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
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0:01f31e923fe2 | 10057 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 10058 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
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0:01f31e923fe2 | 10059 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
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0:01f31e923fe2 | 10060 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 10061 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ |
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0:01f31e923fe2 | 10062 | |
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0:01f31e923fe2 | 10063 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
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0:01f31e923fe2 | 10064 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
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0:01f31e923fe2 | 10065 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
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0:01f31e923fe2 | 10066 | #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
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0:01f31e923fe2 | 10067 | #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
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0:01f31e923fe2 | 10068 | |
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0:01f31e923fe2 | 10069 | #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) |
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0:01f31e923fe2 | 10070 | #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ |
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0:01f31e923fe2 | 10071 | #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
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0:01f31e923fe2 | 10072 | #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) |
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0:01f31e923fe2 | 10073 | #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ |
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0:01f31e923fe2 | 10074 | #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
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0:01f31e923fe2 | 10075 | #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) |
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0:01f31e923fe2 | 10076 | #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ |
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0:01f31e923fe2 | 10077 | #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ |
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0:01f31e923fe2 | 10078 | #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) |
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0:01f31e923fe2 | 10079 | #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ |
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0:01f31e923fe2 | 10080 | #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
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0:01f31e923fe2 | 10081 | #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) |
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0:01f31e923fe2 | 10082 | #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ |
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0:01f31e923fe2 | 10083 | #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ |
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0:01f31e923fe2 | 10084 | #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) |
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0:01f31e923fe2 | 10085 | #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ |
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0:01f31e923fe2 | 10086 | #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ |
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0:01f31e923fe2 | 10087 | #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) |
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0:01f31e923fe2 | 10088 | #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ |
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0:01f31e923fe2 | 10089 | #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ |
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0:01f31e923fe2 | 10090 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) |
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0:01f31e923fe2 | 10091 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ |
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0:01f31e923fe2 | 10092 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
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0:01f31e923fe2 | 10093 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) |
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0:01f31e923fe2 | 10094 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ |
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0:01f31e923fe2 | 10095 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
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0:01f31e923fe2 | 10096 | |
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0:01f31e923fe2 | 10097 | /******************************************************************************/ |
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0:01f31e923fe2 | 10098 | /* */ |
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0:01f31e923fe2 | 10099 | /* FLASH and Option Bytes Registers */ |
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0:01f31e923fe2 | 10100 | /* */ |
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0:01f31e923fe2 | 10101 | /******************************************************************************/ |
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0:01f31e923fe2 | 10102 | /******************* Bit definition for FLASH_ACR register ******************/ |
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0:01f31e923fe2 | 10103 | #define FLASH_ACR_LATENCY_Pos (0U) |
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0:01f31e923fe2 | 10104 | #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ |
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0:01f31e923fe2 | 10105 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ |
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0:01f31e923fe2 | 10106 | #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 10107 | #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 10108 | #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 10109 | |
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0:01f31e923fe2 | 10110 | #define FLASH_ACR_HLFCYA_Pos (3U) |
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0:01f31e923fe2 | 10111 | #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ |
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0:01f31e923fe2 | 10112 | #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ |
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0:01f31e923fe2 | 10113 | #define FLASH_ACR_PRFTBE_Pos (4U) |
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0:01f31e923fe2 | 10114 | #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 10115 | #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ |
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0:01f31e923fe2 | 10116 | #define FLASH_ACR_PRFTBS_Pos (5U) |
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0:01f31e923fe2 | 10117 | #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 10118 | #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ |
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0:01f31e923fe2 | 10119 | |
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0:01f31e923fe2 | 10120 | /****************** Bit definition for FLASH_KEYR register ******************/ |
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0:01f31e923fe2 | 10121 | #define FLASH_KEYR_FKEYR_Pos (0U) |
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0:01f31e923fe2 | 10122 | #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 10123 | #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ |
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0:01f31e923fe2 | 10124 | |
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0:01f31e923fe2 | 10125 | #define RDP_KEY_Pos (0U) |
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0:01f31e923fe2 | 10126 | #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */ |
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0:01f31e923fe2 | 10127 | #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ |
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0:01f31e923fe2 | 10128 | #define FLASH_KEY1_Pos (0U) |
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0:01f31e923fe2 | 10129 | #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ |
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0:01f31e923fe2 | 10130 | #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ |
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0:01f31e923fe2 | 10131 | #define FLASH_KEY2_Pos (0U) |
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0:01f31e923fe2 | 10132 | #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ |
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0:01f31e923fe2 | 10133 | #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ |
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0:01f31e923fe2 | 10134 | |
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0:01f31e923fe2 | 10135 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
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0:01f31e923fe2 | 10136 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
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0:01f31e923fe2 | 10137 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
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0:01f31e923fe2 | 10138 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ |
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0:01f31e923fe2 | 10139 | |
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0:01f31e923fe2 | 10140 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
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0:01f31e923fe2 | 10141 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
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0:01f31e923fe2 | 10142 | |
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0:01f31e923fe2 | 10143 | /****************** Bit definition for FLASH_SR register ********************/ |
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0:01f31e923fe2 | 10144 | #define FLASH_SR_BSY_Pos (0U) |
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0:01f31e923fe2 | 10145 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 10146 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
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0:01f31e923fe2 | 10147 | #define FLASH_SR_PGERR_Pos (2U) |
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0:01f31e923fe2 | 10148 | #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 10149 | #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ |
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0:01f31e923fe2 | 10150 | #define FLASH_SR_WRPRTERR_Pos (4U) |
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0:01f31e923fe2 | 10151 | #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ |
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0:01f31e923fe2 | 10152 | #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ |
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0:01f31e923fe2 | 10153 | #define FLASH_SR_EOP_Pos (5U) |
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0:01f31e923fe2 | 10154 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ |
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0:01f31e923fe2 | 10155 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ |
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0:01f31e923fe2 | 10156 | |
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0:01f31e923fe2 | 10157 | /******************* Bit definition for FLASH_CR register *******************/ |
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0:01f31e923fe2 | 10158 | #define FLASH_CR_PG_Pos (0U) |
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0:01f31e923fe2 | 10159 | #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
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0:01f31e923fe2 | 10160 | #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ |
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0:01f31e923fe2 | 10161 | #define FLASH_CR_PER_Pos (1U) |
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0:01f31e923fe2 | 10162 | #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
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0:01f31e923fe2 | 10163 | #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ |
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0:01f31e923fe2 | 10164 | #define FLASH_CR_MER_Pos (2U) |
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0:01f31e923fe2 | 10165 | #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
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0:01f31e923fe2 | 10166 | #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ |
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0:01f31e923fe2 | 10167 | #define FLASH_CR_OPTPG_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10168 | #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10169 | #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10170 | #define FLASH_CR_OPTER_Pos (5U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10171 | #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10172 | #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10173 | #define FLASH_CR_STRT_Pos (6U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10174 | #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10175 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10176 | #define FLASH_CR_LOCK_Pos (7U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10177 | #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10178 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10179 | #define FLASH_CR_OPTWRE_Pos (9U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10180 | #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10181 | #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10182 | #define FLASH_CR_ERRIE_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10183 | #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10184 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10185 | #define FLASH_CR_EOPIE_Pos (12U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10186 | #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10187 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10188 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10189 | /******************* Bit definition for FLASH_AR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10190 | #define FLASH_AR_FAR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10191 | #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10192 | #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10193 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10194 | /****************** Bit definition for FLASH_OBR register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10195 | #define FLASH_OBR_OPTERR_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10196 | #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10197 | #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10198 | #define FLASH_OBR_RDPRT_Pos (1U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10199 | #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10200 | #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10201 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10202 | #define FLASH_OBR_IWDG_SW_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10203 | #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10204 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10205 | #define FLASH_OBR_nRST_STOP_Pos (3U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10206 | #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10207 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10208 | #define FLASH_OBR_nRST_STDBY_Pos (4U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10209 | #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10210 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10211 | #define FLASH_OBR_USER_Pos (2U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10212 | #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10213 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10214 | #define FLASH_OBR_DATA0_Pos (10U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10215 | #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10216 | #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10217 | #define FLASH_OBR_DATA1_Pos (18U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10218 | #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10219 | #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10220 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10221 | /****************** Bit definition for FLASH_WRPR register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10222 | #define FLASH_WRPR_WRP_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10223 | #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10224 | #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10225 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10226 | /*----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 10227 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10228 | /****************** Bit definition for FLASH_RDP register *******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10229 | #define FLASH_RDP_RDP_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10230 | #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10231 | #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10232 | #define FLASH_RDP_nRDP_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10233 | #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10234 | #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10235 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10236 | /****************** Bit definition for FLASH_USER register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10237 | #define FLASH_USER_USER_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10238 | #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10239 | #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10240 | #define FLASH_USER_nUSER_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10241 | #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10242 | #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10243 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10244 | /****************** Bit definition for FLASH_Data0 register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10245 | #define FLASH_DATA0_DATA0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10246 | #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10247 | #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10248 | #define FLASH_DATA0_nDATA0_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10249 | #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10250 | #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10251 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10252 | /****************** Bit definition for FLASH_Data1 register *****************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10253 | #define FLASH_DATA1_DATA1_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10254 | #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10255 | #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10256 | #define FLASH_DATA1_nDATA1_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10257 | #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10258 | #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10259 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10260 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10261 | #define FLASH_WRP0_WRP0_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10262 | #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10263 | #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10264 | #define FLASH_WRP0_nWRP0_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10265 | #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10266 | #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10267 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10268 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10269 | #define FLASH_WRP1_WRP1_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10270 | #define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10271 | #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10272 | #define FLASH_WRP1_nWRP1_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10273 | #define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10274 | #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10275 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10276 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10277 | #define FLASH_WRP2_WRP2_Pos (0U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10278 | #define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10279 | #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10280 | #define FLASH_WRP2_nWRP2_Pos (8U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10281 | #define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10282 | #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10283 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10284 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10285 | #define FLASH_WRP3_WRP3_Pos (16U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10286 | #define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10287 | #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10288 | #define FLASH_WRP3_nWRP3_Pos (24U) |
| Pawel Zarembski |
0:01f31e923fe2 | 10289 | #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10290 | #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10291 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10292 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10293 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10294 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 10295 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 10296 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10297 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10298 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 10299 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 10300 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10301 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10302 | /** @addtogroup Exported_macro |
| Pawel Zarembski |
0:01f31e923fe2 | 10303 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 10304 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10305 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10306 | /****************************** ADC Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10307 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10308 | ((INSTANCE) == ADC2)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10309 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10310 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| Pawel Zarembski |
0:01f31e923fe2 | 10311 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10312 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| Pawel Zarembski |
0:01f31e923fe2 | 10313 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10314 | #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| Pawel Zarembski |
0:01f31e923fe2 | 10315 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10316 | /****************************** CAN Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10317 | #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) |
| Pawel Zarembski |
0:01f31e923fe2 | 10318 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10319 | /****************************** CRC Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10320 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| Pawel Zarembski |
0:01f31e923fe2 | 10321 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10322 | /****************************** DAC Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10323 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10324 | /****************************** DMA Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10325 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10326 | ((INSTANCE) == DMA1_Channel2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10327 | ((INSTANCE) == DMA1_Channel3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10328 | ((INSTANCE) == DMA1_Channel4) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10329 | ((INSTANCE) == DMA1_Channel5) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10330 | ((INSTANCE) == DMA1_Channel6) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10331 | ((INSTANCE) == DMA1_Channel7)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10332 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10333 | /******************************* GPIO Instances *******************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10334 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10335 | ((INSTANCE) == GPIOB) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10336 | ((INSTANCE) == GPIOC) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10337 | ((INSTANCE) == GPIOD) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10338 | ((INSTANCE) == GPIOE)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10339 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10340 | /**************************** GPIO Alternate Function Instances ***************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10341 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| Pawel Zarembski |
0:01f31e923fe2 | 10342 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10343 | /**************************** GPIO Lock Instances *****************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10344 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| Pawel Zarembski |
0:01f31e923fe2 | 10345 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10346 | /******************************** I2C Instances *******************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10347 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10348 | ((INSTANCE) == I2C2)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10349 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10350 | /****************************** IWDG Instances ********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10351 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| Pawel Zarembski |
0:01f31e923fe2 | 10352 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10353 | /******************************** SPI Instances *******************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10354 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10355 | ((INSTANCE) == SPI2)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10356 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10357 | /****************************** START TIM Instances ***************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10358 | /****************************** TIM Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10359 | #define IS_TIM_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10360 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10361 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10362 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10363 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10364 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10365 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10366 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10367 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10368 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10369 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10370 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10371 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10372 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10373 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10374 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10375 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10376 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10377 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10378 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10379 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10380 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10381 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10382 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10383 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10384 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10385 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10386 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10387 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10388 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10389 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10390 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10391 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10392 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10393 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10394 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10395 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10396 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10397 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10398 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10399 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10400 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10401 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10402 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10403 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10404 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10405 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10406 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10407 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10408 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10409 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10410 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10411 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10412 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10413 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10414 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10415 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10416 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10417 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10418 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10419 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10420 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10421 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10422 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10423 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10424 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10425 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10426 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10427 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10428 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10429 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10430 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10431 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10432 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10433 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10434 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10435 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10436 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10437 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10438 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10439 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10440 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10441 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10442 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10443 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10444 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10445 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10446 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10447 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10448 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10449 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10450 | ((INSTANCE) == TIM1) |
| Pawel Zarembski |
0:01f31e923fe2 | 10451 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10452 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10453 | ((((INSTANCE) == TIM1) && \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10454 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10455 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10456 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10457 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10458 | || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10459 | (((INSTANCE) == TIM2) && \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10460 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10461 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10462 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10463 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10464 | || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10465 | (((INSTANCE) == TIM3) && \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10466 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10467 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10468 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10469 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10470 | || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10471 | (((INSTANCE) == TIM4) && \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10472 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10473 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10474 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10475 | ((CHANNEL) == TIM_CHANNEL_4)))) |
| Pawel Zarembski |
0:01f31e923fe2 | 10476 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10477 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10478 | (((INSTANCE) == TIM1) && \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10479 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10480 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10481 | ((CHANNEL) == TIM_CHANNEL_3))) |
| Pawel Zarembski |
0:01f31e923fe2 | 10482 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10483 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10484 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10485 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10486 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10487 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10488 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10489 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10490 | ((INSTANCE) == TIM1) |
| Pawel Zarembski |
0:01f31e923fe2 | 10491 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10492 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10493 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10494 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10495 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10496 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10497 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10498 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10499 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10500 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10501 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10502 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10503 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10504 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10505 | (((INSTANCE) == TIM1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10506 | ((INSTANCE) == TIM2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10507 | ((INSTANCE) == TIM3) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10508 | ((INSTANCE) == TIM4)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10509 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10510 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
| Pawel Zarembski |
0:01f31e923fe2 | 10511 | ((INSTANCE) == TIM1) |
| Pawel Zarembski |
0:01f31e923fe2 | 10512 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10513 | /****************************** END TIM Instances *****************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10514 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10515 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10516 | /******************** USART Instances : Synchronous mode **********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10517 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10518 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10519 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10520 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10521 | /******************** UART Instances : Asynchronous mode **********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10522 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10523 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10524 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10525 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10526 | /******************** UART Instances : Half-Duplex mode **********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10527 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10528 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10529 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10530 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10531 | /******************** UART Instances : LIN mode **********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10532 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10533 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10534 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10535 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10536 | /****************** UART Instances : Hardware Flow control ********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10537 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10538 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10539 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10540 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10541 | /********************* UART Instances : Smard card mode ***********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10542 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10543 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10544 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10545 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10546 | /*********************** UART Instances : IRDA mode ***************************/ |
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0:01f31e923fe2 | 10547 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
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0:01f31e923fe2 | 10548 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10549 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10550 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10551 | /***************** UART Instances : Multi-Processor mode **********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10552 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10553 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10554 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10555 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10556 | /***************** UART Instances : DMA mode available **********************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10557 | #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10558 | ((INSTANCE) == USART2) || \ |
| Pawel Zarembski |
0:01f31e923fe2 | 10559 | ((INSTANCE) == USART3)) |
| Pawel Zarembski |
0:01f31e923fe2 | 10560 | |
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0:01f31e923fe2 | 10561 | /****************************** RTC Instances *********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10562 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
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0:01f31e923fe2 | 10563 | |
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0:01f31e923fe2 | 10564 | /**************************** WWDG Instances *****************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10565 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
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0:01f31e923fe2 | 10566 | |
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0:01f31e923fe2 | 10567 | /****************************** USB Instances ********************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10568 | #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
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0:01f31e923fe2 | 10569 | |
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0:01f31e923fe2 | 10570 | |
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0:01f31e923fe2 | 10571 | |
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0:01f31e923fe2 | 10572 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10573 | /** |
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0:01f31e923fe2 | 10574 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 10575 | */ |
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0:01f31e923fe2 | 10576 | /******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 10577 | /* For a painless codes migration between the STM32F1xx device product */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10578 | /* lines, the aliases defined below are put in place to overcome the */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10579 | /* differences in the interrupt handlers and IRQn definitions. */ |
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0:01f31e923fe2 | 10580 | /* No need to update developed interrupt code when moving across */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10581 | /* product lines within the same STM32F1 Family */ |
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0:01f31e923fe2 | 10582 | /******************************************************************************/ |
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0:01f31e923fe2 | 10583 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10584 | /* Aliases for __IRQn */ |
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0:01f31e923fe2 | 10585 | #define ADC1_IRQn ADC1_2_IRQn |
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0:01f31e923fe2 | 10586 | #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn |
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0:01f31e923fe2 | 10587 | #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
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0:01f31e923fe2 | 10588 | #define TIM9_IRQn TIM1_BRK_IRQn |
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0:01f31e923fe2 | 10589 | #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
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0:01f31e923fe2 | 10590 | #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn |
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0:01f31e923fe2 | 10591 | #define TIM11_IRQn TIM1_TRG_COM_IRQn |
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0:01f31e923fe2 | 10592 | #define TIM10_IRQn TIM1_UP_IRQn |
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0:01f31e923fe2 | 10593 | #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn |
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0:01f31e923fe2 | 10594 | #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
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0:01f31e923fe2 | 10595 | #define CEC_IRQn USBWakeUp_IRQn |
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0:01f31e923fe2 | 10596 | #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn |
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0:01f31e923fe2 | 10597 | #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn |
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0:01f31e923fe2 | 10598 | #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn |
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0:01f31e923fe2 | 10599 | #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn |
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0:01f31e923fe2 | 10600 | #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn |
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0:01f31e923fe2 | 10601 | |
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0:01f31e923fe2 | 10602 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10603 | /* Aliases for __IRQHandler */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10604 | #define ADC1_IRQHandler ADC1_2_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10605 | #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10606 | #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10607 | #define TIM9_IRQHandler TIM1_BRK_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10608 | #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
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0:01f31e923fe2 | 10609 | #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10610 | #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10611 | #define TIM10_IRQHandler TIM1_UP_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10612 | #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler |
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0:01f31e923fe2 | 10613 | #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler |
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0:01f31e923fe2 | 10614 | #define CEC_IRQHandler USBWakeUp_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10615 | #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler |
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0:01f31e923fe2 | 10616 | #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10617 | #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10618 | #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler |
| Pawel Zarembski |
0:01f31e923fe2 | 10619 | #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler |
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0:01f31e923fe2 | 10620 | |
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0:01f31e923fe2 | 10621 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10622 | /** |
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0:01f31e923fe2 | 10623 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 10624 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10625 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10626 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 10627 | * @} |
| Pawel Zarembski |
0:01f31e923fe2 | 10628 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10629 | |
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0:01f31e923fe2 | 10630 | |
| Pawel Zarembski |
0:01f31e923fe2 | 10631 | #ifdef __cplusplus |
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0:01f31e923fe2 | 10632 | } |
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0:01f31e923fe2 | 10633 | #endif /* __cplusplus */ |
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0:01f31e923fe2 | 10634 | |
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0:01f31e923fe2 | 10635 | #endif /* __STM32F103xB_H */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10636 | |
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0:01f31e923fe2 | 10637 | |
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0:01f31e923fe2 | 10638 | |
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0:01f31e923fe2 | 10639 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |