Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nxp/lpc11u35/gpio.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file gpio.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include "LPC11Uxx.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "compiler.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "settings.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "iap.h"
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 static void busy_wait(uint32_t cycles)
Pawel Zarembski 0:01f31e923fe2 30 {
Pawel Zarembski 0:01f31e923fe2 31 volatile uint32_t i;
Pawel Zarembski 0:01f31e923fe2 32 i = cycles;
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 while (i > 0) {
Pawel Zarembski 0:01f31e923fe2 35 i--;
Pawel Zarembski 0:01f31e923fe2 36 }
Pawel Zarembski 0:01f31e923fe2 37 }
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 void gpio_init(void)
Pawel Zarembski 0:01f31e923fe2 40 {
Pawel Zarembski 0:01f31e923fe2 41 // enable clock for GPIO port 0
Pawel Zarembski 0:01f31e923fe2 42 LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 6);
Pawel Zarembski 0:01f31e923fe2 43 #if defined(TARGET_POWER_HOLD)
Pawel Zarembski 0:01f31e923fe2 44 // Target PowerHOLD port
Pawel Zarembski 0:01f31e923fe2 45 PIN_PWH_IOCON = PIN_PWH_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 46 LPC_GPIO->CLR[PIN_PWH_PORT] = PIN_PWH;
Pawel Zarembski 0:01f31e923fe2 47 LPC_GPIO->DIR[PIN_PWH_PORT] |= PIN_PWH;
Pawel Zarembski 0:01f31e923fe2 48 #endif
Pawel Zarembski 0:01f31e923fe2 49 // configure GPIO-LED as output
Pawel Zarembski 0:01f31e923fe2 50 #if defined(CONTROLLED_POWER_LED)
Pawel Zarembski 0:01f31e923fe2 51 // Power led (red)
Pawel Zarembski 0:01f31e923fe2 52 PIN_POW_LED_IOCON = PIN_POW_LED_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 53 LPC_GPIO->CLR[PIN_POW_LED_PORT] = PIN_POW_LED;
Pawel Zarembski 0:01f31e923fe2 54 LPC_GPIO->DIR[PIN_POW_LED_PORT] |= PIN_POW_LED;
Pawel Zarembski 0:01f31e923fe2 55 #endif
Pawel Zarembski 0:01f31e923fe2 56 // DAP led (green)
Pawel Zarembski 0:01f31e923fe2 57 PIN_DAP_LED_IOCON = PIN_DAP_LED_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 58 LPC_GPIO->SET[PIN_DAP_LED_PORT] = PIN_DAP_LED;
Pawel Zarembski 0:01f31e923fe2 59 LPC_GPIO->DIR[PIN_DAP_LED_PORT] |= PIN_DAP_LED;
Pawel Zarembski 0:01f31e923fe2 60 // MSD led (red)
Pawel Zarembski 0:01f31e923fe2 61 PIN_MSD_LED_IOCON = PIN_MSD_LED_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 62 LPC_GPIO->SET[PIN_MSD_LED_PORT] = PIN_MSD_LED;
Pawel Zarembski 0:01f31e923fe2 63 LPC_GPIO->DIR[PIN_MSD_LED_PORT] |= PIN_MSD_LED;
Pawel Zarembski 0:01f31e923fe2 64 // Serial LED (blue)
Pawel Zarembski 0:01f31e923fe2 65 PIN_CDC_LED_IOCON = PIN_CDC_LED_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 66 LPC_GPIO->SET[PIN_CDC_LED_PORT] = PIN_CDC_LED;
Pawel Zarembski 0:01f31e923fe2 67 LPC_GPIO->DIR[PIN_CDC_LED_PORT] |= PIN_CDC_LED;
Pawel Zarembski 0:01f31e923fe2 68 // configure Button(s) as input
Pawel Zarembski 0:01f31e923fe2 69 PIN_RESET_IN_IOCON = PIN_RESET_IN_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 70 LPC_GPIO->DIR[PIN_RESET_IN_PORT] &= ~PIN_RESET_IN;
Pawel Zarembski 0:01f31e923fe2 71 PIN_RESET_IN_FWRD_IOCON = PIN_RESET_IN_FWRD_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 72 LPC_GPIO->DIR[PIN_RESET_IN_FWRD_PORT] &= ~PIN_RESET_IN_FWRD;
Pawel Zarembski 0:01f31e923fe2 73 #if !defined(PIN_nRESET_FET_DRIVE)
Pawel Zarembski 0:01f31e923fe2 74 // open drain logic for reset button
Pawel Zarembski 0:01f31e923fe2 75 PIN_nRESET_IOCON = PIN_nRESET_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 76 LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 77 LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 78 #else
Pawel Zarembski 0:01f31e923fe2 79 // FET drive logic for reset button
Pawel Zarembski 0:01f31e923fe2 80 PIN_nRESET_IOCON = PIN_nRESET_IOCON_INIT;
Pawel Zarembski 0:01f31e923fe2 81 LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 82 LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 83 #endif
Pawel Zarembski 0:01f31e923fe2 84 /* Enable AHB clock to the FlexInt, GroupedInt domain. */
Pawel Zarembski 0:01f31e923fe2 85 LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 23) | (1 << 24));
Pawel Zarembski 0:01f31e923fe2 86 // Give the cap on the reset button time to charge
Pawel Zarembski 0:01f31e923fe2 87 busy_wait(10000);
Pawel Zarembski 0:01f31e923fe2 88
Pawel Zarembski 0:01f31e923fe2 89 if (gpio_get_reset_btn() || config_ram_get_initial_hold_in_bl()) {
Pawel Zarembski 0:01f31e923fe2 90 IRQn_Type irq;
Pawel Zarembski 0:01f31e923fe2 91 // Disable SYSTICK timer and interrupt before calling into ISP
Pawel Zarembski 0:01f31e923fe2 92 SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 // Disable all nvic interrupts
Pawel Zarembski 0:01f31e923fe2 95 for (irq = (IRQn_Type)0; irq < (IRQn_Type)32; irq++) {
Pawel Zarembski 0:01f31e923fe2 96 NVIC_DisableIRQ(irq);
Pawel Zarembski 0:01f31e923fe2 97 NVIC_ClearPendingIRQ(irq);
Pawel Zarembski 0:01f31e923fe2 98 }
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 // If switching to "bootloader" mode then setup the watchdog
Pawel Zarembski 0:01f31e923fe2 101 // so it will exit CRP mode after ~30 seconds
Pawel Zarembski 0:01f31e923fe2 102 if (config_ram_get_initial_hold_in_bl()) {
Pawel Zarembski 0:01f31e923fe2 103 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 15); // Enable watchdog module
Pawel Zarembski 0:01f31e923fe2 104 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); // Enable watchdog clock (WDOSC)
Pawel Zarembski 0:01f31e923fe2 105 LPC_SYSCON->WDTOSCCTRL = (0xF << 5); // Set max frequency - 2.3MHz
Pawel Zarembski 0:01f31e923fe2 106 LPC_WWDT->CLKSEL = (1 << 0); // Select watchdog clock
Pawel Zarembski 0:01f31e923fe2 107 LPC_WWDT->TC = 0x00FFFFFF; // Set time to reset to ~29s
Pawel Zarembski 0:01f31e923fe2 108 LPC_WWDT->MOD = (1 << 0) | (1 << 1); // Enable watchdog and set reset
Pawel Zarembski 0:01f31e923fe2 109 LPC_WWDT->FEED = 0xAA; // Enable watchdog
Pawel Zarembski 0:01f31e923fe2 110 LPC_WWDT->FEED = 0x55;
Pawel Zarembski 0:01f31e923fe2 111 }
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 iap_reinvoke();
Pawel Zarembski 0:01f31e923fe2 114 }
Pawel Zarembski 0:01f31e923fe2 115 }
Pawel Zarembski 0:01f31e923fe2 116
Pawel Zarembski 0:01f31e923fe2 117 void gpio_set_hid_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 118 {
Pawel Zarembski 0:01f31e923fe2 119 if (state) {
Pawel Zarembski 0:01f31e923fe2 120 LPC_GPIO->CLR[PIN_DAP_LED_PORT] = PIN_DAP_LED;
Pawel Zarembski 0:01f31e923fe2 121 } else {
Pawel Zarembski 0:01f31e923fe2 122 LPC_GPIO->SET[PIN_DAP_LED_PORT] = PIN_DAP_LED;
Pawel Zarembski 0:01f31e923fe2 123 }
Pawel Zarembski 0:01f31e923fe2 124 }
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126 void gpio_set_cdc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 127 {
Pawel Zarembski 0:01f31e923fe2 128 if (state) {
Pawel Zarembski 0:01f31e923fe2 129 LPC_GPIO->CLR[PIN_CDC_LED_PORT] = PIN_CDC_LED;
Pawel Zarembski 0:01f31e923fe2 130 } else {
Pawel Zarembski 0:01f31e923fe2 131 LPC_GPIO->SET[PIN_CDC_LED_PORT] = PIN_CDC_LED;
Pawel Zarembski 0:01f31e923fe2 132 }
Pawel Zarembski 0:01f31e923fe2 133 }
Pawel Zarembski 0:01f31e923fe2 134
Pawel Zarembski 0:01f31e923fe2 135 void gpio_set_msc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 136 {
Pawel Zarembski 0:01f31e923fe2 137 if (state) {
Pawel Zarembski 0:01f31e923fe2 138 LPC_GPIO->CLR[PIN_MSD_LED_PORT] = PIN_MSD_LED;
Pawel Zarembski 0:01f31e923fe2 139 } else {
Pawel Zarembski 0:01f31e923fe2 140 LPC_GPIO->SET[PIN_MSD_LED_PORT] = PIN_MSD_LED;
Pawel Zarembski 0:01f31e923fe2 141 }
Pawel Zarembski 0:01f31e923fe2 142 }
Pawel Zarembski 0:01f31e923fe2 143
Pawel Zarembski 0:01f31e923fe2 144 uint8_t gpio_get_reset_btn_no_fwrd()
Pawel Zarembski 0:01f31e923fe2 145 {
Pawel Zarembski 0:01f31e923fe2 146 return LPC_GPIO->PIN[PIN_RESET_IN_PORT] & PIN_RESET_IN ? 0 : 1;
Pawel Zarembski 0:01f31e923fe2 147 }
Pawel Zarembski 0:01f31e923fe2 148
Pawel Zarembski 0:01f31e923fe2 149 uint8_t gpio_get_reset_btn_fwrd()
Pawel Zarembski 0:01f31e923fe2 150 {
Pawel Zarembski 0:01f31e923fe2 151 return LPC_GPIO->PIN[PIN_RESET_IN_FWRD_PORT] & PIN_RESET_IN_FWRD ? 0 : 1;
Pawel Zarembski 0:01f31e923fe2 152 }
Pawel Zarembski 0:01f31e923fe2 153
Pawel Zarembski 0:01f31e923fe2 154 void gpio_set_board_power(bool powerEnabled)
Pawel Zarembski 0:01f31e923fe2 155 {
Pawel Zarembski 0:01f31e923fe2 156 }