Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/flc_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* **************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, Maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | *************************************************************************** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /* Define to prevent redundant inclusion */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | #ifndef _MXC_FLC_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | #define _MXC_FLC_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | /* **** Includes **** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #include <stdint.h> |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | #ifdef __cplusplus |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | extern "C" { |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | /// @cond |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | If types are not defined elsewhere (CMSIS) define them here |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | #ifndef __IO |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | #define __IO volatile |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | #ifndef __I |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | #define __I volatile const |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | #ifndef __O |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define __O volatile |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | #ifndef __R |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | #define __R volatile const |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | /// @endcond |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | /* **** Definitions **** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | * @defgroup flc_special_codes Flash Controller Codes/Keys. |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | * @brief Required values to pass to the flash controller to perform restricted |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | * operations. |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */ |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | /**@} end of flc_special_codes */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | * @defgroup flc_registers Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | * @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module. |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | * @ingroup flc |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | access to each register in module. |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | * Structure type to access the Flash Controller registers with direct 32-bit |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | access to each. |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | __IO uint32_t faddr; /**< <tt>\b 0x0000: </tt> FLC_FADDR Register - Flash Operation Address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | __IO uint32_t fckdiv; /**< <tt>\b 0x0004: </tt> FLC_FCKDIV Register - Flash Clock Pulse Divisor */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | __IO uint32_t ctrl; /**< <tt>\b 0x0008: </tt> FLC_CTRL Register - Flash Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | __R uint32_t rsv00C[6]; /**< <tt>\b 0x000C-0x0020:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | __IO uint32_t intr; /**< <tt>\b 0x0024: </tt> FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | __R uint32_t rsv028[2]; /**< <tt>\b 0x0028-0x002C:</tt> RESERVED */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | __IO uint32_t fdata; /**< <tt>\b 0x0030: </tt> FLC_FDATA Register - Flash Operation Data Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | __R uint32_t rsv034[7]; /**< <tt>\b 0x0034-0x004C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | __IO uint32_t perform; /**< <tt>\b 0x0050: </tt> FLC_PERFORM Register - Flash Performance Settings */ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | __IO uint32_t tacc; /**< <tt>\b 0x0054: </tt> FLC_TACC Register - Flash Read Cycle Config */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | __IO uint32_t tprog; /**< <tt>\b 0x0058: </tt> FLC_TPROG Register - Flash Write Cycle Config */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | __R uint32_t rsv05C[9]; /**< <tt>\b 0x005C-0x007C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | __IO uint32_t status; /**< <tt>\b 0x0080: </tt> FLC_STATUS Register - Security Status Flags */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | __R uint32_t rsv084; /**< <tt>\b 0x0084: </tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | __IO uint32_t security; /**< <tt>\b 0x0088: </tt> FLC_SECURITY Register - Flash Controller Security Settings */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | __R uint32_t rsv08C[4]; /**< <tt>\b 0x008C-0x0098:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | __IO uint32_t bypass; /**< <tt>\b 0x009C: </tt> FLC_BYPASS Register - Status Flags for DSB Operations */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | __R uint32_t rsv0A0[24]; /**< <tt>\b 0x00A0-0x00FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | __IO uint32_t user_option; /**< <tt>\b 0x0100: </tt> FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | __R uint32_t rsv104[15]; /**< <tt>\b 0x0104-0x013C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | __IO uint32_t ctrl2; /**< <tt>\b 0x0140: </tt> FLC_CTRL2 Register - Flash Control Register 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | __IO uint32_t intfl1; /**< <tt>\b 0x0144: </tt> FLC_INTFL1 Register - Interrupt Flags Register 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | __IO uint32_t inten1; /**< <tt>\b 0x0148: </tt> FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | __R uint32_t rsv14C[9]; /**< <tt>\b 0x014C-0x016C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | __IO uint32_t bl_ctrl; /**< <tt>\b 0x0170: </tt> FLC_BL_CTRL Register - Bootloader Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | __IO uint32_t twk; /**< <tt>\b 0x0174: </tt> FLC_TWK Register - PDM33 Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | __R uint32_t rsv178; /**< <tt>\b 0x0178: </tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | __IO uint32_t slm; /**< <tt>\b 0x017C: </tt> FLC_SLM Register - Sleep Mode Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | __R uint32_t rsv180[32]; /**< <tt>\b 0x0180-0x01FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | __IO uint32_t disable_xr0; /**< <tt>\b 0x0200: </tt> FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | __IO uint32_t disable_xr1; /**< <tt>\b 0x0204: </tt> FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | __IO uint32_t disable_xr2; /**< <tt>\b 0x0208: </tt> FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | __IO uint32_t disable_xr3; /**< <tt>\b 0x020C: </tt> FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | __IO uint32_t disable_xr4; /**< <tt>\b 0x0210: </tt> FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | __IO uint32_t disable_xr5; /**< <tt>\b 0x0214: </tt> FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | __IO uint32_t disable_xr6; /**< <tt>\b 0x0218: </tt> FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | __IO uint32_t disable_xr7; /**< <tt>\b 0x021C: </tt> FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | __R uint32_t rsv220[56]; /**< <tt>\b 0x0220-0x02FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | __IO uint32_t disable_we0; /**< <tt>\b 0x0300: </tt> FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | __IO uint32_t disable_we1; /**< <tt>\b 0x0304: </tt> FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | __IO uint32_t disable_we2; /**< <tt>\b 0x0308: </tt> FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | __IO uint32_t disable_we3; /**< <tt>\b 0x030C: </tt> FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | __IO uint32_t disable_we4; /**< <tt>\b 0x0310: </tt> FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | __IO uint32_t disable_we5; /**< <tt>\b 0x0314: </tt> FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | __IO uint32_t disable_we6; /**< <tt>\b 0x0318: </tt> FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | __IO uint32_t disable_we7; /**< <tt>\b 0x031C: </tt> FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | } mxc_flc_regs_t; |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | /**@} end of group flc_registers */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | Register offsets for module FLC. |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | * @defgroup FLC_Register_Offsets Register Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | * @brief Flash Controller Register Offsets from the FLC Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>\b 0x0000</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>\b 0x0004</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>\b 0x0008</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>\b 0x0024</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>\b 0x0030</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: <tt>\b 0x0050</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: <tt>\b 0x0054</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: <tt>\b 0x0058</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt>\b 0x0080</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt>\b 0x0088</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt>\b 0x009C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: <tt>\b 0x0100</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: <tt>\b 0x0140</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: <tt>\b 0x0144</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: <tt>\b 0x0148</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: <tt>\b 0x0170</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: <tt>\b 0x0174</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: <tt>\b 0x017C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: <tt>\b 0x0200</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: <tt>\b 0x0204</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: <tt>\b 0x0208</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: <tt>\b 0x020C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: <tt>\b 0x0210</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: <tt>\b 0x0214</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: <tt>\b 0x0218</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: <tt>\b 0x021C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: <tt>\b 0x0300</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: <tt>\b 0x0304</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: <tt>\b 0x0308</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: <tt>\b 0x030C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: <tt>\b 0x0310</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: <tt>\b 0x0314</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: <tt>\b 0x0318</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: <tt>\b 0x031C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | /**@} end of group FLC_Register_Offsets */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | Field positions and Masks for module FLC. |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | * @defgroup FLC_FADDR_Register FLC_FADDR |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | * @brief Field Positions and Bit Masks for the FLC_FADDR register. |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | /**@} end of group FLC_FADDR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | * @defgroup FLC_FCKDIV_Register FLC_FCKDIV |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | * @brief Field Positions and Bit Masks for the FLC_FCKDIV register. |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | /**@} end of group FLC_FCKDIV */ |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | * @defgroup FLC_CTRL_Register FLC_CTRL |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | * @brief Field Positions and Bit Masks for the FLC_CTRL register. |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | /**@} end of group FLC_CTRL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | * @defgroup FLC_INTR_Register FLC_INTR |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | * @brief Field Positions and Bit Masks for the FLC_INTR register. |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | #define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | #define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | #define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | #define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | #define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | #define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | #define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | #define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | /**@} end of group FLC_INTR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | * @defgroup FLC_PERFORM_Register FLC_PERFORM |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | * @brief Field Positions and Bit Masks for the FLC_PERFORM register. |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | #define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | #define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | /**@} end of group FLC_PERFORM */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | * @defgroup FLC_STATUS_Register FLC_STATUS |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | * @brief Field Positions and Bit Masks for the FLC_STATUS register. |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | /**@} end of group FLC_STATUS*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | * @defgroup FLC_SECURITY_Register FLC_SECURITY |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | * @brief Field Positions and Bit Masks for the FLC_SECURITY register. |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 298 | #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 301 | #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | /**@} end of group FLC_SECURITY */ |
| Pawel Zarembski |
0:01f31e923fe2 | 308 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 309 | * @defgroup FLC_BYPASS_Register FLC_BYPASS |
| Pawel Zarembski |
0:01f31e923fe2 | 310 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 311 | * @brief Field Positions and Bit Masks for the FLC_BYPASS register. |
| Pawel Zarembski |
0:01f31e923fe2 | 312 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 313 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 314 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 315 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 316 | #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 317 | #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 318 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 319 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 320 | #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 321 | #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 322 | /**@} end of group FLC_BYPASS*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 323 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 324 | * @defgroup FLC_CTRL2_Register FLC_CTRL2 |
| Pawel Zarembski |
0:01f31e923fe2 | 325 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 326 | * @brief Field Positions and Bit Masks for the FLC_CTRL2 register. |
| Pawel Zarembski |
0:01f31e923fe2 | 327 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 328 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 329 | #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 330 | #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 331 | #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 332 | #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 333 | #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 334 | #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 335 | #define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 336 | #define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 337 | #define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 338 | #define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 339 | #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 340 | #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 341 | #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 342 | #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 343 | /**@} end of group FLC_CTRL2*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 344 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 345 | * @defgroup FLC_INTFL1_Register FLC_INTFL1 |
| Pawel Zarembski |
0:01f31e923fe2 | 346 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 347 | * @brief Field Positions and Bit Masks for the FLC_INTFL1 register. |
| Pawel Zarembski |
0:01f31e923fe2 | 348 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 349 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 350 | #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 351 | #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 352 | #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 353 | #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 354 | #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 355 | #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 356 | #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 357 | #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 358 | #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 359 | #define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 360 | #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 361 | #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 362 | /**@} end of group FLC_INTFL1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 363 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 364 | * @defgroup FLC_INTEN1_Register FLC_INTEN1 |
| Pawel Zarembski |
0:01f31e923fe2 | 365 | * @ingroup flc_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 366 | * @brief Field Positions and Bit Masks for the FLC_INTEN1 register. |
| Pawel Zarembski |
0:01f31e923fe2 | 367 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 368 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 369 | #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 370 | #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 371 | #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 372 | #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 373 | #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 374 | #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 375 | #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 376 | #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 377 | #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 378 | #define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 379 | #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 380 | #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 381 | /**@} end of group FLC_INTEN1*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 382 | |
| Pawel Zarembski |
0:01f31e923fe2 | 383 | #ifdef __cplusplus |
| Pawel Zarembski |
0:01f31e923fe2 | 384 | } |
| Pawel Zarembski |
0:01f31e923fe2 | 385 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 386 | |
| Pawel Zarembski |
0:01f31e923fe2 | 387 | #endif /* _MXC_FLC_REGS_H_ */ |