Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32620/uart.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* CMSIS-DAP Interface Firmware
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2009-2013 ARM Limited
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Licensed under the Apache License, Version 2.0 (the "License");
Pawel Zarembski 0:01f31e923fe2 5 * you may not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 6 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 11 * distributed under the License is distributed on an "AS IS" BASIS,
Pawel Zarembski 0:01f31e923fe2 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 13 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 14 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 15 */
Pawel Zarembski 0:01f31e923fe2 16
Pawel Zarembski 0:01f31e923fe2 17 #include <string.h>
Pawel Zarembski 0:01f31e923fe2 18 #include "max32620.h"
Pawel Zarembski 0:01f31e923fe2 19 #include "clkman_regs.h"
Pawel Zarembski 0:01f31e923fe2 20 #include "ioman_regs.h"
Pawel Zarembski 0:01f31e923fe2 21 #include "gpio_regs.h"
Pawel Zarembski 0:01f31e923fe2 22 #include "uart_regs.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "uart.h"
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 // Size must be 2^n
Pawel Zarembski 0:01f31e923fe2 26 #define BUFFER_SIZE (4096)
Pawel Zarembski 0:01f31e923fe2 27
Pawel Zarembski 0:01f31e923fe2 28 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
Pawel Zarembski 0:01f31e923fe2 29 MXC_F_UART_INTFL_RX_PARITY_ERR | \
Pawel Zarembski 0:01f31e923fe2 30 MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 // Track bit rate to avoid calculation from bus clock, clock scaler and baud divisor values
Pawel Zarembski 0:01f31e923fe2 34 static uint32_t baudrate;
Pawel Zarembski 0:01f31e923fe2 35
Pawel Zarembski 0:01f31e923fe2 36 static mxc_uart_regs_t *CdcAcmUart = MXC_UART0;
Pawel Zarembski 0:01f31e923fe2 37 static mxc_uart_fifo_regs_t *CdcAcmUartFifo = MXC_UART0_FIFO;
Pawel Zarembski 0:01f31e923fe2 38 static const IRQn_Type CdcAcmUartIrqNumber = UART0_IRQn;
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 static struct {
Pawel Zarembski 0:01f31e923fe2 42 uint8_t data[BUFFER_SIZE];
Pawel Zarembski 0:01f31e923fe2 43 volatile uint16_t idx_in;
Pawel Zarembski 0:01f31e923fe2 44 volatile uint16_t idx_out;
Pawel Zarembski 0:01f31e923fe2 45 volatile int16_t cnt_in;
Pawel Zarembski 0:01f31e923fe2 46 volatile int16_t cnt_out;
Pawel Zarembski 0:01f31e923fe2 47 } write_buffer, read_buffer;
Pawel Zarembski 0:01f31e923fe2 48
Pawel Zarembski 0:01f31e923fe2 49 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 50 static void set_bitrate(uint32_t bps)
Pawel Zarembski 0:01f31e923fe2 51 {
Pawel Zarembski 0:01f31e923fe2 52 uint32_t baud_divisor;
Pawel Zarembski 0:01f31e923fe2 53
Pawel Zarembski 0:01f31e923fe2 54 baud_divisor = SystemCoreClock / (1 << (MXC_CLKMAN->sys_clk_ctrl_8_uart - 1));
Pawel Zarembski 0:01f31e923fe2 55 baud_divisor /= (bps * 16);
Pawel Zarembski 0:01f31e923fe2 56 CdcAcmUart->baud = baud_divisor;
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 baudrate = bps;
Pawel Zarembski 0:01f31e923fe2 59 }
Pawel Zarembski 0:01f31e923fe2 60
Pawel Zarembski 0:01f31e923fe2 61 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 62 int32_t uart_initialize(void)
Pawel Zarembski 0:01f31e923fe2 63 {
Pawel Zarembski 0:01f31e923fe2 64 if (MXC_CLKMAN->sys_clk_ctrl_8_uart != MXC_S_CLKMAN_CLK_SCALE_DIV_4) {
Pawel Zarembski 0:01f31e923fe2 65 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
Pawel Zarembski 0:01f31e923fe2 66 }
Pawel Zarembski 0:01f31e923fe2 67 // Configure GPIO for UART
Pawel Zarembski 0:01f31e923fe2 68 MXC_IOMAN->uart0_req = ((0 << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ);
Pawel Zarembski 0:01f31e923fe2 69 while (MXC_IOMAN->uart0_ack != ((0 << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ));
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 // Disable TX and RX fifos
Pawel Zarembski 0:01f31e923fe2 72 CdcAcmUart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 // Disable interrupts
Pawel Zarembski 0:01f31e923fe2 75 CdcAcmUart->inten = 0;
Pawel Zarembski 0:01f31e923fe2 76 CdcAcmUart->intfl = CdcAcmUart->intfl;
Pawel Zarembski 0:01f31e923fe2 77
Pawel Zarembski 0:01f31e923fe2 78 // Set the parity, size, stop and flow configuration
Pawel Zarembski 0:01f31e923fe2 79 CdcAcmUart->ctrl |= (MXC_S_UART_CTRL_DATA_SIZE_8_BITS | MXC_S_UART_CTRL_PARITY_DISABLE);
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 // Set receive fifo threshold to 0
Pawel Zarembski 0:01f31e923fe2 82 CdcAcmUart->rx_fifo_ctrl &= ~MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL;
Pawel Zarembski 0:01f31e923fe2 83 CdcAcmUart->rx_fifo_ctrl |= (0 << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 // Enable TX and RX fifos
Pawel Zarembski 0:01f31e923fe2 86 CdcAcmUart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
Pawel Zarembski 0:01f31e923fe2 87
Pawel Zarembski 0:01f31e923fe2 88 NVIC_EnableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 89
Pawel Zarembski 0:01f31e923fe2 90 // Set transmit almost empty level to three-quarters of the fifo size
Pawel Zarembski 0:01f31e923fe2 91 CdcAcmUart->tx_fifo_ctrl &= ~MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL;
Pawel Zarembski 0:01f31e923fe2 92 CdcAcmUart->tx_fifo_ctrl |= (MXC_UART_FIFO_DEPTH - (MXC_UART_FIFO_DEPTH >> 2)) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS;
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 // Enable TX and RX interrupts
Pawel Zarembski 0:01f31e923fe2 95 CdcAcmUart->inten = (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | MXC_F_UART_INTFL_RX_FIFO_OVERFLOW | MXC_F_UART_INTEN_TX_FIFO_AE);
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 // Enable UART
Pawel Zarembski 0:01f31e923fe2 98 CdcAcmUart->ctrl |= MXC_F_UART_CTRL_UART_EN;
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 return 1;
Pawel Zarembski 0:01f31e923fe2 101 }
Pawel Zarembski 0:01f31e923fe2 102
Pawel Zarembski 0:01f31e923fe2 103 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 104 int32_t uart_uninitialize(void)
Pawel Zarembski 0:01f31e923fe2 105 {
Pawel Zarembski 0:01f31e923fe2 106 // Disable UART
Pawel Zarembski 0:01f31e923fe2 107 CdcAcmUart->ctrl &= ~MXC_F_UART_CTRL_UART_EN;
Pawel Zarembski 0:01f31e923fe2 108
Pawel Zarembski 0:01f31e923fe2 109 // Disable interrupts
Pawel Zarembski 0:01f31e923fe2 110 CdcAcmUart->inten = 0;
Pawel Zarembski 0:01f31e923fe2 111 NVIC_DisableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 // Clear buffers
Pawel Zarembski 0:01f31e923fe2 114 memset(&write_buffer, 0, sizeof(write_buffer));
Pawel Zarembski 0:01f31e923fe2 115 memset(&read_buffer, 0, sizeof(read_buffer));
Pawel Zarembski 0:01f31e923fe2 116
Pawel Zarembski 0:01f31e923fe2 117 return 1;
Pawel Zarembski 0:01f31e923fe2 118 }
Pawel Zarembski 0:01f31e923fe2 119
Pawel Zarembski 0:01f31e923fe2 120 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 121 void uart_set_control_line_state(uint16_t ctrl_bmp)
Pawel Zarembski 0:01f31e923fe2 122 {
Pawel Zarembski 0:01f31e923fe2 123 }
Pawel Zarembski 0:01f31e923fe2 124
Pawel Zarembski 0:01f31e923fe2 125 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 126 int32_t uart_reset(void)
Pawel Zarembski 0:01f31e923fe2 127 {
Pawel Zarembski 0:01f31e923fe2 128 // Clear buffers
Pawel Zarembski 0:01f31e923fe2 129 memset(&write_buffer, 0, sizeof(write_buffer));
Pawel Zarembski 0:01f31e923fe2 130 memset(&read_buffer, 0, sizeof(read_buffer));
Pawel Zarembski 0:01f31e923fe2 131
Pawel Zarembski 0:01f31e923fe2 132 return 1;
Pawel Zarembski 0:01f31e923fe2 133 }
Pawel Zarembski 0:01f31e923fe2 134
Pawel Zarembski 0:01f31e923fe2 135 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 136 int32_t uart_set_configuration(UART_Configuration *config)
Pawel Zarembski 0:01f31e923fe2 137 {
Pawel Zarembski 0:01f31e923fe2 138 uint32_t ctrl;
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140 // Get current configuration; clearing parameters that may be configured here
Pawel Zarembski 0:01f31e923fe2 141 ctrl = CdcAcmUart->ctrl & ~(MXC_F_UART_CTRL_PARITY |
Pawel Zarembski 0:01f31e923fe2 142 MXC_F_UART_CTRL_DATA_SIZE |
Pawel Zarembski 0:01f31e923fe2 143 MXC_F_UART_CTRL_EXTRA_STOP |
Pawel Zarembski 0:01f31e923fe2 144 MXC_F_UART_CTRL_CTS_EN |
Pawel Zarembski 0:01f31e923fe2 145 MXC_F_UART_CTRL_RTS_EN);
Pawel Zarembski 0:01f31e923fe2 146
Pawel Zarembski 0:01f31e923fe2 147 switch (config->Parity) {
Pawel Zarembski 0:01f31e923fe2 148 case UART_PARITY_NONE: break;
Pawel Zarembski 0:01f31e923fe2 149 case UART_PARITY_ODD: ctrl |= MXC_S_UART_CTRL_PARITY_ODD;
Pawel Zarembski 0:01f31e923fe2 150 case UART_PARITY_EVEN: ctrl |= MXC_S_UART_CTRL_PARITY_EVEN;
Pawel Zarembski 0:01f31e923fe2 151 case UART_PARITY_MARK: return 0;
Pawel Zarembski 0:01f31e923fe2 152 case UART_PARITY_SPACE: return 0;
Pawel Zarembski 0:01f31e923fe2 153 }
Pawel Zarembski 0:01f31e923fe2 154
Pawel Zarembski 0:01f31e923fe2 155 switch (config->DataBits) {
Pawel Zarembski 0:01f31e923fe2 156 case UART_DATA_BITS_5: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_5_BITS; break;
Pawel Zarembski 0:01f31e923fe2 157 case UART_DATA_BITS_6: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_6_BITS; break;
Pawel Zarembski 0:01f31e923fe2 158 case UART_DATA_BITS_7: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_7_BITS; break;
Pawel Zarembski 0:01f31e923fe2 159 case UART_DATA_BITS_8: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_8_BITS; break;
Pawel Zarembski 0:01f31e923fe2 160 case UART_DATA_BITS_16: return 0;
Pawel Zarembski 0:01f31e923fe2 161 }
Pawel Zarembski 0:01f31e923fe2 162
Pawel Zarembski 0:01f31e923fe2 163 switch (config->StopBits) {
Pawel Zarembski 0:01f31e923fe2 164 case UART_STOP_BITS_1: break;
Pawel Zarembski 0:01f31e923fe2 165 case UART_STOP_BITS_1_5:
Pawel Zarembski 0:01f31e923fe2 166 case UART_STOP_BITS_2: ctrl |= MXC_F_UART_CTRL_EXTRA_STOP; break;
Pawel Zarembski 0:01f31e923fe2 167 }
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 switch (config->FlowControl) {
Pawel Zarembski 0:01f31e923fe2 170 case UART_FLOW_CONTROL_NONE: break;
Pawel Zarembski 0:01f31e923fe2 171 case UART_FLOW_CONTROL_RTS_CTS: return 0;
Pawel Zarembski 0:01f31e923fe2 172 case UART_FLOW_CONTROL_XON_XOFF: return 0;
Pawel Zarembski 0:01f31e923fe2 173 }
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 set_bitrate(config->Baudrate);
Pawel Zarembski 0:01f31e923fe2 176
Pawel Zarembski 0:01f31e923fe2 177 // Set the new configuration
Pawel Zarembski 0:01f31e923fe2 178 CdcAcmUart->ctrl = ctrl;
Pawel Zarembski 0:01f31e923fe2 179
Pawel Zarembski 0:01f31e923fe2 180 return 1;
Pawel Zarembski 0:01f31e923fe2 181 }
Pawel Zarembski 0:01f31e923fe2 182
Pawel Zarembski 0:01f31e923fe2 183 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 184 int32_t uart_get_configuration(UART_Configuration *config)
Pawel Zarembski 0:01f31e923fe2 185 {
Pawel Zarembski 0:01f31e923fe2 186 uint32_t ctrl;
Pawel Zarembski 0:01f31e923fe2 187
Pawel Zarembski 0:01f31e923fe2 188 // Capture current configuration
Pawel Zarembski 0:01f31e923fe2 189 ctrl = CdcAcmUart->ctrl;
Pawel Zarembski 0:01f31e923fe2 190
Pawel Zarembski 0:01f31e923fe2 191 if (!(ctrl & MXC_S_UART_CTRL_PARITY_DISABLE)) {
Pawel Zarembski 0:01f31e923fe2 192 config->Parity = UART_PARITY_NONE;
Pawel Zarembski 0:01f31e923fe2 193 } else if (ctrl & MXC_S_UART_CTRL_PARITY_ODD) {
Pawel Zarembski 0:01f31e923fe2 194 config->Parity = UART_PARITY_ODD;
Pawel Zarembski 0:01f31e923fe2 195 } else {
Pawel Zarembski 0:01f31e923fe2 196 // Note both EVEN and MARK parity are captured here
Pawel Zarembski 0:01f31e923fe2 197 config->Parity = UART_PARITY_EVEN;
Pawel Zarembski 0:01f31e923fe2 198 }
Pawel Zarembski 0:01f31e923fe2 199
Pawel Zarembski 0:01f31e923fe2 200 switch (ctrl & MXC_F_UART_CTRL_DATA_SIZE) {
Pawel Zarembski 0:01f31e923fe2 201 case MXC_S_UART_CTRL_DATA_SIZE_5_BITS: config->DataBits = UART_DATA_BITS_5; break;
Pawel Zarembski 0:01f31e923fe2 202 case MXC_S_UART_CTRL_DATA_SIZE_6_BITS: config->DataBits = UART_DATA_BITS_6; break;
Pawel Zarembski 0:01f31e923fe2 203 case MXC_S_UART_CTRL_DATA_SIZE_7_BITS: config->DataBits = UART_DATA_BITS_7; break;
Pawel Zarembski 0:01f31e923fe2 204 case MXC_S_UART_CTRL_DATA_SIZE_8_BITS: config->DataBits = UART_DATA_BITS_8; break;
Pawel Zarembski 0:01f31e923fe2 205 }
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207 if (!(ctrl & MXC_F_UART_CTRL_EXTRA_STOP)) {
Pawel Zarembski 0:01f31e923fe2 208 config->StopBits = UART_STOP_BITS_1;
Pawel Zarembski 0:01f31e923fe2 209 } else {
Pawel Zarembski 0:01f31e923fe2 210 config->StopBits = UART_STOP_BITS_2;
Pawel Zarembski 0:01f31e923fe2 211 }
Pawel Zarembski 0:01f31e923fe2 212
Pawel Zarembski 0:01f31e923fe2 213 if ((ctrl & (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) == (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) {
Pawel Zarembski 0:01f31e923fe2 214 config->FlowControl = UART_FLOW_CONTROL_RTS_CTS;
Pawel Zarembski 0:01f31e923fe2 215 } else {
Pawel Zarembski 0:01f31e923fe2 216 // Not true if only one of ...CST_EN and ...RTS_EN are asserted
Pawel Zarembski 0:01f31e923fe2 217 config->FlowControl = UART_FLOW_CONTROL_NONE;
Pawel Zarembski 0:01f31e923fe2 218 }
Pawel Zarembski 0:01f31e923fe2 219
Pawel Zarembski 0:01f31e923fe2 220 config->Baudrate = baudrate;
Pawel Zarembski 0:01f31e923fe2 221
Pawel Zarembski 0:01f31e923fe2 222 return 1;
Pawel Zarembski 0:01f31e923fe2 223 }
Pawel Zarembski 0:01f31e923fe2 224
Pawel Zarembski 0:01f31e923fe2 225 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 226 int32_t uart_write_free(void)
Pawel Zarembski 0:01f31e923fe2 227 {
Pawel Zarembski 0:01f31e923fe2 228 return BUFFER_SIZE - (write_buffer.cnt_in - write_buffer.cnt_out);
Pawel Zarembski 0:01f31e923fe2 229 }
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 232 int32_t uart_write_data(uint8_t *data, uint16_t size)
Pawel Zarembski 0:01f31e923fe2 233 {
Pawel Zarembski 0:01f31e923fe2 234 uint16_t xfer_count = size;
Pawel Zarembski 0:01f31e923fe2 235
Pawel Zarembski 0:01f31e923fe2 236 NVIC_DisableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 237 if (write_buffer.cnt_in == write_buffer.cnt_out) {
Pawel Zarembski 0:01f31e923fe2 238 while ((((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH) &&
Pawel Zarembski 0:01f31e923fe2 239 (xfer_count > 0)) {
Pawel Zarembski 0:01f31e923fe2 240 CdcAcmUart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
Pawel Zarembski 0:01f31e923fe2 241 CdcAcmUartFifo->tx = *data++;
Pawel Zarembski 0:01f31e923fe2 242 xfer_count--;
Pawel Zarembski 0:01f31e923fe2 243 }
Pawel Zarembski 0:01f31e923fe2 244 }
Pawel Zarembski 0:01f31e923fe2 245 NVIC_EnableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 246
Pawel Zarembski 0:01f31e923fe2 247 while (xfer_count > 0) {
Pawel Zarembski 0:01f31e923fe2 248 if ((write_buffer.cnt_in - write_buffer.cnt_out) < BUFFER_SIZE) {
Pawel Zarembski 0:01f31e923fe2 249 write_buffer.data[write_buffer.idx_in++] = *data++;
Pawel Zarembski 0:01f31e923fe2 250 write_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 251 write_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 252 xfer_count--;
Pawel Zarembski 0:01f31e923fe2 253 } else {
Pawel Zarembski 0:01f31e923fe2 254 break;
Pawel Zarembski 0:01f31e923fe2 255 }
Pawel Zarembski 0:01f31e923fe2 256 }
Pawel Zarembski 0:01f31e923fe2 257 return size - xfer_count;
Pawel Zarembski 0:01f31e923fe2 258 }
Pawel Zarembski 0:01f31e923fe2 259
Pawel Zarembski 0:01f31e923fe2 260 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 261 int32_t uart_read_data(uint8_t *data, uint16_t size)
Pawel Zarembski 0:01f31e923fe2 262 {
Pawel Zarembski 0:01f31e923fe2 263 int32_t cnt;
Pawel Zarembski 0:01f31e923fe2 264
Pawel Zarembski 0:01f31e923fe2 265 for (cnt = 0; (cnt < size) && (read_buffer.cnt_in != read_buffer.cnt_out); cnt++) {
Pawel Zarembski 0:01f31e923fe2 266 *data++ = read_buffer.data[read_buffer.idx_out++];
Pawel Zarembski 0:01f31e923fe2 267 read_buffer.idx_out &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 268 read_buffer.cnt_out++;
Pawel Zarembski 0:01f31e923fe2 269 }
Pawel Zarembski 0:01f31e923fe2 270
Pawel Zarembski 0:01f31e923fe2 271 return cnt;
Pawel Zarembski 0:01f31e923fe2 272 }
Pawel Zarembski 0:01f31e923fe2 273
Pawel Zarembski 0:01f31e923fe2 274 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 275 void UART0_IRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 276 {
Pawel Zarembski 0:01f31e923fe2 277 /* Capture interrupt flag state at entry */
Pawel Zarembski 0:01f31e923fe2 278 uint32_t intfl = CdcAcmUart->intfl;
Pawel Zarembski 0:01f31e923fe2 279 /* Clear interrupts that will be serviced */
Pawel Zarembski 0:01f31e923fe2 280 CdcAcmUart->intfl = intfl;
Pawel Zarembski 0:01f31e923fe2 281
Pawel Zarembski 0:01f31e923fe2 282 if (intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
Pawel Zarembski 0:01f31e923fe2 283 read_buffer.data[read_buffer.idx_in++] = '*';
Pawel Zarembski 0:01f31e923fe2 284 read_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 285 read_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 286 }
Pawel Zarembski 0:01f31e923fe2 287
Pawel Zarembski 0:01f31e923fe2 288 if (intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
Pawel Zarembski 0:01f31e923fe2 289 while ((CdcAcmUart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) &&
Pawel Zarembski 0:01f31e923fe2 290 ((read_buffer.cnt_in - read_buffer.cnt_out) < BUFFER_SIZE)) {
Pawel Zarembski 0:01f31e923fe2 291 read_buffer.data[read_buffer.idx_in++] = CdcAcmUartFifo->rx;
Pawel Zarembski 0:01f31e923fe2 292 CdcAcmUart->intfl = MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY;
Pawel Zarembski 0:01f31e923fe2 293 read_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 294 read_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 295 }
Pawel Zarembski 0:01f31e923fe2 296 if (((read_buffer.cnt_in - read_buffer.cnt_out) >= BUFFER_SIZE)) {
Pawel Zarembski 0:01f31e923fe2 297 read_buffer.data[read_buffer.idx_in++] = '%';
Pawel Zarembski 0:01f31e923fe2 298 read_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 299 read_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 300 }
Pawel Zarembski 0:01f31e923fe2 301 }
Pawel Zarembski 0:01f31e923fe2 302
Pawel Zarembski 0:01f31e923fe2 303 if (intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
Pawel Zarembski 0:01f31e923fe2 304 /*
Pawel Zarembski 0:01f31e923fe2 305 Transfer data from write buffer to transmit fifo if
Pawel Zarembski 0:01f31e923fe2 306 a) write buffer contains data and
Pawel Zarembski 0:01f31e923fe2 307 b) transmit fifo is not full
Pawel Zarembski 0:01f31e923fe2 308 */
Pawel Zarembski 0:01f31e923fe2 309 while ((write_buffer.cnt_out != write_buffer.cnt_in) &&
Pawel Zarembski 0:01f31e923fe2 310 (((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH)) {
Pawel Zarembski 0:01f31e923fe2 311 CdcAcmUartFifo->tx = write_buffer.data[write_buffer.idx_out++];
Pawel Zarembski 0:01f31e923fe2 312 write_buffer.idx_out &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 313 write_buffer.cnt_out++;
Pawel Zarembski 0:01f31e923fe2 314 }
Pawel Zarembski 0:01f31e923fe2 315 }
Pawel Zarembski 0:01f31e923fe2 316 }