Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32620/trim_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Pawel Zarembski |
0:01f31e923fe2 | 1 | /******************************************************************************* |
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0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
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0:01f31e923fe2 | 3 | * |
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0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
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0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
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0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
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0:01f31e923fe2 | 10 | * |
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0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
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0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
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0:01f31e923fe2 | 13 | * |
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0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
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0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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0:01f31e923fe2 | 21 | * |
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0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
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0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
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0:01f31e923fe2 | 25 | * |
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0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
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0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
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0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
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0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
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0:01f31e923fe2 | 30 | * ownership rights. |
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0:01f31e923fe2 | 31 | * |
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0:01f31e923fe2 | 32 | ******************************************************************************/ |
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0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | #ifndef _MXC_TRIM_REGS_H_ |
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0:01f31e923fe2 | 35 | #define _MXC_TRIM_REGS_H_ |
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0:01f31e923fe2 | 36 | |
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0:01f31e923fe2 | 37 | #ifdef __cplusplus |
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0:01f31e923fe2 | 38 | extern "C" { |
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0:01f31e923fe2 | 39 | #endif |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #include <stdint.h> |
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0:01f31e923fe2 | 42 | |
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0:01f31e923fe2 | 43 | /* |
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0:01f31e923fe2 | 44 | If types are not defined elsewhere (CMSIS) define them here |
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0:01f31e923fe2 | 45 | */ |
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0:01f31e923fe2 | 46 | #ifndef __IO |
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0:01f31e923fe2 | 47 | #define __IO volatile |
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0:01f31e923fe2 | 48 | #endif |
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0:01f31e923fe2 | 49 | #ifndef __I |
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0:01f31e923fe2 | 50 | #define __I volatile const |
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0:01f31e923fe2 | 51 | #endif |
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0:01f31e923fe2 | 52 | #ifndef __O |
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0:01f31e923fe2 | 53 | #define __O volatile |
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0:01f31e923fe2 | 54 | #endif |
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0:01f31e923fe2 | 55 | #ifndef __R |
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0:01f31e923fe2 | 56 | #define __R volatile const |
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0:01f31e923fe2 | 57 | #endif |
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0:01f31e923fe2 | 58 | |
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0:01f31e923fe2 | 59 | |
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0:01f31e923fe2 | 60 | /* |
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0:01f31e923fe2 | 61 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
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0:01f31e923fe2 | 62 | access to each register in module. |
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0:01f31e923fe2 | 63 | */ |
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0:01f31e923fe2 | 64 | |
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0:01f31e923fe2 | 65 | /* Offset Register Description |
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0:01f31e923fe2 | 66 | ============= ============================================================================ */ |
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0:01f31e923fe2 | 67 | typedef struct { |
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0:01f31e923fe2 | 68 | __R uint32_t rsv000[10]; /* 0x0000-0x0024 */ |
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0:01f31e923fe2 | 69 | __IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */ |
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0:01f31e923fe2 | 70 | __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */ |
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0:01f31e923fe2 | 71 | __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */ |
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0:01f31e923fe2 | 72 | __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */ |
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0:01f31e923fe2 | 73 | __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */ |
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0:01f31e923fe2 | 74 | __IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */ |
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0:01f31e923fe2 | 75 | } mxc_trim_regs_t; |
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0:01f31e923fe2 | 76 | |
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0:01f31e923fe2 | 77 | |
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0:01f31e923fe2 | 78 | /* |
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0:01f31e923fe2 | 79 | Register offsets for module TRIM. |
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0:01f31e923fe2 | 80 | */ |
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0:01f31e923fe2 | 81 | |
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0:01f31e923fe2 | 82 | #define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL) |
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0:01f31e923fe2 | 83 | #define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL) |
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0:01f31e923fe2 | 84 | #define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL) |
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0:01f31e923fe2 | 85 | #define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL) |
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0:01f31e923fe2 | 86 | #define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL) |
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0:01f31e923fe2 | 87 | #define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL) |
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0:01f31e923fe2 | 88 | |
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0:01f31e923fe2 | 89 | |
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0:01f31e923fe2 | 90 | /* |
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0:01f31e923fe2 | 91 | Field positions and masks for module TRIM. |
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0:01f31e923fe2 | 92 | */ |
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0:01f31e923fe2 | 93 | |
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0:01f31e923fe2 | 94 | #define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0 |
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0:01f31e923fe2 | 95 | #define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS)) |
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0:01f31e923fe2 | 96 | #define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2 |
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0:01f31e923fe2 | 97 | #define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS)) |
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0:01f31e923fe2 | 98 | |
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0:01f31e923fe2 | 99 | #define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL)) |
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0:01f31e923fe2 | 100 | #define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL)) |
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0:01f31e923fe2 | 101 | #define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL)) |
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0:01f31e923fe2 | 102 | |
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0:01f31e923fe2 | 103 | #define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL)) |
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0:01f31e923fe2 | 104 | #define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL)) |
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0:01f31e923fe2 | 105 | #define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL)) |
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0:01f31e923fe2 | 106 | #define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL)) |
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0:01f31e923fe2 | 107 | #define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL)) |
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0:01f31e923fe2 | 108 | |
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0:01f31e923fe2 | 109 | #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0 |
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0:01f31e923fe2 | 110 | #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS)) |
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0:01f31e923fe2 | 111 | #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16 |
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0:01f31e923fe2 | 112 | #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS)) |
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0:01f31e923fe2 | 113 | |
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0:01f31e923fe2 | 114 | #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0 |
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0:01f31e923fe2 | 115 | #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS)) |
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0:01f31e923fe2 | 116 | #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16 |
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0:01f31e923fe2 | 117 | #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS)) |
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0:01f31e923fe2 | 118 | #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28 |
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0:01f31e923fe2 | 119 | #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS)) |
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0:01f31e923fe2 | 120 | |
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0:01f31e923fe2 | 121 | |
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0:01f31e923fe2 | 122 | |
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0:01f31e923fe2 | 123 | #ifdef __cplusplus |
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0:01f31e923fe2 | 124 | } |
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0:01f31e923fe2 | 125 | #endif |
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0:01f31e923fe2 | 126 | |
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0:01f31e923fe2 | 127 | #endif /* _MXC_TRIM_REGS_H_ */ |