Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/system_SAM3U.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**************************************************************************//**
Pawel Zarembski 0:01f31e923fe2 2 * @file system_SAM3U.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
Pawel Zarembski 0:01f31e923fe2 4 * for the Atmel SAM3U Device Series
Pawel Zarembski 0:01f31e923fe2 5 * @version V1.10
Pawel Zarembski 0:01f31e923fe2 6 * @date 16. April 2013
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * @note
Pawel Zarembski 0:01f31e923fe2 9 * Copyright (C) 2019-2013 ARM Limited. All rights reserved.
Pawel Zarembski 0:01f31e923fe2 10 *
Pawel Zarembski 0:01f31e923fe2 11 * @par
Pawel Zarembski 0:01f31e923fe2 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Pawel Zarembski 0:01f31e923fe2 13 * processor based microcontrollers. This file can be freely distributed
Pawel Zarembski 0:01f31e923fe2 14 * within development tools that are supporting such ARM based processors.
Pawel Zarembski 0:01f31e923fe2 15 *
Pawel Zarembski 0:01f31e923fe2 16 * @par
Pawel Zarembski 0:01f31e923fe2 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Pawel Zarembski 0:01f31e923fe2 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Pawel Zarembski 0:01f31e923fe2 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Pawel Zarembski 0:01f31e923fe2 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Pawel Zarembski 0:01f31e923fe2 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Pawel Zarembski 0:01f31e923fe2 22 *
Pawel Zarembski 0:01f31e923fe2 23 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 #include "sam3u.h"
Pawel Zarembski 0:01f31e923fe2 27
Pawel Zarembski 0:01f31e923fe2 28 /*
Pawel Zarembski 0:01f31e923fe2 29 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
Pawel Zarembski 0:01f31e923fe2 30 */
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 /*--------------------- Embedded Flash Controllers Configuration -------------
Pawel Zarembski 0:01f31e923fe2 33 //
Pawel Zarembski 0:01f31e923fe2 34 // <e0> Embedded Flash Controller 0 (EEFC0)
Pawel Zarembski 0:01f31e923fe2 35 // <o1.8..11> FWS: Flash Wait State <1-16><#-1>
Pawel Zarembski 0:01f31e923fe2 36 // <o1.24> FAM: Flash Access Mode
Pawel Zarembski 0:01f31e923fe2 37 // <0=> 128-bit in read mode (enhance speed)
Pawel Zarembski 0:01f31e923fe2 38 // <1=> 64-bit in read mode (enhance power consumption)
Pawel Zarembski 0:01f31e923fe2 39 // </e0>
Pawel Zarembski 0:01f31e923fe2 40 //
Pawel Zarembski 0:01f31e923fe2 41 // <e2> Embedded Flash Controller 1 (EEFC1)
Pawel Zarembski 0:01f31e923fe2 42 // <o3.8..11> FWS: Flash Wait State <1-16><#-1>
Pawel Zarembski 0:01f31e923fe2 43 // <o3.24> FAM: Flash Access Mode
Pawel Zarembski 0:01f31e923fe2 44 // <0=> 128-bit in read mode (enhance speed)
Pawel Zarembski 0:01f31e923fe2 45 // <1=> 64-bit in read mode (enhance power consumption)
Pawel Zarembski 0:01f31e923fe2 46 // </e2>
Pawel Zarembski 0:01f31e923fe2 47 */
Pawel Zarembski 0:01f31e923fe2 48 #define EEFC0_SETUP 1 // Reset values:
Pawel Zarembski 0:01f31e923fe2 49 #define EEFC0_FMR_Val 0x00000300 // 0x00000000
Pawel Zarembski 0:01f31e923fe2 50 #define EEFC1_SETUP 1 // Reset values:
Pawel Zarembski 0:01f31e923fe2 51 #define EEFC1_FMR_Val 0x00000300 // 0x00000000
Pawel Zarembski 0:01f31e923fe2 52
Pawel Zarembski 0:01f31e923fe2 53
Pawel Zarembski 0:01f31e923fe2 54 /*--------------------- Power Management Controller Configuration ------------
Pawel Zarembski 0:01f31e923fe2 55 //
Pawel Zarembski 0:01f31e923fe2 56 // <e> Power Management Controller (PMC)
Pawel Zarembski 0:01f31e923fe2 57 // <h> System Clock Enable Register (PMC_SCER)
Pawel Zarembski 0:01f31e923fe2 58 // <o1.8> PCK0: Programmable Clock 0 Output Enable
Pawel Zarembski 0:01f31e923fe2 59 // <o1.9> PCK1: Programmable Clock 1 Output Enable
Pawel Zarembski 0:01f31e923fe2 60 // <o1.10> PCK2: Programmable Clock 2 Output Enable
Pawel Zarembski 0:01f31e923fe2 61 // </h>
Pawel Zarembski 0:01f31e923fe2 62 //
Pawel Zarembski 0:01f31e923fe2 63 // <h> Peripheral Clock Enable Register (PMC_PCER)
Pawel Zarembski 0:01f31e923fe2 64 // <o2.2> PID2: Real Time Clock Clock Enable
Pawel Zarembski 0:01f31e923fe2 65 // <o2.3> PID3: Real Time Timer Clock Enable
Pawel Zarembski 0:01f31e923fe2 66 // <o2.4> PID4: Watchdog Timer Clock Enable
Pawel Zarembski 0:01f31e923fe2 67 // <o2.5> PID5: Power Management Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 68 // <o2.6> PID6: Enhanced Embedded Flash Controller 0 Clock Enable
Pawel Zarembski 0:01f31e923fe2 69 // <o2.7> PID7: Enhanced Embedded Flash Controller 1 Clock Enable
Pawel Zarembski 0:01f31e923fe2 70 // <o2.8> PID8: UART Clock Enable
Pawel Zarembski 0:01f31e923fe2 71 // <o2.9> PID9: Static Memory Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 72 // <o2.10> PID10: Parallel I/O Controller A Clock Enable
Pawel Zarembski 0:01f31e923fe2 73 // <o2.11> PID11: Parallel I/O Controller B Clock Enable
Pawel Zarembski 0:01f31e923fe2 74 // <o2.12> PID12: Parallel I/O Controller C Clock Enable
Pawel Zarembski 0:01f31e923fe2 75 // <o2.13> PID13: USART 0 Clock Enable
Pawel Zarembski 0:01f31e923fe2 76 // <o2.14> PID14: USART 1 Clock Enable
Pawel Zarembski 0:01f31e923fe2 77 // <o2.15> PID15: USART 2 Clock Enable
Pawel Zarembski 0:01f31e923fe2 78 // <o2.16> PID16: USART 3 Clock Enable
Pawel Zarembski 0:01f31e923fe2 79 // <o2.17> PID17: High Speed Multimedia Card Interface Clock Enable
Pawel Zarembski 0:01f31e923fe2 80 // <o2.18> PID18: Two-wire Interface 0 Clock Enable
Pawel Zarembski 0:01f31e923fe2 81 // <o2.19> PID19: Two-wire Interface 1 Clock Enable
Pawel Zarembski 0:01f31e923fe2 82 // <o2.20> PID20: Synchronous Peripheral Interface Clock Enable
Pawel Zarembski 0:01f31e923fe2 83 // <o2.21> PID21: Synchronous Serial Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 84 // <o2.22> PID22: Timer Counter 0 Clock Enable
Pawel Zarembski 0:01f31e923fe2 85 // <o2.23> PID23: Timer Counter 1 Clock Enable
Pawel Zarembski 0:01f31e923fe2 86 // <o2.24> PID24: Timer Counter 2 Clock Enable
Pawel Zarembski 0:01f31e923fe2 87 // <o2.25> PID25: Pulse Width Modulation Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 88 // <o2.26> PID26: 12-bit ADC Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 89 // <o2.27> PID27: 10-bit ADC Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 90 // <o2.28> PID28: DMA Controller Clock Enable
Pawel Zarembski 0:01f31e923fe2 91 // <o2.29> PID29: USB Device High Speed Clock Enable
Pawel Zarembski 0:01f31e923fe2 92 // </h>
Pawel Zarembski 0:01f31e923fe2 93 //
Pawel Zarembski 0:01f31e923fe2 94 // <h> UTMI Clock Configuration Register (CKGR_UCKR)
Pawel Zarembski 0:01f31e923fe2 95 // <o3.16> UPLLEN: UTMI PLL Enable
Pawel Zarembski 0:01f31e923fe2 96 // <o3.20..23> UPLLCOUNT: UTMI PLL Startup Time <0-15>
Pawel Zarembski 0:01f31e923fe2 97 // </h>
Pawel Zarembski 0:01f31e923fe2 98 //
Pawel Zarembski 0:01f31e923fe2 99 // <h> Main Oscillator Register (CKGR_MOR)
Pawel Zarembski 0:01f31e923fe2 100 // <o4.0> MOSCXTEN: Main Crystal Oscillator Enable
Pawel Zarembski 0:01f31e923fe2 101 // <o4.1> MOSCXTBY: Main Crystal Oscillator Bypass
Pawel Zarembski 0:01f31e923fe2 102 // <o4.2> WAITMODE: Wait Mode Command
Pawel Zarembski 0:01f31e923fe2 103 // <o4.3> MOSCRCEN: Main On-chip RC Oscillator Enable
Pawel Zarembski 0:01f31e923fe2 104 // <o4.4..6> MOSCRCF: Main On-chip RC Oscillator Frequency Selection
Pawel Zarembski 0:01f31e923fe2 105 // <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved
Pawel Zarembski 0:01f31e923fe2 106 // <o4.8..15> MOSCXTST: Main Crystal Oscillator Startup Time <0-255>
Pawel Zarembski 0:01f31e923fe2 107 // <o4.24> MOSCSEL: Main Oscillator Selection
Pawel Zarembski 0:01f31e923fe2 108 // <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator
Pawel Zarembski 0:01f31e923fe2 109 // <o4.25> CFDEN: Clock Failure Detector Enable
Pawel Zarembski 0:01f31e923fe2 110 // </h>
Pawel Zarembski 0:01f31e923fe2 111 //
Pawel Zarembski 0:01f31e923fe2 112 // <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
Pawel Zarembski 0:01f31e923fe2 113 // <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
Pawel Zarembski 0:01f31e923fe2 114 // <i> Example: XTAL = 12 MHz, DIVA = 1, MULA = 14 => PLLA = 168 MHz
Pawel Zarembski 0:01f31e923fe2 115 // <o5.0..7> DIVA: PLL Divider A <0-255>
Pawel Zarembski 0:01f31e923fe2 116 // <i> 0 - Divider output is 0
Pawel Zarembski 0:01f31e923fe2 117 // <i> 1 - Divider is bypassed
Pawel Zarembski 0:01f31e923fe2 118 // <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
Pawel Zarembski 0:01f31e923fe2 119 // <o5.8..13> PLLACOUNT: PLL A Counter <0-63>
Pawel Zarembski 0:01f31e923fe2 120 // <i> Number of Slow Clocks before the LOCKA bit is set in
Pawel Zarembski 0:01f31e923fe2 121 // <i> PMC_SR after CKGR_PLLAR is written
Pawel Zarembski 0:01f31e923fe2 122 // <o5.14..15> STMODE: Start Mode
Pawel Zarembski 0:01f31e923fe2 123 // <0=> Fast Startup <1=> Reserved <2=> Normal Startup <3=> Reserved
Pawel Zarembski 0:01f31e923fe2 124 // <i> Must be set to "Normal Startup" when PLL A is Off
Pawel Zarembski 0:01f31e923fe2 125 // <o5.16..26> MULA: PLL A Multiplier <0-2047>
Pawel Zarembski 0:01f31e923fe2 126 // <i> 0 - The PLL A is deactivated
Pawel Zarembski 0:01f31e923fe2 127 // <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input
Pawel Zarembski 0:01f31e923fe2 128 // <i> frequency multiplied by MULA + 1
Pawel Zarembski 0:01f31e923fe2 129 // </h>
Pawel Zarembski 0:01f31e923fe2 130 //
Pawel Zarembski 0:01f31e923fe2 131 // <h> Master Clock Register (CKGR_MCKR)
Pawel Zarembski 0:01f31e923fe2 132 // <o6.0..1> CSS: Master Clock Selection
Pawel Zarembski 0:01f31e923fe2 133 // <0=> Slow Clock
Pawel Zarembski 0:01f31e923fe2 134 // <1=> Main Clock
Pawel Zarembski 0:01f31e923fe2 135 // <2=> PLL A Clock
Pawel Zarembski 0:01f31e923fe2 136 // <3=> UPLL Clock
Pawel Zarembski 0:01f31e923fe2 137 // <o6.4..6> PRES: Master Clock Prescaler
Pawel Zarembski 0:01f31e923fe2 138 // <0=> Clock <1=> Clock / 2
Pawel Zarembski 0:01f31e923fe2 139 // <2=> Clock / 4 <3=> Clock / 8
Pawel Zarembski 0:01f31e923fe2 140 // <4=> Clock / 16 <5=> Clock / 32
Pawel Zarembski 0:01f31e923fe2 141 // <6=> Clock / 64 <7=> Clock / 6
Pawel Zarembski 0:01f31e923fe2 142 // </h>
Pawel Zarembski 0:01f31e923fe2 143 //
Pawel Zarembski 0:01f31e923fe2 144 // <h> Programmable Clock Register 0 (PMC_PCK0)
Pawel Zarembski 0:01f31e923fe2 145 // <o7.0..2> CSS: Master Clock Selection
Pawel Zarembski 0:01f31e923fe2 146 // <0=> Slow Clock
Pawel Zarembski 0:01f31e923fe2 147 // <1=> Main Clock
Pawel Zarembski 0:01f31e923fe2 148 // <2=> PLL A Clock
Pawel Zarembski 0:01f31e923fe2 149 // <3=> UPLL Clock
Pawel Zarembski 0:01f31e923fe2 150 // <4=> Master Clock
Pawel Zarembski 0:01f31e923fe2 151 // <5=> Master Clock
Pawel Zarembski 0:01f31e923fe2 152 // <6=> Master Clock
Pawel Zarembski 0:01f31e923fe2 153 // <7=> Master Clock
Pawel Zarembski 0:01f31e923fe2 154 // <o7.4..6> PRES: Programmable Clock Prescaler
Pawel Zarembski 0:01f31e923fe2 155 // <0=> Clock <1=> Clock / 2
Pawel Zarembski 0:01f31e923fe2 156 // <2=> Clock / 4 <3=> Clock / 8
Pawel Zarembski 0:01f31e923fe2 157 // <4=> Clock / 16 <5=> Clock / 32
Pawel Zarembski 0:01f31e923fe2 158 // <6=> Clock / 64 <7=> Reserved
Pawel Zarembski 0:01f31e923fe2 159 // </h>
Pawel Zarembski 0:01f31e923fe2 160 //
Pawel Zarembski 0:01f31e923fe2 161 // <h> Programmable Clock Register 1 (PMC_PCK1)
Pawel Zarembski 0:01f31e923fe2 162 // <o8.0..2> CSS: Master Clock Selection
Pawel Zarembski 0:01f31e923fe2 163 // <0=> Slow Clock
Pawel Zarembski 0:01f31e923fe2 164 // <1=> Main Clock
Pawel Zarembski 0:01f31e923fe2 165 // <2=> PLL A Clock
Pawel Zarembski 0:01f31e923fe2 166 // <3=> UPLL Clock
Pawel Zarembski 0:01f31e923fe2 167 // <4=> Master Clock
Pawel Zarembski 0:01f31e923fe2 168 // <5=> Master Clock
Pawel Zarembski 0:01f31e923fe2 169 // <6=> Master Clock
Pawel Zarembski 0:01f31e923fe2 170 // <7=> Master Clock
Pawel Zarembski 0:01f31e923fe2 171 // <o8.4..6> PRES: Programmable Clock Prescaler
Pawel Zarembski 0:01f31e923fe2 172 // <0=> None <1=> Clock / 2
Pawel Zarembski 0:01f31e923fe2 173 // <2=> Clock / 4 <3=> Clock / 8
Pawel Zarembski 0:01f31e923fe2 174 // <4=> Clock / 16 <5=> Clock / 32
Pawel Zarembski 0:01f31e923fe2 175 // <6=> Clock / 64 <7=> Reserved
Pawel Zarembski 0:01f31e923fe2 176 // </h>
Pawel Zarembski 0:01f31e923fe2 177 //
Pawel Zarembski 0:01f31e923fe2 178 // <h> Programmable Clock Register 2 (PMC_PCK2)
Pawel Zarembski 0:01f31e923fe2 179 // <o9.0..2> CSS: Master Clock Selection
Pawel Zarembski 0:01f31e923fe2 180 // <0=> Slow Clock
Pawel Zarembski 0:01f31e923fe2 181 // <1=> Main Clock
Pawel Zarembski 0:01f31e923fe2 182 // <2=> PLL A Clock
Pawel Zarembski 0:01f31e923fe2 183 // <3=> UPLL Clock
Pawel Zarembski 0:01f31e923fe2 184 // <4=> Master Clock
Pawel Zarembski 0:01f31e923fe2 185 // <5=> Master Clock
Pawel Zarembski 0:01f31e923fe2 186 // <6=> Master Clock
Pawel Zarembski 0:01f31e923fe2 187 // <7=> Master Clock
Pawel Zarembski 0:01f31e923fe2 188 // <o9.4..6> PRES: Programmable Clock Prescaler
Pawel Zarembski 0:01f31e923fe2 189 // <0=> None <1=> Clock / 2
Pawel Zarembski 0:01f31e923fe2 190 // <2=> Clock / 4 <3=> Clock / 8
Pawel Zarembski 0:01f31e923fe2 191 // <4=> Clock / 16 <5=> Clock / 32
Pawel Zarembski 0:01f31e923fe2 192 // <6=> Clock / 64 <7=> Reserved
Pawel Zarembski 0:01f31e923fe2 193 // </h>
Pawel Zarembski 0:01f31e923fe2 194 // </e>
Pawel Zarembski 0:01f31e923fe2 195 */
Pawel Zarembski 0:01f31e923fe2 196 #define PMC_SETUP 1 // Reset values:
Pawel Zarembski 0:01f31e923fe2 197 #define PMC_SCER_Val 0x00000000 // WO register (0x00000001)
Pawel Zarembski 0:01f31e923fe2 198 #define PMC_PCER_Val 0x00001C00 // WO register (0x00000000)
Pawel Zarembski 0:01f31e923fe2 199 #define CKGR_UCKR_Val 0x10200000 // 0x10200800
Pawel Zarembski 0:01f31e923fe2 200 #define CKGR_MOR_Val 0x01370101 // 0x00000001
Pawel Zarembski 0:01f31e923fe2 201 #define CKGR_PLLAR_Val 0x200F8601 //0x200D8601 // 0x00003F00
Pawel Zarembski 0:01f31e923fe2 202 #define PMC_MCKR_Val 0x00000012 // 0x00000001
Pawel Zarembski 0:01f31e923fe2 203 #define PMC_PCK0_Val 0x00000000 // 0x00000000
Pawel Zarembski 0:01f31e923fe2 204 #define PMC_PCK1_Val 0x00000000 // 0x00000000
Pawel Zarembski 0:01f31e923fe2 205 #define PMC_PCK2_Val 0x00000000 // 0x00000000
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207
Pawel Zarembski 0:01f31e923fe2 208 /*--------------------- Watchdog Configuration -------------------------------
Pawel Zarembski 0:01f31e923fe2 209 //
Pawel Zarembski 0:01f31e923fe2 210 // <e> Watchdog Disable
Pawel Zarembski 0:01f31e923fe2 211 // </e>
Pawel Zarembski 0:01f31e923fe2 212 */
Pawel Zarembski 0:01f31e923fe2 213 #define WDT_SETUP 1 // Reset values:
Pawel Zarembski 0:01f31e923fe2 214
Pawel Zarembski 0:01f31e923fe2 215
Pawel Zarembski 0:01f31e923fe2 216 /*
Pawel Zarembski 0:01f31e923fe2 217 //-------- <<< end of configuration section >>> ------------------------------
Pawel Zarembski 0:01f31e923fe2 218 */
Pawel Zarembski 0:01f31e923fe2 219
Pawel Zarembski 0:01f31e923fe2 220 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 221 Check the register settings
Pawel Zarembski 0:01f31e923fe2 222 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 223 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
Pawel Zarembski 0:01f31e923fe2 224 #define CHECK_RSVD(val, mask) (val & mask)
Pawel Zarembski 0:01f31e923fe2 225
Pawel Zarembski 0:01f31e923fe2 226 /* Embedded Flash Controllers Configuration ----------------------------------*/
Pawel Zarembski 0:01f31e923fe2 227 #if (CHECK_RSVD((EEFC0_FMR_Val), ~0x01000F01))
Pawel Zarembski 0:01f31e923fe2 228 #error "EEFC0_FMR: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 229 #endif
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 #if (CHECK_RSVD((EEFC1_FMR_Val), ~0x01000F01))
Pawel Zarembski 0:01f31e923fe2 232 #error "EEFC1_FMR: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 233 #endif
Pawel Zarembski 0:01f31e923fe2 234
Pawel Zarembski 0:01f31e923fe2 235 /* Power Management Controller Configuration ---------------------------------*/
Pawel Zarembski 0:01f31e923fe2 236 #if (CHECK_RSVD((PMC_SCER_Val), ~0x00000700))
Pawel Zarembski 0:01f31e923fe2 237 #error "PMC_SCER: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 238 #endif
Pawel Zarembski 0:01f31e923fe2 239
Pawel Zarembski 0:01f31e923fe2 240 #if (CHECK_RSVD((PMC_PCER_Val), ~0xFFFFFFFC))
Pawel Zarembski 0:01f31e923fe2 241 #error "PMC_PCER: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 242 #endif
Pawel Zarembski 0:01f31e923fe2 243
Pawel Zarembski 0:01f31e923fe2 244 #if (CHECK_RSVD((CKGR_UCKR_Val), ~0x10F10000))
Pawel Zarembski 0:01f31e923fe2 245 #error "CKGR_UCKR: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 246 #endif
Pawel Zarembski 0:01f31e923fe2 247
Pawel Zarembski 0:01f31e923fe2 248 #if (CHECK_RSVD((CKGR_MOR_Val), ~0x03FFFF7F))
Pawel Zarembski 0:01f31e923fe2 249 #error "CKGR_MOR: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 250 #endif
Pawel Zarembski 0:01f31e923fe2 251
Pawel Zarembski 0:01f31e923fe2 252 #if (CHECK_RSVD((CKGR_PLLAR_Val), ~0x27FFFFFF))
Pawel Zarembski 0:01f31e923fe2 253 #error "CKGR_PLLAR: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 254 #endif
Pawel Zarembski 0:01f31e923fe2 255
Pawel Zarembski 0:01f31e923fe2 256 #if (CHECK_RSVD((PMC_MCKR_Val), ~0x00000073))
Pawel Zarembski 0:01f31e923fe2 257 #error "PMC_MCKR: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 258 #endif
Pawel Zarembski 0:01f31e923fe2 259
Pawel Zarembski 0:01f31e923fe2 260 #if (CHECK_RSVD((PMC_PCK0_Val), ~0x00000077))
Pawel Zarembski 0:01f31e923fe2 261 #error "PMC_PCK0: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 262 #endif
Pawel Zarembski 0:01f31e923fe2 263
Pawel Zarembski 0:01f31e923fe2 264 #if (CHECK_RSVD((PMC_PCK1_Val), ~0x00000077))
Pawel Zarembski 0:01f31e923fe2 265 #error "PMC_PCK1: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 266 #endif
Pawel Zarembski 0:01f31e923fe2 267
Pawel Zarembski 0:01f31e923fe2 268 #if (CHECK_RSVD((PMC_PCK2_Val), ~0x00000077))
Pawel Zarembski 0:01f31e923fe2 269 #error "PMC_PCK2: Invalid values of reserved bits!"
Pawel Zarembski 0:01f31e923fe2 270 #endif
Pawel Zarembski 0:01f31e923fe2 271
Pawel Zarembski 0:01f31e923fe2 272
Pawel Zarembski 0:01f31e923fe2 273 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 274 DEFINES
Pawel Zarembski 0:01f31e923fe2 275 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 276
Pawel Zarembski 0:01f31e923fe2 277 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 278 Define clocks
Pawel Zarembski 0:01f31e923fe2 279 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 280 #define XTAL (12000000UL) /* Crystal frequency */
Pawel Zarembski 0:01f31e923fe2 281 #define XTAL32 ( 32768UL) /* 32k crystal frequency */
Pawel Zarembski 0:01f31e923fe2 282 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
Pawel Zarembski 0:01f31e923fe2 283 #define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
Pawel Zarembski 0:01f31e923fe2 284 #define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
Pawel Zarembski 0:01f31e923fe2 285 #define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
Pawel Zarembski 0:01f31e923fe2 286
Pawel Zarembski 0:01f31e923fe2 287
Pawel Zarembski 0:01f31e923fe2 288
Pawel Zarembski 0:01f31e923fe2 289 #if (PMC_SETUP)
Pawel Zarembski 0:01f31e923fe2 290 /* Determine clock frequency according to clock register values */
Pawel Zarembski 0:01f31e923fe2 291 #if ((PMC_MCKR_Val & 3) == 0) /* Slow Clock is selected */
Pawel Zarembski 0:01f31e923fe2 292 #if (1 /* PMC_SR & (1 << 7) */) /* MUST be checked with correct register */
Pawel Zarembski 0:01f31e923fe2 293 #define __CORE_CLK_PRE (OSC32_CLK)
Pawel Zarembski 0:01f31e923fe2 294 #else
Pawel Zarembski 0:01f31e923fe2 295 #define __CORE_CLK_PRE (ERC_OSC)
Pawel Zarembski 0:01f31e923fe2 296 #endif
Pawel Zarembski 0:01f31e923fe2 297 #elif ((PMC_MCKR_Val & 3) == 1) /* Main Clock is selected */
Pawel Zarembski 0:01f31e923fe2 298 #if (CKGR_MOR_Val & (1 << 24))
Pawel Zarembski 0:01f31e923fe2 299 #if ((CKGR_MOR_Val & (1<< 0)) == 0)
Pawel Zarembski 0:01f31e923fe2 300 #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!"
Pawel Zarembski 0:01f31e923fe2 301 #endif
Pawel Zarembski 0:01f31e923fe2 302 #define __CORE_CLK_PRE (OSC_CLK)
Pawel Zarembski 0:01f31e923fe2 303 #else
Pawel Zarembski 0:01f31e923fe2 304 #if ((CKGR_MOR_Val & (1<< 3)) == 0)
Pawel Zarembski 0:01f31e923fe2 305 #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!"
Pawel Zarembski 0:01f31e923fe2 306 #endif
Pawel Zarembski 0:01f31e923fe2 307 #if (((CKGR_MOR_Val >> 4) & 3) == 0)
Pawel Zarembski 0:01f31e923fe2 308 #define __CORE_CLK_PRE (EFRC_OSC)
Pawel Zarembski 0:01f31e923fe2 309 #elif (((CKGR_MOR_Val >> 4) & 3) == 1)
Pawel Zarembski 0:01f31e923fe2 310 #define __CORE_CLK_PRE (EFRC_OSC * 2)
Pawel Zarembski 0:01f31e923fe2 311 #elif (((CKGR_MOR_Val >> 4) & 3) == 2)
Pawel Zarembski 0:01f31e923fe2 312 #define __CORE_CLK_PRE (EFRC_OSC * 3)
Pawel Zarembski 0:01f31e923fe2 313 #else
Pawel Zarembski 0:01f31e923fe2 314 #define __CORE_CLK_PRE (EFRC_OSC)
Pawel Zarembski 0:01f31e923fe2 315 #endif
Pawel Zarembski 0:01f31e923fe2 316 #endif
Pawel Zarembski 0:01f31e923fe2 317 #elif ((PMC_MCKR_Val & 3) == 2) /* PLLA Clock is selected */
Pawel Zarembski 0:01f31e923fe2 318 #if (CKGR_MOR_Val & (1 << 24))
Pawel Zarembski 0:01f31e923fe2 319 #if ((CKGR_MOR_Val & (1<< 0)) == 0)
Pawel Zarembski 0:01f31e923fe2 320 #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!"
Pawel Zarembski 0:01f31e923fe2 321 #endif
Pawel Zarembski 0:01f31e923fe2 322 #define __PLLA_CLK (OSC_CLK)
Pawel Zarembski 0:01f31e923fe2 323 #else
Pawel Zarembski 0:01f31e923fe2 324 #if ((CKGR_MOR_Val & (1<< 3)) == 0)
Pawel Zarembski 0:01f31e923fe2 325 #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!"
Pawel Zarembski 0:01f31e923fe2 326 #endif
Pawel Zarembski 0:01f31e923fe2 327 #if (((CKGR_MOR_Val >> 4) & 3) == 0)
Pawel Zarembski 0:01f31e923fe2 328 #define __PLLA_CLK (EFRC_OSC)
Pawel Zarembski 0:01f31e923fe2 329 #elif (((CKGR_MOR_Val >> 4) & 3) == 1)
Pawel Zarembski 0:01f31e923fe2 330 #define __PLLA_CLK (EFRC_OSC * 2)
Pawel Zarembski 0:01f31e923fe2 331 #elif (((CKGR_MOR_Val >> 4) & 3) == 2)
Pawel Zarembski 0:01f31e923fe2 332 #define __PLLA_CLK (EFRC_OSC * 3)
Pawel Zarembski 0:01f31e923fe2 333 #else
Pawel Zarembski 0:01f31e923fe2 334 #define __PLLA_CLK (EFRC_OSC)
Pawel Zarembski 0:01f31e923fe2 335 #endif
Pawel Zarembski 0:01f31e923fe2 336 #endif
Pawel Zarembski 0:01f31e923fe2 337
Pawel Zarembski 0:01f31e923fe2 338 #define __PLLA_MUL ((((CKGR_PLLAR_Val) >> 16) & 0x7FF) + 1)
Pawel Zarembski 0:01f31e923fe2 339 #define __PLLA_DIV ((((CKGR_PLLAR_Val) >> 0) & 0x0FF))
Pawel Zarembski 0:01f31e923fe2 340 #define __CORE_CLK_PRE (__PLLA_CLK * __PLLA_MUL / __PLLA_DIV)
Pawel Zarembski 0:01f31e923fe2 341 #else /* UPLL Clock is selected */
Pawel Zarembski 0:01f31e923fe2 342 #define __CORE_CLK_PRE (OSC_CLK * 40)
Pawel Zarembski 0:01f31e923fe2 343 #endif
Pawel Zarembski 0:01f31e923fe2 344
Pawel Zarembski 0:01f31e923fe2 345 #if (((PMC_MCKR_Val >> 4) & 7) == 7)
Pawel Zarembski 0:01f31e923fe2 346 #define __CORE_CLK (__CORE_CLK_PRE / 6)
Pawel Zarembski 0:01f31e923fe2 347 #else
Pawel Zarembski 0:01f31e923fe2 348 #define __CORE_CLK (__CORE_CLK_PRE >> ((PMC_MCKR_Val >> 4) & 7))
Pawel Zarembski 0:01f31e923fe2 349 #endif
Pawel Zarembski 0:01f31e923fe2 350
Pawel Zarembski 0:01f31e923fe2 351 #else
Pawel Zarembski 0:01f31e923fe2 352 #define __CORE_CLK (EFRC_OSC)
Pawel Zarembski 0:01f31e923fe2 353 #endif
Pawel Zarembski 0:01f31e923fe2 354
Pawel Zarembski 0:01f31e923fe2 355 #if (__CORE_CLK > 96000000UL)
Pawel Zarembski 0:01f31e923fe2 356 #error "Core Clock > 96MHz!"
Pawel Zarembski 0:01f31e923fe2 357 #endif
Pawel Zarembski 0:01f31e923fe2 358
Pawel Zarembski 0:01f31e923fe2 359 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 360 Clock Variable definitions
Pawel Zarembski 0:01f31e923fe2 361 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 362 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
Pawel Zarembski 0:01f31e923fe2 363
Pawel Zarembski 0:01f31e923fe2 364
Pawel Zarembski 0:01f31e923fe2 365 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 366 Clock functions
Pawel Zarembski 0:01f31e923fe2 367 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 368 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
Pawel Zarembski 0:01f31e923fe2 369 {
Pawel Zarembski 0:01f31e923fe2 370 /* Determine clock frequency according to clock register values */
Pawel Zarembski 0:01f31e923fe2 371 switch (PMC->PMC_MCKR & 3) {
Pawel Zarembski 0:01f31e923fe2 372 case 0: /* Slow clock */
Pawel Zarembski 0:01f31e923fe2 373 if (SUPC->SUPC_SR & (1 << 7))
Pawel Zarembski 0:01f31e923fe2 374 SystemCoreClock = OSC32_CLK;
Pawel Zarembski 0:01f31e923fe2 375 else
Pawel Zarembski 0:01f31e923fe2 376 SystemCoreClock = ERC_OSC;
Pawel Zarembski 0:01f31e923fe2 377 break;
Pawel Zarembski 0:01f31e923fe2 378 case 1: /* Main clock */
Pawel Zarembski 0:01f31e923fe2 379 if (PMC->CKGR_MOR & (1 << 24))
Pawel Zarembski 0:01f31e923fe2 380 SystemCoreClock = OSC_CLK;
Pawel Zarembski 0:01f31e923fe2 381 else {
Pawel Zarembski 0:01f31e923fe2 382 SystemCoreClock = EFRC_OSC;
Pawel Zarembski 0:01f31e923fe2 383 switch ((PMC->CKGR_MOR >> 4) & 3) {
Pawel Zarembski 0:01f31e923fe2 384 case 0:
Pawel Zarembski 0:01f31e923fe2 385 break;
Pawel Zarembski 0:01f31e923fe2 386 case 1:
Pawel Zarembski 0:01f31e923fe2 387 SystemCoreClock *= 2;
Pawel Zarembski 0:01f31e923fe2 388 break;
Pawel Zarembski 0:01f31e923fe2 389 case 2:
Pawel Zarembski 0:01f31e923fe2 390 SystemCoreClock *= 3;
Pawel Zarembski 0:01f31e923fe2 391 break;
Pawel Zarembski 0:01f31e923fe2 392 case 3:
Pawel Zarembski 0:01f31e923fe2 393 break;
Pawel Zarembski 0:01f31e923fe2 394 }
Pawel Zarembski 0:01f31e923fe2 395 }
Pawel Zarembski 0:01f31e923fe2 396 break;
Pawel Zarembski 0:01f31e923fe2 397 case 2: /* PLLA clock */
Pawel Zarembski 0:01f31e923fe2 398 if (PMC->CKGR_MOR & (1 << 24))
Pawel Zarembski 0:01f31e923fe2 399 SystemCoreClock = OSC_CLK;
Pawel Zarembski 0:01f31e923fe2 400 else {
Pawel Zarembski 0:01f31e923fe2 401 SystemCoreClock = EFRC_OSC;
Pawel Zarembski 0:01f31e923fe2 402 switch ((PMC->CKGR_MOR >> 4) & 3) {
Pawel Zarembski 0:01f31e923fe2 403 case 0:
Pawel Zarembski 0:01f31e923fe2 404 break;
Pawel Zarembski 0:01f31e923fe2 405 case 1:
Pawel Zarembski 0:01f31e923fe2 406 SystemCoreClock *= 2;
Pawel Zarembski 0:01f31e923fe2 407 break;
Pawel Zarembski 0:01f31e923fe2 408 case 2:
Pawel Zarembski 0:01f31e923fe2 409 SystemCoreClock *= 3;
Pawel Zarembski 0:01f31e923fe2 410 break;
Pawel Zarembski 0:01f31e923fe2 411 case 3:
Pawel Zarembski 0:01f31e923fe2 412 break;
Pawel Zarembski 0:01f31e923fe2 413 }
Pawel Zarembski 0:01f31e923fe2 414 }
Pawel Zarembski 0:01f31e923fe2 415 SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> 16) & 0x7FF) + 1);
Pawel Zarembski 0:01f31e923fe2 416 SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> 0) & 0x0FF));
Pawel Zarembski 0:01f31e923fe2 417 break;
Pawel Zarembski 0:01f31e923fe2 418 case 3: /* UPLL clock */
Pawel Zarembski 0:01f31e923fe2 419 SystemCoreClock = OSC_CLK * 40;
Pawel Zarembski 0:01f31e923fe2 420 break;
Pawel Zarembski 0:01f31e923fe2 421 }
Pawel Zarembski 0:01f31e923fe2 422
Pawel Zarembski 0:01f31e923fe2 423 if (((PMC->PMC_MCKR >> 4) & 7) == 7)
Pawel Zarembski 0:01f31e923fe2 424 SystemCoreClock /= 6;
Pawel Zarembski 0:01f31e923fe2 425 else
Pawel Zarembski 0:01f31e923fe2 426 SystemCoreClock >>= ((PMC->PMC_MCKR >> 4) & 7);
Pawel Zarembski 0:01f31e923fe2 427
Pawel Zarembski 0:01f31e923fe2 428 }
Pawel Zarembski 0:01f31e923fe2 429
Pawel Zarembski 0:01f31e923fe2 430 /**
Pawel Zarembski 0:01f31e923fe2 431 * Initialize the system
Pawel Zarembski 0:01f31e923fe2 432 *
Pawel Zarembski 0:01f31e923fe2 433 * @param none
Pawel Zarembski 0:01f31e923fe2 434 * @return none
Pawel Zarembski 0:01f31e923fe2 435 *
Pawel Zarembski 0:01f31e923fe2 436 * @brief Setup the microcontroller system.
Pawel Zarembski 0:01f31e923fe2 437 * Initialize the System and update the SystemFrequency variable.
Pawel Zarembski 0:01f31e923fe2 438 */
Pawel Zarembski 0:01f31e923fe2 439 void SystemInit (void)
Pawel Zarembski 0:01f31e923fe2 440 {
Pawel Zarembski 0:01f31e923fe2 441 #if (EEFC0_SETUP == 1) /* Embedded Flash Controller 0 Setup */
Pawel Zarembski 0:01f31e923fe2 442 EFC0->EEFC_FMR = EEFC0_FMR_Val;
Pawel Zarembski 0:01f31e923fe2 443 #endif
Pawel Zarembski 0:01f31e923fe2 444
Pawel Zarembski 0:01f31e923fe2 445 #if (EEFC1_SETUP == 1) /* Embedded Flash Controller 1 Setup */
Pawel Zarembski 0:01f31e923fe2 446 #ifdef EFC1 /* some SAM3U devices do not have EFC1*/
Pawel Zarembski 0:01f31e923fe2 447 EFC1->EEFC_FMR = EEFC1_FMR_Val;
Pawel Zarembski 0:01f31e923fe2 448 #endif
Pawel Zarembski 0:01f31e923fe2 449 #endif
Pawel Zarembski 0:01f31e923fe2 450
Pawel Zarembski 0:01f31e923fe2 451 #if (PMC_SETUP == 1) /* Power Management Controller Setup */
Pawel Zarembski 0:01f31e923fe2 452
Pawel Zarembski 0:01f31e923fe2 453 PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */
Pawel Zarembski 0:01f31e923fe2 454
Pawel Zarembski 0:01f31e923fe2 455 #if (CKGR_UCKR_Val & (1 << 16)) /* If UPLL Enabled */
Pawel Zarembski 0:01f31e923fe2 456 PMC->CKGR_UCKR = CKGR_UCKR_Val;
Pawel Zarembski 0:01f31e923fe2 457 while (!(PMC->PMC_SR & (1 << 6))); /* Wait for LOCKU */
Pawel Zarembski 0:01f31e923fe2 458 #endif
Pawel Zarembski 0:01f31e923fe2 459
Pawel Zarembski 0:01f31e923fe2 460 #if (CKGR_MOR_Val & ((1<<3)|(1<<0))) /* If MOSCRCEN or MOSCXTEN set */
Pawel Zarembski 0:01f31e923fe2 461 PMC->CKGR_MOR = (PMC->CKGR_MOR & (1<<24)) | /* Keep the current MOSCSEL */
Pawel Zarembski 0:01f31e923fe2 462 (CKGR_MOR_Val & ~(1<<24)) | /* Set value except MOSCSEL */
Pawel Zarembski 0:01f31e923fe2 463 ((1<<3)|(1<<0)); /* and enable bothe OSC */
Pawel Zarembski 0:01f31e923fe2 464 #if (CKGR_MOR_Val & ((1 << 3)))
Pawel Zarembski 0:01f31e923fe2 465 while (!(PMC->PMC_SR & (1 << 17))); /* Wait for MOSCRCS */
Pawel Zarembski 0:01f31e923fe2 466 #endif
Pawel Zarembski 0:01f31e923fe2 467 #if (CKGR_MOR_Val & ((1 << 0)))
Pawel Zarembski 0:01f31e923fe2 468 while (!(PMC->PMC_SR & (1 << 0))); /* Wait for MOSCXTS */
Pawel Zarembski 0:01f31e923fe2 469 #endif
Pawel Zarembski 0:01f31e923fe2 470 PMC->CKGR_MOR = CKGR_MOR_Val; /* set the desired selection */
Pawel Zarembski 0:01f31e923fe2 471 while (!(PMC->PMC_SR & (1 << 16))); /* Wait for MOSCSELS */
Pawel Zarembski 0:01f31e923fe2 472 #endif
Pawel Zarembski 0:01f31e923fe2 473
Pawel Zarembski 0:01f31e923fe2 474 #if (CKGR_PLLAR_Val & ((0x7FF<<16))) /* If MULA != 0 */
Pawel Zarembski 0:01f31e923fe2 475 PMC->CKGR_PLLAR = CKGR_PLLAR_Val;
Pawel Zarembski 0:01f31e923fe2 476 while (!(PMC->PMC_SR & (1 << 1))); /* Wait for LOCKA */
Pawel Zarembski 0:01f31e923fe2 477 #endif
Pawel Zarembski 0:01f31e923fe2 478
Pawel Zarembski 0:01f31e923fe2 479 if ((PMC_MCKR_Val & 0x03) >= 2) {
Pawel Zarembski 0:01f31e923fe2 480 /* Write PRES field only */
Pawel Zarembski 0:01f31e923fe2 481 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x70) | (PMC_MCKR_Val & 0x70);
Pawel Zarembski 0:01f31e923fe2 482 } else {
Pawel Zarembski 0:01f31e923fe2 483 /* Write CSS field only */
Pawel Zarembski 0:01f31e923fe2 484 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x03) | (PMC_MCKR_Val & 0x03);
Pawel Zarembski 0:01f31e923fe2 485 }
Pawel Zarembski 0:01f31e923fe2 486 while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */
Pawel Zarembski 0:01f31e923fe2 487 PMC->PMC_MCKR = PMC_MCKR_Val; /* Write all MCKR */
Pawel Zarembski 0:01f31e923fe2 488 while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */
Pawel Zarembski 0:01f31e923fe2 489
Pawel Zarembski 0:01f31e923fe2 490 #if (PMC_PCK0_Val)
Pawel Zarembski 0:01f31e923fe2 491 PMC->PMC_PCKR[0] = PMC_PCK0_Val; /* Write PCK0 */
Pawel Zarembski 0:01f31e923fe2 492 while (!(PMC->PMC_SR & (1 << 8))); /* Wait for PCKRDY0 */
Pawel Zarembski 0:01f31e923fe2 493 #endif
Pawel Zarembski 0:01f31e923fe2 494 #if (PMC_PCK1_Val)
Pawel Zarembski 0:01f31e923fe2 495 PMC->PMC_PCKR[1] = PMC_PCK1_Val; /* Write PCK1 */
Pawel Zarembski 0:01f31e923fe2 496 while (!(PMC->PMC_SR & (1 << 9))); /* Wait for PCKRDY1 */
Pawel Zarembski 0:01f31e923fe2 497 #endif
Pawel Zarembski 0:01f31e923fe2 498 #if (PMC_PCK2_Val)
Pawel Zarembski 0:01f31e923fe2 499 PMC->PMC_PCKR[2] = PMC_PCK2_Val; /* Write PCK2 */
Pawel Zarembski 0:01f31e923fe2 500 while (!(PMC->PMC_SR & (1 << 10))); /* Wait for PCKRDY2 */
Pawel Zarembski 0:01f31e923fe2 501 #endif
Pawel Zarembski 0:01f31e923fe2 502
Pawel Zarembski 0:01f31e923fe2 503 PMC->PMC_SCER = PMC_SCER_Val;
Pawel Zarembski 0:01f31e923fe2 504 PMC->PMC_PCER0 = PMC_PCER_Val;
Pawel Zarembski 0:01f31e923fe2 505
Pawel Zarembski 0:01f31e923fe2 506 PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */
Pawel Zarembski 0:01f31e923fe2 507 #endif
Pawel Zarembski 0:01f31e923fe2 508
Pawel Zarembski 0:01f31e923fe2 509 #if (WDT_SETUP == 1) /* Watchdog Setup */
Pawel Zarembski 0:01f31e923fe2 510 WDT->WDT_MR = WDT_MR_WDDIS;
Pawel Zarembski 0:01f31e923fe2 511 #endif
Pawel Zarembski 0:01f31e923fe2 512 }