Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/sam3u2c.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U2C_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U2C_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /** \addtogroup SAM3U2C_definitions SAM3U2C definitions
Pawel Zarembski 0:01f31e923fe2 34 This file defines all structures and symbols for SAM3U2C:
Pawel Zarembski 0:01f31e923fe2 35 - registers and bitfields
Pawel Zarembski 0:01f31e923fe2 36 - peripheral base address
Pawel Zarembski 0:01f31e923fe2 37 - peripheral ID
Pawel Zarembski 0:01f31e923fe2 38 - PIO definitions
Pawel Zarembski 0:01f31e923fe2 39 */
Pawel Zarembski 0:01f31e923fe2 40 /*@{*/
Pawel Zarembski 0:01f31e923fe2 41
Pawel Zarembski 0:01f31e923fe2 42 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 43 extern "C" {
Pawel Zarembski 0:01f31e923fe2 44 #endif
Pawel Zarembski 0:01f31e923fe2 45
Pawel Zarembski 0:01f31e923fe2 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 47 #include "stdint.h"
Pawel Zarembski 0:01f31e923fe2 48 #ifndef __cplusplus
Pawel Zarembski 0:01f31e923fe2 49 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
Pawel Zarembski 0:01f31e923fe2 50 #else
Pawel Zarembski 0:01f31e923fe2 51 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
Pawel Zarembski 0:01f31e923fe2 52 #endif
Pawel Zarembski 0:01f31e923fe2 53 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
Pawel Zarembski 0:01f31e923fe2 54 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
Pawel Zarembski 0:01f31e923fe2 55 #endif
Pawel Zarembski 0:01f31e923fe2 56
Pawel Zarembski 0:01f31e923fe2 57 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 58 /* CMSIS DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 59 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 60 /** \addtogroup SAM3U2C_cmsis CMSIS Definitions */
Pawel Zarembski 0:01f31e923fe2 61 /*@{*/
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 /**< Interrupt Number Definition */
Pawel Zarembski 0:01f31e923fe2 64 typedef enum IRQn
Pawel Zarembski 0:01f31e923fe2 65 {
Pawel Zarembski 0:01f31e923fe2 66 /****** Cortex-M3 Processor Exceptions Numbers ******************************/
Pawel Zarembski 0:01f31e923fe2 67 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
Pawel Zarembski 0:01f31e923fe2 68 MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
Pawel Zarembski 0:01f31e923fe2 69 BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
Pawel Zarembski 0:01f31e923fe2 70 UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
Pawel Zarembski 0:01f31e923fe2 71 SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
Pawel Zarembski 0:01f31e923fe2 72 DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
Pawel Zarembski 0:01f31e923fe2 73 PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
Pawel Zarembski 0:01f31e923fe2 74 SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
Pawel Zarembski 0:01f31e923fe2 75 /****** SAM3U2C specific Interrupt Numbers *********************************/
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 SUPC_IRQn = 0, /**< 0 SAM3U2C Supply Controller (SUPC) */
Pawel Zarembski 0:01f31e923fe2 78 RSTC_IRQn = 1, /**< 1 SAM3U2C Reset Controller (RSTC) */
Pawel Zarembski 0:01f31e923fe2 79 RTC_IRQn = 2, /**< 2 SAM3U2C Real Time Clock (RTC) */
Pawel Zarembski 0:01f31e923fe2 80 RTT_IRQn = 3, /**< 3 SAM3U2C Real Time Timer (RTT) */
Pawel Zarembski 0:01f31e923fe2 81 WDT_IRQn = 4, /**< 4 SAM3U2C Watchdog Timer (WDT) */
Pawel Zarembski 0:01f31e923fe2 82 PMC_IRQn = 5, /**< 5 SAM3U2C Power Management Controller (PMC) */
Pawel Zarembski 0:01f31e923fe2 83 EFC0_IRQn = 6, /**< 6 SAM3U2C Enhanced Embedded Flash Controller 0 (EFC0) */
Pawel Zarembski 0:01f31e923fe2 84 UART_IRQn = 8, /**< 8 SAM3U2C Universal Asynchronous Receiver Transmitter (UART) */
Pawel Zarembski 0:01f31e923fe2 85 SMC_IRQn = 9, /**< 9 SAM3U2C Static Memory Controller (SMC) */
Pawel Zarembski 0:01f31e923fe2 86 PIOA_IRQn = 10, /**< 10 SAM3U2C Parallel I/O Controller A, (PIOA) */
Pawel Zarembski 0:01f31e923fe2 87 PIOB_IRQn = 11, /**< 11 SAM3U2C Parallel I/O Controller B (PIOB) */
Pawel Zarembski 0:01f31e923fe2 88 USART0_IRQn = 13, /**< 13 SAM3U2C USART 0 (USART0) */
Pawel Zarembski 0:01f31e923fe2 89 USART1_IRQn = 14, /**< 14 SAM3U2C USART 1 (USART1) */
Pawel Zarembski 0:01f31e923fe2 90 USART2_IRQn = 15, /**< 15 SAM3U2C USART 2 (USART2) */
Pawel Zarembski 0:01f31e923fe2 91 HSMCI_IRQn = 17, /**< 17 SAM3U2C High Speed Multimedia Card Interface (HSMCI) */
Pawel Zarembski 0:01f31e923fe2 92 TWI0_IRQn = 18, /**< 18 SAM3U2C Two-Wire Interface 0 (TWI0) */
Pawel Zarembski 0:01f31e923fe2 93 TWI1_IRQn = 19, /**< 19 SAM3U2C Two-Wire Interface 1 (TWI1) */
Pawel Zarembski 0:01f31e923fe2 94 SPI_IRQn = 20, /**< 20 SAM3U2C Serial Peripheral Interface (SPI) */
Pawel Zarembski 0:01f31e923fe2 95 SSC_IRQn = 21, /**< 21 SAM3U2C Synchronous Serial Controller (SSC) */
Pawel Zarembski 0:01f31e923fe2 96 TC0_IRQn = 22, /**< 22 SAM3U2C Timer Counter 0 (TC0) */
Pawel Zarembski 0:01f31e923fe2 97 TC1_IRQn = 23, /**< 23 SAM3U2C Timer Counter 1 (TC1) */
Pawel Zarembski 0:01f31e923fe2 98 TC2_IRQn = 24, /**< 24 SAM3U2C Timer Counter 2 (TC2) */
Pawel Zarembski 0:01f31e923fe2 99 PWM_IRQn = 25, /**< 25 SAM3U2C Pulse Width Modulation Controller (PWM) */
Pawel Zarembski 0:01f31e923fe2 100 ADC12B_IRQn = 26, /**< 26 SAM3U2C 12-bit ADC Controller (ADC12B) */
Pawel Zarembski 0:01f31e923fe2 101 ADC_IRQn = 27, /**< 27 SAM3U2C 10-bit ADC Controller (ADC) */
Pawel Zarembski 0:01f31e923fe2 102 DMAC_IRQn = 28, /**< 28 SAM3U2C DMA Controller (DMAC) */
Pawel Zarembski 0:01f31e923fe2 103 UDPHS_IRQn = 29, /**< 29 SAM3U2C USB Device High Speed (UDPHS) */
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 PERIPH_COUNT_IRQn = 30 /**< Number of peripheral IDs */
Pawel Zarembski 0:01f31e923fe2 106 } IRQn_Type;
Pawel Zarembski 0:01f31e923fe2 107
Pawel Zarembski 0:01f31e923fe2 108 typedef struct _DeviceVectors
Pawel Zarembski 0:01f31e923fe2 109 {
Pawel Zarembski 0:01f31e923fe2 110 /* Stack pointer */
Pawel Zarembski 0:01f31e923fe2 111 void* pvStack;
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 /* Cortex-M handlers */
Pawel Zarembski 0:01f31e923fe2 114 void* pfnReset_Handler;
Pawel Zarembski 0:01f31e923fe2 115 void* pfnNMI_Handler;
Pawel Zarembski 0:01f31e923fe2 116 void* pfnHardFault_Handler;
Pawel Zarembski 0:01f31e923fe2 117 void* pfnMemManage_Handler;
Pawel Zarembski 0:01f31e923fe2 118 void* pfnBusFault_Handler;
Pawel Zarembski 0:01f31e923fe2 119 void* pfnUsageFault_Handler;
Pawel Zarembski 0:01f31e923fe2 120 void* pfnReserved1_Handler;
Pawel Zarembski 0:01f31e923fe2 121 void* pfnReserved2_Handler;
Pawel Zarembski 0:01f31e923fe2 122 void* pfnReserved3_Handler;
Pawel Zarembski 0:01f31e923fe2 123 void* pfnReserved4_Handler;
Pawel Zarembski 0:01f31e923fe2 124 void* pfnSVC_Handler;
Pawel Zarembski 0:01f31e923fe2 125 void* pfnDebugMon_Handler;
Pawel Zarembski 0:01f31e923fe2 126 void* pfnReserved5_Handler;
Pawel Zarembski 0:01f31e923fe2 127 void* pfnPendSV_Handler;
Pawel Zarembski 0:01f31e923fe2 128 void* pfnSysTick_Handler;
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 /* Peripheral handlers */
Pawel Zarembski 0:01f31e923fe2 131 void* pfnSUPC_Handler; /* 0 Supply Controller */
Pawel Zarembski 0:01f31e923fe2 132 void* pfnRSTC_Handler; /* 1 Reset Controller */
Pawel Zarembski 0:01f31e923fe2 133 void* pfnRTC_Handler; /* 2 Real Time Clock */
Pawel Zarembski 0:01f31e923fe2 134 void* pfnRTT_Handler; /* 3 Real Time Timer */
Pawel Zarembski 0:01f31e923fe2 135 void* pfnWDT_Handler; /* 4 Watchdog Timer */
Pawel Zarembski 0:01f31e923fe2 136 void* pfnPMC_Handler; /* 5 Power Management Controller */
Pawel Zarembski 0:01f31e923fe2 137 void* pfnEFC0_Handler; /* 6 Enhanced Embedded Flash Controller 0 */
Pawel Zarembski 0:01f31e923fe2 138 void* pvReserved7;
Pawel Zarembski 0:01f31e923fe2 139 void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transmitter */
Pawel Zarembski 0:01f31e923fe2 140 void* pfnSMC_Handler; /* 9 Static Memory Controller */
Pawel Zarembski 0:01f31e923fe2 141 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A, */
Pawel Zarembski 0:01f31e923fe2 142 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
Pawel Zarembski 0:01f31e923fe2 143 void* pvReserved12;
Pawel Zarembski 0:01f31e923fe2 144 void* pfnUSART0_Handler; /* 13 USART 0 */
Pawel Zarembski 0:01f31e923fe2 145 void* pfnUSART1_Handler; /* 14 USART 1 */
Pawel Zarembski 0:01f31e923fe2 146 void* pfnUSART2_Handler; /* 15 USART 2 */
Pawel Zarembski 0:01f31e923fe2 147 void* pvReserved16;
Pawel Zarembski 0:01f31e923fe2 148 void* pfnHSMCI_Handler; /* 17 High Speed Multimedia Card Interface */
Pawel Zarembski 0:01f31e923fe2 149 void* pfnTWI0_Handler; /* 18 Two-Wire Interface 0 */
Pawel Zarembski 0:01f31e923fe2 150 void* pfnTWI1_Handler; /* 19 Two-Wire Interface 1 */
Pawel Zarembski 0:01f31e923fe2 151 void* pfnSPI_Handler; /* 20 Serial Peripheral Interface */
Pawel Zarembski 0:01f31e923fe2 152 void* pfnSSC_Handler; /* 21 Synchronous Serial Controller */
Pawel Zarembski 0:01f31e923fe2 153 void* pfnTC0_Handler; /* 22 Timer Counter 0 */
Pawel Zarembski 0:01f31e923fe2 154 void* pfnTC1_Handler; /* 23 Timer Counter 1 */
Pawel Zarembski 0:01f31e923fe2 155 void* pfnTC2_Handler; /* 24 Timer Counter 2 */
Pawel Zarembski 0:01f31e923fe2 156 void* pfnPWM_Handler; /* 25 Pulse Width Modulation Controller */
Pawel Zarembski 0:01f31e923fe2 157 void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
Pawel Zarembski 0:01f31e923fe2 158 void* pfnADC_Handler; /* 27 10-bit ADC Controller */
Pawel Zarembski 0:01f31e923fe2 159 void* pfnDMAC_Handler; /* 28 DMA Controller */
Pawel Zarembski 0:01f31e923fe2 160 void* pfnUDPHS_Handler; /* 29 USB Device High Speed */
Pawel Zarembski 0:01f31e923fe2 161 } DeviceVectors;
Pawel Zarembski 0:01f31e923fe2 162
Pawel Zarembski 0:01f31e923fe2 163 /* Cortex-M3 core handlers */
Pawel Zarembski 0:01f31e923fe2 164 void Reset_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 165 void NMI_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 166 void HardFault_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 167 void MemManage_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 168 void BusFault_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 169 void UsageFault_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 170 void SVC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 171 void DebugMon_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 172 void PendSV_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 173 void SysTick_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 /* Peripherals handlers */
Pawel Zarembski 0:01f31e923fe2 176 void ADC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 177 void ADC12B_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 178 void DMAC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 179 void EFC0_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 180 void HSMCI_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 181 void PIOA_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 182 void PIOB_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 183 void PMC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 184 void PWM_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 185 void RSTC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 186 void RTC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 187 void RTT_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 188 void SMC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 189 void SPI_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 190 void SSC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 191 void SUPC_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 192 void TC0_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 193 void TC1_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 194 void TC2_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 195 void TWI0_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 196 void TWI1_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 197 void UART_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 198 void UDPHS_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 199 void USART0_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 200 void USART1_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 201 void USART2_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 202 void WDT_Handler ( void );
Pawel Zarembski 0:01f31e923fe2 203
Pawel Zarembski 0:01f31e923fe2 204 /**
Pawel Zarembski 0:01f31e923fe2 205 * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
Pawel Zarembski 0:01f31e923fe2 206 */
Pawel Zarembski 0:01f31e923fe2 207
Pawel Zarembski 0:01f31e923fe2 208 #define __CM3_REV 0x0200 /**< SAM3U2C core revision number ([15:8] revision number, [7:0] patch number) */
Pawel Zarembski 0:01f31e923fe2 209 #define __MPU_PRESENT 1 /**< SAM3U2C does provide a MPU */
Pawel Zarembski 0:01f31e923fe2 210 #define __NVIC_PRIO_BITS 4 /**< SAM3U2C uses 4 Bits for the Priority Levels */
Pawel Zarembski 0:01f31e923fe2 211 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
Pawel Zarembski 0:01f31e923fe2 212
Pawel Zarembski 0:01f31e923fe2 213 /*
Pawel Zarembski 0:01f31e923fe2 214 * \brief CMSIS includes
Pawel Zarembski 0:01f31e923fe2 215 */
Pawel Zarembski 0:01f31e923fe2 216
Pawel Zarembski 0:01f31e923fe2 217 #include "core_cm3.h"
Pawel Zarembski 0:01f31e923fe2 218 #if !defined DONT_USE_CMSIS_INIT
Pawel Zarembski 0:01f31e923fe2 219 #include "system_SAM3U.h"
Pawel Zarembski 0:01f31e923fe2 220 #endif /* DONT_USE_CMSIS_INIT */
Pawel Zarembski 0:01f31e923fe2 221
Pawel Zarembski 0:01f31e923fe2 222 /*@}*/
Pawel Zarembski 0:01f31e923fe2 223
Pawel Zarembski 0:01f31e923fe2 224 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 225 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 226 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 227 /** \addtogroup SAM3U2C_api Peripheral Software API */
Pawel Zarembski 0:01f31e923fe2 228 /*@{*/
Pawel Zarembski 0:01f31e923fe2 229
Pawel Zarembski 0:01f31e923fe2 230 #include "component/adc.h"
Pawel Zarembski 0:01f31e923fe2 231 #include "component/adc12b.h"
Pawel Zarembski 0:01f31e923fe2 232 #include "component/chipid.h"
Pawel Zarembski 0:01f31e923fe2 233 #include "component/dmac.h"
Pawel Zarembski 0:01f31e923fe2 234 #include "component/efc.h"
Pawel Zarembski 0:01f31e923fe2 235 #include "component/gpbr.h"
Pawel Zarembski 0:01f31e923fe2 236 #include "component/hsmci.h"
Pawel Zarembski 0:01f31e923fe2 237 #include "component/matrix.h"
Pawel Zarembski 0:01f31e923fe2 238 #include "component/pdc.h"
Pawel Zarembski 0:01f31e923fe2 239 #include "component/pio.h"
Pawel Zarembski 0:01f31e923fe2 240 #include "component/pmc.h"
Pawel Zarembski 0:01f31e923fe2 241 #include "component/pwm.h"
Pawel Zarembski 0:01f31e923fe2 242 #include "component/rstc.h"
Pawel Zarembski 0:01f31e923fe2 243 #include "component/rtc.h"
Pawel Zarembski 0:01f31e923fe2 244 #include "component/rtt.h"
Pawel Zarembski 0:01f31e923fe2 245 #include "component/smc.h"
Pawel Zarembski 0:01f31e923fe2 246 #include "component/spi.h"
Pawel Zarembski 0:01f31e923fe2 247 #include "component/ssc.h"
Pawel Zarembski 0:01f31e923fe2 248 #include "component/supc.h"
Pawel Zarembski 0:01f31e923fe2 249 #include "component/tc.h"
Pawel Zarembski 0:01f31e923fe2 250 #include "component/twi.h"
Pawel Zarembski 0:01f31e923fe2 251 #include "component/uart.h"
Pawel Zarembski 0:01f31e923fe2 252 #include "component/udphs.h"
Pawel Zarembski 0:01f31e923fe2 253 #include "component/usart.h"
Pawel Zarembski 0:01f31e923fe2 254 #include "component/wdt.h"
Pawel Zarembski 0:01f31e923fe2 255 /*@}*/
Pawel Zarembski 0:01f31e923fe2 256
Pawel Zarembski 0:01f31e923fe2 257 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 258 /* REGISTER ACCESS DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 259 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 260 /** \addtogroup SAM3U2C_reg Registers Access Definitions */
Pawel Zarembski 0:01f31e923fe2 261 /*@{*/
Pawel Zarembski 0:01f31e923fe2 262
Pawel Zarembski 0:01f31e923fe2 263 #include "instance/hsmci.h"
Pawel Zarembski 0:01f31e923fe2 264 #include "instance/ssc.h"
Pawel Zarembski 0:01f31e923fe2 265 #include "instance/spi.h"
Pawel Zarembski 0:01f31e923fe2 266 #include "instance/tc0.h"
Pawel Zarembski 0:01f31e923fe2 267 #include "instance/twi0.h"
Pawel Zarembski 0:01f31e923fe2 268 #include "instance/twi1.h"
Pawel Zarembski 0:01f31e923fe2 269 #include "instance/pwm.h"
Pawel Zarembski 0:01f31e923fe2 270 #include "instance/usart0.h"
Pawel Zarembski 0:01f31e923fe2 271 #include "instance/usart1.h"
Pawel Zarembski 0:01f31e923fe2 272 #include "instance/usart2.h"
Pawel Zarembski 0:01f31e923fe2 273 #include "instance/udphs.h"
Pawel Zarembski 0:01f31e923fe2 274 #include "instance/adc12b.h"
Pawel Zarembski 0:01f31e923fe2 275 #include "instance/adc.h"
Pawel Zarembski 0:01f31e923fe2 276 #include "instance/dmac.h"
Pawel Zarembski 0:01f31e923fe2 277 #include "instance/smc.h"
Pawel Zarembski 0:01f31e923fe2 278 #include "instance/matrix.h"
Pawel Zarembski 0:01f31e923fe2 279 #include "instance/pmc.h"
Pawel Zarembski 0:01f31e923fe2 280 #include "instance/uart.h"
Pawel Zarembski 0:01f31e923fe2 281 #include "instance/chipid.h"
Pawel Zarembski 0:01f31e923fe2 282 #include "instance/efc0.h"
Pawel Zarembski 0:01f31e923fe2 283 #include "instance/pioa.h"
Pawel Zarembski 0:01f31e923fe2 284 #include "instance/piob.h"
Pawel Zarembski 0:01f31e923fe2 285 #include "instance/rstc.h"
Pawel Zarembski 0:01f31e923fe2 286 #include "instance/supc.h"
Pawel Zarembski 0:01f31e923fe2 287 #include "instance/rtt.h"
Pawel Zarembski 0:01f31e923fe2 288 #include "instance/wdt.h"
Pawel Zarembski 0:01f31e923fe2 289 #include "instance/rtc.h"
Pawel Zarembski 0:01f31e923fe2 290 #include "instance/gpbr.h"
Pawel Zarembski 0:01f31e923fe2 291 /*@}*/
Pawel Zarembski 0:01f31e923fe2 292
Pawel Zarembski 0:01f31e923fe2 293 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 294 /* PERIPHERAL ID DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 295 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 296 /** \addtogroup SAM3U2C_id Peripheral Ids Definitions */
Pawel Zarembski 0:01f31e923fe2 297 /*@{*/
Pawel Zarembski 0:01f31e923fe2 298
Pawel Zarembski 0:01f31e923fe2 299 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
Pawel Zarembski 0:01f31e923fe2 300 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
Pawel Zarembski 0:01f31e923fe2 301 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
Pawel Zarembski 0:01f31e923fe2 302 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
Pawel Zarembski 0:01f31e923fe2 303 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
Pawel Zarembski 0:01f31e923fe2 304 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
Pawel Zarembski 0:01f31e923fe2 305 #define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
Pawel Zarembski 0:01f31e923fe2 306 #define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
Pawel Zarembski 0:01f31e923fe2 307 #define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
Pawel Zarembski 0:01f31e923fe2 308 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
Pawel Zarembski 0:01f31e923fe2 309 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
Pawel Zarembski 0:01f31e923fe2 310 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
Pawel Zarembski 0:01f31e923fe2 311 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
Pawel Zarembski 0:01f31e923fe2 312 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
Pawel Zarembski 0:01f31e923fe2 313 #define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
Pawel Zarembski 0:01f31e923fe2 314 #define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
Pawel Zarembski 0:01f31e923fe2 315 #define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
Pawel Zarembski 0:01f31e923fe2 316 #define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
Pawel Zarembski 0:01f31e923fe2 317 #define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
Pawel Zarembski 0:01f31e923fe2 318 #define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
Pawel Zarembski 0:01f31e923fe2 319 #define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
Pawel Zarembski 0:01f31e923fe2 320 #define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
Pawel Zarembski 0:01f31e923fe2 321 #define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
Pawel Zarembski 0:01f31e923fe2 322 #define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
Pawel Zarembski 0:01f31e923fe2 323 #define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
Pawel Zarembski 0:01f31e923fe2 324 #define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
Pawel Zarembski 0:01f31e923fe2 325 #define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
Pawel Zarembski 0:01f31e923fe2 326
Pawel Zarembski 0:01f31e923fe2 327 #define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
Pawel Zarembski 0:01f31e923fe2 328 /*@}*/
Pawel Zarembski 0:01f31e923fe2 329
Pawel Zarembski 0:01f31e923fe2 330 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 331 /* BASE ADDRESS DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 332 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 333 /** \addtogroup SAM3U2C_base Peripheral Base Address Definitions */
Pawel Zarembski 0:01f31e923fe2 334 /*@{*/
Pawel Zarembski 0:01f31e923fe2 335
Pawel Zarembski 0:01f31e923fe2 336 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 337 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
Pawel Zarembski 0:01f31e923fe2 338 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 339 #define SPI (0x40008000U) /**< \brief (SPI ) Base Address */
Pawel Zarembski 0:01f31e923fe2 340 #define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 341 #define TWI0 (0x40084000U) /**< \brief (TWI0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 342 #define PDC_TWI0 (0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 343 #define TWI1 (0x40088000U) /**< \brief (TWI1 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 344 #define PDC_TWI1 (0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 345 #define PWM (0x4008C000U) /**< \brief (PWM ) Base Address */
Pawel Zarembski 0:01f31e923fe2 346 #define PDC_PWM (0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
Pawel Zarembski 0:01f31e923fe2 347 #define USART0 (0x40090000U) /**< \brief (USART0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 348 #define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
Pawel Zarembski 0:01f31e923fe2 349 #define USART1 (0x40094000U) /**< \brief (USART1 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 350 #define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
Pawel Zarembski 0:01f31e923fe2 351 #define USART2 (0x40098000U) /**< \brief (USART2 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 352 #define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
Pawel Zarembski 0:01f31e923fe2 353 #define UDPHS (0x400A4000U) /**< \brief (UDPHS ) Base Address */
Pawel Zarembski 0:01f31e923fe2 354 #define ADC12B (0x400A8000U) /**< \brief (ADC12B ) Base Address */
Pawel Zarembski 0:01f31e923fe2 355 #define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
Pawel Zarembski 0:01f31e923fe2 356 #define ADC (0x400AC000U) /**< \brief (ADC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 357 #define PDC_ADC (0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 358 #define DMAC (0x400B0000U) /**< \brief (DMAC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 359 #define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 360 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
Pawel Zarembski 0:01f31e923fe2 361 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 362 #define UART (0x400E0600U) /**< \brief (UART ) Base Address */
Pawel Zarembski 0:01f31e923fe2 363 #define PDC_UART (0x400E0700U) /**< \brief (PDC_UART ) Base Address */
Pawel Zarembski 0:01f31e923fe2 364 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
Pawel Zarembski 0:01f31e923fe2 365 #define EFC0 (0x400E0800U) /**< \brief (EFC0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 366 #define PIOA (0x400E0C00U) /**< \brief (PIOA ) Base Address */
Pawel Zarembski 0:01f31e923fe2 367 #define PIOB (0x400E0E00U) /**< \brief (PIOB ) Base Address */
Pawel Zarembski 0:01f31e923fe2 368 #define RSTC (0x400E1200U) /**< \brief (RSTC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 369 #define SUPC (0x400E1210U) /**< \brief (SUPC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 370 #define RTT (0x400E1230U) /**< \brief (RTT ) Base Address */
Pawel Zarembski 0:01f31e923fe2 371 #define WDT (0x400E1250U) /**< \brief (WDT ) Base Address */
Pawel Zarembski 0:01f31e923fe2 372 #define RTC (0x400E1260U) /**< \brief (RTC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 373 #define GPBR (0x400E1290U) /**< \brief (GPBR ) Base Address */
Pawel Zarembski 0:01f31e923fe2 374 #else
Pawel Zarembski 0:01f31e923fe2 375 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
Pawel Zarembski 0:01f31e923fe2 376 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 377 #define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */
Pawel Zarembski 0:01f31e923fe2 378 #define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 379 #define TWI0 ((Twi *)0x40084000U) /**< \brief (TWI0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 380 #define PDC_TWI0 ((Pdc *)0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 381 #define TWI1 ((Twi *)0x40088000U) /**< \brief (TWI1 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 382 #define PDC_TWI1 ((Pdc *)0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 383 #define PWM ((Pwm *)0x4008C000U) /**< \brief (PWM ) Base Address */
Pawel Zarembski 0:01f31e923fe2 384 #define PDC_PWM ((Pdc *)0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
Pawel Zarembski 0:01f31e923fe2 385 #define USART0 ((Usart *)0x40090000U) /**< \brief (USART0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 386 #define PDC_USART0 ((Pdc *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
Pawel Zarembski 0:01f31e923fe2 387 #define USART1 ((Usart *)0x40094000U) /**< \brief (USART1 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 388 #define PDC_USART1 ((Pdc *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
Pawel Zarembski 0:01f31e923fe2 389 #define USART2 ((Usart *)0x40098000U) /**< \brief (USART2 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 390 #define PDC_USART2 ((Pdc *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
Pawel Zarembski 0:01f31e923fe2 391 #define UDPHS ((Udphs *)0x400A4000U) /**< \brief (UDPHS ) Base Address */
Pawel Zarembski 0:01f31e923fe2 392 #define ADC12B ((Adc12b *)0x400A8000U) /**< \brief (ADC12B ) Base Address */
Pawel Zarembski 0:01f31e923fe2 393 #define PDC_ADC12B ((Pdc *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
Pawel Zarembski 0:01f31e923fe2 394 #define ADC ((Adc *)0x400AC000U) /**< \brief (ADC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 395 #define PDC_ADC ((Pdc *)0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 396 #define DMAC ((Dmac *)0x400B0000U) /**< \brief (DMAC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 397 #define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 398 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
Pawel Zarembski 0:01f31e923fe2 399 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 400 #define UART ((Uart *)0x400E0600U) /**< \brief (UART ) Base Address */
Pawel Zarembski 0:01f31e923fe2 401 #define PDC_UART ((Pdc *)0x400E0700U) /**< \brief (PDC_UART ) Base Address */
Pawel Zarembski 0:01f31e923fe2 402 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
Pawel Zarembski 0:01f31e923fe2 403 #define EFC0 ((Efc *)0x400E0800U) /**< \brief (EFC0 ) Base Address */
Pawel Zarembski 0:01f31e923fe2 404 #define PIOA ((Pio *)0x400E0C00U) /**< \brief (PIOA ) Base Address */
Pawel Zarembski 0:01f31e923fe2 405 #define PIOB ((Pio *)0x400E0E00U) /**< \brief (PIOB ) Base Address */
Pawel Zarembski 0:01f31e923fe2 406 #define RSTC ((Rstc *)0x400E1200U) /**< \brief (RSTC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 407 #define SUPC ((Supc *)0x400E1210U) /**< \brief (SUPC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 408 #define RTT ((Rtt *)0x400E1230U) /**< \brief (RTT ) Base Address */
Pawel Zarembski 0:01f31e923fe2 409 #define WDT ((Wdt *)0x400E1250U) /**< \brief (WDT ) Base Address */
Pawel Zarembski 0:01f31e923fe2 410 #define RTC ((Rtc *)0x400E1260U) /**< \brief (RTC ) Base Address */
Pawel Zarembski 0:01f31e923fe2 411 #define GPBR ((Gpbr *)0x400E1290U) /**< \brief (GPBR ) Base Address */
Pawel Zarembski 0:01f31e923fe2 412 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 413 /*@}*/
Pawel Zarembski 0:01f31e923fe2 414
Pawel Zarembski 0:01f31e923fe2 415 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 416 /* PIO DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 417 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 418 /** \addtogroup SAM3U2C_pio Peripheral Pio Definitions */
Pawel Zarembski 0:01f31e923fe2 419 /*@{*/
Pawel Zarembski 0:01f31e923fe2 420
Pawel Zarembski 0:01f31e923fe2 421 #include "pio/sam3u2c.h"
Pawel Zarembski 0:01f31e923fe2 422 /*@}*/
Pawel Zarembski 0:01f31e923fe2 423
Pawel Zarembski 0:01f31e923fe2 424 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 425 /* MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 426 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 427
Pawel Zarembski 0:01f31e923fe2 428 #define IFLASH0_SIZE (0x20000u)
Pawel Zarembski 0:01f31e923fe2 429 #define IFLASH0_PAGE_SIZE (256u)
Pawel Zarembski 0:01f31e923fe2 430 #define IFLASH0_LOCK_REGION_SIZE (8192u)
Pawel Zarembski 0:01f31e923fe2 431 #define IFLASH0_NB_OF_PAGES (64u)
Pawel Zarembski 0:01f31e923fe2 432 #define IFLASH0_NB_OF_LOCK_BITS (32u)
Pawel Zarembski 0:01f31e923fe2 433 #define IRAM0_SIZE (0x4000u)
Pawel Zarembski 0:01f31e923fe2 434 #define IRAM1_SIZE (0x4000u)
Pawel Zarembski 0:01f31e923fe2 435 #define NFCRAM_SIZE (0x1000u)
Pawel Zarembski 0:01f31e923fe2 436 #define IFLASH_SIZE (IFLASH0_SIZE)
Pawel Zarembski 0:01f31e923fe2 437 #define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
Pawel Zarembski 0:01f31e923fe2 438
Pawel Zarembski 0:01f31e923fe2 439 #define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
Pawel Zarembski 0:01f31e923fe2 440 #define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
Pawel Zarembski 0:01f31e923fe2 441 #define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
Pawel Zarembski 0:01f31e923fe2 442 #define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
Pawel Zarembski 0:01f31e923fe2 443 #define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
Pawel Zarembski 0:01f31e923fe2 444 #define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
Pawel Zarembski 0:01f31e923fe2 445
Pawel Zarembski 0:01f31e923fe2 446 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 447 /* MISCELLANEOUS DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 448 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 449
Pawel Zarembski 0:01f31e923fe2 450 #define CHIP_JTAGID (0x05B2A01FUL)
Pawel Zarembski 0:01f31e923fe2 451 #define CHIP_CIDR (0x280A0760UL)
Pawel Zarembski 0:01f31e923fe2 452 #define CHIP_EXID (0x0UL)
Pawel Zarembski 0:01f31e923fe2 453
Pawel Zarembski 0:01f31e923fe2 454 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 455 /* ELECTRICAL DEFINITIONS FOR SAM3U2C */
Pawel Zarembski 0:01f31e923fe2 456 /* ************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 457
Pawel Zarembski 0:01f31e923fe2 458 /* Device characteristics */
Pawel Zarembski 0:01f31e923fe2 459 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
Pawel Zarembski 0:01f31e923fe2 460 #define CHIP_FREQ_SLCK_RC (32000UL)
Pawel Zarembski 0:01f31e923fe2 461 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
Pawel Zarembski 0:01f31e923fe2 462 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
Pawel Zarembski 0:01f31e923fe2 463 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
Pawel Zarembski 0:01f31e923fe2 464 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
Pawel Zarembski 0:01f31e923fe2 465 #define CHIP_FREQ_CPU_MAX (96000000UL)
Pawel Zarembski 0:01f31e923fe2 466 #define CHIP_FREQ_XTAL_32K (32768UL)
Pawel Zarembski 0:01f31e923fe2 467 #define CHIP_FREQ_XTAL_12M (12000000UL)
Pawel Zarembski 0:01f31e923fe2 468
Pawel Zarembski 0:01f31e923fe2 469 /* Embedded Flash Write Wait State */
Pawel Zarembski 0:01f31e923fe2 470 #define CHIP_FLASH_WRITE_WAIT_STATE (6U)
Pawel Zarembski 0:01f31e923fe2 471
Pawel Zarembski 0:01f31e923fe2 472 /* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
Pawel Zarembski 0:01f31e923fe2 473 #define CHIP_FREQ_FWS_0 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
Pawel Zarembski 0:01f31e923fe2 474 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
Pawel Zarembski 0:01f31e923fe2 475 #define CHIP_FREQ_FWS_2 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
Pawel Zarembski 0:01f31e923fe2 476 #define CHIP_FREQ_FWS_3 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
Pawel Zarembski 0:01f31e923fe2 477
Pawel Zarembski 0:01f31e923fe2 478 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 479 }
Pawel Zarembski 0:01f31e923fe2 480 #endif
Pawel Zarembski 0:01f31e923fe2 481
Pawel Zarembski 0:01f31e923fe2 482 /*@}*/
Pawel Zarembski 0:01f31e923fe2 483
Pawel Zarembski 0:01f31e923fe2 484 #endif /* _SAM3U2C_ */