Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/atmel/sam3u2c/instance/udphs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | /* Atmel Microcontroller Software Support */ |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | /* SAM Software Package License */ |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | /* Copyright (c) %copyright_year%, Atmel Corporation */ |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | /* All rights reserved. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | /* Redistribution and use in source and binary forms, with or without */ |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | /* modification, are permitted provided that the following condition is met: */ |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | /* this list of conditions and the disclaimer below. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | /* this software without specific prior written permission. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | /* */ |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | /* ---------------------------------------------------------------------------- */ |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | #ifndef _SAM3U_UDPHS_INSTANCE_ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | #define _SAM3U_UDPHS_INSTANCE_ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /* ========== Register definition for UDPHS peripheral ========== */ |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | #define REG_UDPHS_CTRL (0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | #define REG_UDPHS_FNUM (0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | #define REG_UDPHS_IEN (0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | #define REG_UDPHS_INTSTA (0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #define REG_UDPHS_CLRINT (0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | #define REG_UDPHS_EPTRST (0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | #define REG_UDPHS_TST (0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | #define REG_UDPHS_EPTCFG0 (0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | #define REG_UDPHS_EPTCTLENB0 (0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | #define REG_UDPHS_EPTCTLDIS0 (0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | #define REG_UDPHS_EPTCTL0 (0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | #define REG_UDPHS_EPTSETSTA0 (0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | #define REG_UDPHS_EPTCLRSTA0 (0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | #define REG_UDPHS_EPTSTA0 (0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | #define REG_UDPHS_EPTCFG1 (0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | #define REG_UDPHS_EPTCTLENB1 (0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | #define REG_UDPHS_EPTCTLDIS1 (0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | #define REG_UDPHS_EPTCTL1 (0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | #define REG_UDPHS_EPTSETSTA1 (0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | #define REG_UDPHS_EPTCLRSTA1 (0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | #define REG_UDPHS_EPTSTA1 (0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define REG_UDPHS_EPTCFG2 (0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | #define REG_UDPHS_EPTCTLENB2 (0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | #define REG_UDPHS_EPTCTLDIS2 (0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | #define REG_UDPHS_EPTCTL2 (0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | #define REG_UDPHS_EPTSETSTA2 (0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | #define REG_UDPHS_EPTCLRSTA2 (0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | #define REG_UDPHS_EPTSTA2 (0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | #define REG_UDPHS_EPTCFG3 (0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | #define REG_UDPHS_EPTCTLENB3 (0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | #define REG_UDPHS_EPTCTLDIS3 (0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | #define REG_UDPHS_EPTCTL3 (0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | #define REG_UDPHS_EPTSETSTA3 (0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | #define REG_UDPHS_EPTCLRSTA3 (0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | #define REG_UDPHS_EPTSTA3 (0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | #define REG_UDPHS_EPTCFG4 (0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | #define REG_UDPHS_EPTCTLENB4 (0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | #define REG_UDPHS_EPTCTLDIS4 (0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | #define REG_UDPHS_EPTCTL4 (0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | #define REG_UDPHS_EPTSETSTA4 (0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | #define REG_UDPHS_EPTCLRSTA4 (0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | #define REG_UDPHS_EPTSTA4 (0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | #define REG_UDPHS_EPTCFG5 (0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | #define REG_UDPHS_EPTCTLENB5 (0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | #define REG_UDPHS_EPTCTLDIS5 (0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | #define REG_UDPHS_EPTCTL5 (0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | #define REG_UDPHS_EPTSETSTA5 (0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | #define REG_UDPHS_EPTCLRSTA5 (0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | #define REG_UDPHS_EPTSTA5 (0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | #define REG_UDPHS_EPTCFG6 (0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | #define REG_UDPHS_EPTCTLENB6 (0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | #define REG_UDPHS_EPTCTLDIS6 (0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | #define REG_UDPHS_EPTCTL6 (0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | #define REG_UDPHS_EPTSETSTA6 (0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | #define REG_UDPHS_EPTCLRSTA6 (0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | #define REG_UDPHS_EPTSTA6 (0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | #define REG_UDPHS_DMANXTDSC0 (0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | #define REG_UDPHS_DMAADDRESS0 (0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | #define REG_UDPHS_DMACONTROL0 (0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | #define REG_UDPHS_DMASTATUS0 (0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | #define REG_UDPHS_DMANXTDSC1 (0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | #define REG_UDPHS_DMAADDRESS1 (0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | #define REG_UDPHS_DMACONTROL1 (0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | #define REG_UDPHS_DMASTATUS1 (0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | #define REG_UDPHS_DMANXTDSC2 (0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | #define REG_UDPHS_DMAADDRESS2 (0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | #define REG_UDPHS_DMACONTROL2 (0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | #define REG_UDPHS_DMASTATUS2 (0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | #define REG_UDPHS_DMANXTDSC3 (0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | #define REG_UDPHS_DMAADDRESS3 (0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | #define REG_UDPHS_DMACONTROL3 (0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | #define REG_UDPHS_DMASTATUS3 (0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define REG_UDPHS_DMANXTDSC4 (0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define REG_UDPHS_DMAADDRESS4 (0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define REG_UDPHS_DMACONTROL4 (0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define REG_UDPHS_DMASTATUS4 (0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define REG_UDPHS_DMANXTDSC5 (0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define REG_UDPHS_DMAADDRESS5 (0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define REG_UDPHS_DMACONTROL5 (0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define REG_UDPHS_DMASTATUS5 (0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #else |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define REG_UDPHS_CTRL (*(RwReg*)0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define REG_UDPHS_FNUM (*(RoReg*)0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define REG_UDPHS_IEN (*(RwReg*)0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | #define REG_UDPHS_INTSTA (*(RoReg*)0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define REG_UDPHS_CLRINT (*(WoReg*)0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define REG_UDPHS_EPTRST (*(WoReg*)0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define REG_UDPHS_TST (*(RwReg*)0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define REG_UDPHS_EPTCFG0 (*(RwReg*)0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define REG_UDPHS_EPTCTL0 (*(RoReg*)0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | #define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | #define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define REG_UDPHS_EPTSTA0 (*(RoReg*)0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define REG_UDPHS_EPTCFG1 (*(RwReg*)0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | #define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define REG_UDPHS_EPTCTL1 (*(RoReg*)0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | #define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define REG_UDPHS_EPTSTA1 (*(RoReg*)0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define REG_UDPHS_EPTCFG2 (*(RwReg*)0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define REG_UDPHS_EPTCTL2 (*(RoReg*)0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | #define REG_UDPHS_EPTSTA2 (*(RoReg*)0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define REG_UDPHS_EPTCFG3 (*(RwReg*)0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define REG_UDPHS_EPTCTL3 (*(RoReg*)0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | #define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | #define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | #define REG_UDPHS_EPTSTA3 (*(RoReg*)0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | #define REG_UDPHS_EPTCFG4 (*(RwReg*)0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | #define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | #define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define REG_UDPHS_EPTCTL4 (*(RoReg*)0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define REG_UDPHS_EPTSTA4 (*(RoReg*)0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define REG_UDPHS_EPTCFG5 (*(RwReg*)0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define REG_UDPHS_EPTCTL5 (*(RoReg*)0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define REG_UDPHS_EPTSTA5 (*(RoReg*)0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define REG_UDPHS_EPTCFG6 (*(RwReg*)0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define REG_UDPHS_EPTCTL6 (*(RoReg*)0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | #define REG_UDPHS_EPTSTA6 (*(RoReg*)0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | #define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | #define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | #define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | #define REG_UDPHS_DMASTATUS0 (*(RwReg*)0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | #define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | #define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define REG_UDPHS_DMASTATUS1 (*(RwReg*)0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define REG_UDPHS_DMASTATUS2 (*(RwReg*)0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define REG_UDPHS_DMASTATUS3 (*(RwReg*)0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define REG_UDPHS_DMASTATUS4 (*(RwReg*)0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | #define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | #define REG_UDPHS_DMASTATUS5 (*(RwReg*)0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | #endif /* _SAM3U_UDPHS_INSTANCE_ */ |