Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/spi.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_SPI_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_SPI_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_SPI Serial Peripheral Interface */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Spi hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
Pawel Zarembski 0:01f31e923fe2 44 RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
Pawel Zarembski 0:01f31e923fe2 45 WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
Pawel Zarembski 0:01f31e923fe2 46 RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
Pawel Zarembski 0:01f31e923fe2 47 WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 48 WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 49 RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 50 RoReg Reserved1[4];
Pawel Zarembski 0:01f31e923fe2 51 RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
Pawel Zarembski 0:01f31e923fe2 52 RoReg Reserved2[41];
Pawel Zarembski 0:01f31e923fe2 53 RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
Pawel Zarembski 0:01f31e923fe2 54 RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
Pawel Zarembski 0:01f31e923fe2 55 } Spi;
Pawel Zarembski 0:01f31e923fe2 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 57 /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 58 #define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
Pawel Zarembski 0:01f31e923fe2 59 #define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
Pawel Zarembski 0:01f31e923fe2 60 #define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
Pawel Zarembski 0:01f31e923fe2 61 #define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
Pawel Zarembski 0:01f31e923fe2 62 /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 63 #define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
Pawel Zarembski 0:01f31e923fe2 64 #define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
Pawel Zarembski 0:01f31e923fe2 65 #define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
Pawel Zarembski 0:01f31e923fe2 66 #define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
Pawel Zarembski 0:01f31e923fe2 67 #define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
Pawel Zarembski 0:01f31e923fe2 68 #define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
Pawel Zarembski 0:01f31e923fe2 69 #define SPI_MR_PCS_Pos 16
Pawel Zarembski 0:01f31e923fe2 70 #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
Pawel Zarembski 0:01f31e923fe2 71 #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
Pawel Zarembski 0:01f31e923fe2 72 #define SPI_MR_DLYBCS_Pos 24
Pawel Zarembski 0:01f31e923fe2 73 #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
Pawel Zarembski 0:01f31e923fe2 74 #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
Pawel Zarembski 0:01f31e923fe2 75 /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
Pawel Zarembski 0:01f31e923fe2 76 #define SPI_RDR_RD_Pos 0
Pawel Zarembski 0:01f31e923fe2 77 #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
Pawel Zarembski 0:01f31e923fe2 78 #define SPI_RDR_PCS_Pos 16
Pawel Zarembski 0:01f31e923fe2 79 #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
Pawel Zarembski 0:01f31e923fe2 80 /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
Pawel Zarembski 0:01f31e923fe2 81 #define SPI_TDR_TD_Pos 0
Pawel Zarembski 0:01f31e923fe2 82 #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
Pawel Zarembski 0:01f31e923fe2 83 #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
Pawel Zarembski 0:01f31e923fe2 84 #define SPI_TDR_PCS_Pos 16
Pawel Zarembski 0:01f31e923fe2 85 #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
Pawel Zarembski 0:01f31e923fe2 86 #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
Pawel Zarembski 0:01f31e923fe2 87 #define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
Pawel Zarembski 0:01f31e923fe2 88 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 89 #define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
Pawel Zarembski 0:01f31e923fe2 90 #define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
Pawel Zarembski 0:01f31e923fe2 91 #define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
Pawel Zarembski 0:01f31e923fe2 92 #define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
Pawel Zarembski 0:01f31e923fe2 93 #define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
Pawel Zarembski 0:01f31e923fe2 94 #define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
Pawel Zarembski 0:01f31e923fe2 95 #define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
Pawel Zarembski 0:01f31e923fe2 96 #define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
Pawel Zarembski 0:01f31e923fe2 97 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 98 #define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 99 #define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 100 #define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 101 #define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 102 #define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 103 #define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
Pawel Zarembski 0:01f31e923fe2 104 #define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 105 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 106 #define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 107 #define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 108 #define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 109 #define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 110 #define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 111 #define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
Pawel Zarembski 0:01f31e923fe2 112 #define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 113 /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
Pawel Zarembski 0:01f31e923fe2 114 #define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 115 #define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 116 #define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 117 #define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 118 #define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 119 #define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
Pawel Zarembski 0:01f31e923fe2 120 #define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 121 /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
Pawel Zarembski 0:01f31e923fe2 122 #define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
Pawel Zarembski 0:01f31e923fe2 123 #define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
Pawel Zarembski 0:01f31e923fe2 124 #define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
Pawel Zarembski 0:01f31e923fe2 125 #define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */
Pawel Zarembski 0:01f31e923fe2 126 #define SPI_CSR_BITS_Pos 4
Pawel Zarembski 0:01f31e923fe2 127 #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
Pawel Zarembski 0:01f31e923fe2 128 #define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 129 #define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 130 #define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 131 #define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 132 #define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 133 #define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 134 #define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 135 #define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 136 #define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
Pawel Zarembski 0:01f31e923fe2 137 #define SPI_CSR_SCBR_Pos 8
Pawel Zarembski 0:01f31e923fe2 138 #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
Pawel Zarembski 0:01f31e923fe2 139 #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
Pawel Zarembski 0:01f31e923fe2 140 #define SPI_CSR_DLYBS_Pos 16
Pawel Zarembski 0:01f31e923fe2 141 #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
Pawel Zarembski 0:01f31e923fe2 142 #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
Pawel Zarembski 0:01f31e923fe2 143 #define SPI_CSR_DLYBCT_Pos 24
Pawel Zarembski 0:01f31e923fe2 144 #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
Pawel Zarembski 0:01f31e923fe2 145 #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
Pawel Zarembski 0:01f31e923fe2 146 /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 147 #define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
Pawel Zarembski 0:01f31e923fe2 148 #define SPI_WPMR_WPKEY_Pos 8
Pawel Zarembski 0:01f31e923fe2 149 #define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
Pawel Zarembski 0:01f31e923fe2 150 #define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 151 /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 152 #define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
Pawel Zarembski 0:01f31e923fe2 153 #define SPI_WPSR_WPVSRC_Pos 8
Pawel Zarembski 0:01f31e923fe2 154 #define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 /*@}*/
Pawel Zarembski 0:01f31e923fe2 157
Pawel Zarembski 0:01f31e923fe2 158
Pawel Zarembski 0:01f31e923fe2 159 #endif /* _SAM3U_SPI_COMPONENT_ */