Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/smc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_SMC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_SMC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Static Memory Controller */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_SMC Static Memory Controller */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief SmcCs_number hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
Pawel Zarembski 0:01f31e923fe2 44 RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
Pawel Zarembski 0:01f31e923fe2 45 RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
Pawel Zarembski 0:01f31e923fe2 46 RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
Pawel Zarembski 0:01f31e923fe2 47 } SmcCs_number;
Pawel Zarembski 0:01f31e923fe2 48 /** \brief Smc hardware registers */
Pawel Zarembski 0:01f31e923fe2 49 #define SMCCS_NUMBER_NUMBER 4
Pawel Zarembski 0:01f31e923fe2 50 typedef struct {
Pawel Zarembski 0:01f31e923fe2 51 RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
Pawel Zarembski 0:01f31e923fe2 52 WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
Pawel Zarembski 0:01f31e923fe2 53 RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
Pawel Zarembski 0:01f31e923fe2 54 WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 55 WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 56 RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 57 RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
Pawel Zarembski 0:01f31e923fe2 58 RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
Pawel Zarembski 0:01f31e923fe2 59 WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
Pawel Zarembski 0:01f31e923fe2 60 RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
Pawel Zarembski 0:01f31e923fe2 61 RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
Pawel Zarembski 0:01f31e923fe2 62 RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
Pawel Zarembski 0:01f31e923fe2 63 RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
Pawel Zarembski 0:01f31e923fe2 64 RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
Pawel Zarembski 0:01f31e923fe2 65 RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
Pawel Zarembski 0:01f31e923fe2 66 RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
Pawel Zarembski 0:01f31e923fe2 67 RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
Pawel Zarembski 0:01f31e923fe2 68 RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
Pawel Zarembski 0:01f31e923fe2 69 RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
Pawel Zarembski 0:01f31e923fe2 70 RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
Pawel Zarembski 0:01f31e923fe2 71 RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
Pawel Zarembski 0:01f31e923fe2 72 RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
Pawel Zarembski 0:01f31e923fe2 73 RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
Pawel Zarembski 0:01f31e923fe2 74 RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
Pawel Zarembski 0:01f31e923fe2 75 RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
Pawel Zarembski 0:01f31e923fe2 76 RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
Pawel Zarembski 0:01f31e923fe2 77 RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
Pawel Zarembski 0:01f31e923fe2 78 RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
Pawel Zarembski 0:01f31e923fe2 79 SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */
Pawel Zarembski 0:01f31e923fe2 80 RoReg Reserved1[20];
Pawel Zarembski 0:01f31e923fe2 81 RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
Pawel Zarembski 0:01f31e923fe2 82 WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
Pawel Zarembski 0:01f31e923fe2 83 WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
Pawel Zarembski 0:01f31e923fe2 84 RoReg Reserved2[50];
Pawel Zarembski 0:01f31e923fe2 85 WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
Pawel Zarembski 0:01f31e923fe2 86 RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
Pawel Zarembski 0:01f31e923fe2 87 } Smc;
Pawel Zarembski 0:01f31e923fe2 88 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 89 /* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
Pawel Zarembski 0:01f31e923fe2 90 #define SMC_CFG_PAGESIZE_Pos 0
Pawel Zarembski 0:01f31e923fe2 91 #define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */
Pawel Zarembski 0:01f31e923fe2 92 #define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
Pawel Zarembski 0:01f31e923fe2 93 #define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
Pawel Zarembski 0:01f31e923fe2 94 #define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
Pawel Zarembski 0:01f31e923fe2 95 #define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
Pawel Zarembski 0:01f31e923fe2 96 #define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
Pawel Zarembski 0:01f31e923fe2 97 #define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
Pawel Zarembski 0:01f31e923fe2 98 #define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
Pawel Zarembski 0:01f31e923fe2 99 #define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
Pawel Zarembski 0:01f31e923fe2 100 #define SMC_CFG_DTOCYC_Pos 16
Pawel Zarembski 0:01f31e923fe2 101 #define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
Pawel Zarembski 0:01f31e923fe2 102 #define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
Pawel Zarembski 0:01f31e923fe2 103 #define SMC_CFG_DTOMUL_Pos 20
Pawel Zarembski 0:01f31e923fe2 104 #define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
Pawel Zarembski 0:01f31e923fe2 105 #define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
Pawel Zarembski 0:01f31e923fe2 106 #define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
Pawel Zarembski 0:01f31e923fe2 107 #define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
Pawel Zarembski 0:01f31e923fe2 108 #define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
Pawel Zarembski 0:01f31e923fe2 109 #define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
Pawel Zarembski 0:01f31e923fe2 110 #define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
Pawel Zarembski 0:01f31e923fe2 111 #define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
Pawel Zarembski 0:01f31e923fe2 112 #define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
Pawel Zarembski 0:01f31e923fe2 113 /* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 114 #define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
Pawel Zarembski 0:01f31e923fe2 115 #define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
Pawel Zarembski 0:01f31e923fe2 116 /* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 117 #define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
Pawel Zarembski 0:01f31e923fe2 118 #define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
Pawel Zarembski 0:01f31e923fe2 119 #define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
Pawel Zarembski 0:01f31e923fe2 120 #define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
Pawel Zarembski 0:01f31e923fe2 121 #define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
Pawel Zarembski 0:01f31e923fe2 122 #define SMC_SR_NFCSID_Pos 12
Pawel Zarembski 0:01f31e923fe2 123 #define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
Pawel Zarembski 0:01f31e923fe2 124 #define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
Pawel Zarembski 0:01f31e923fe2 125 #define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
Pawel Zarembski 0:01f31e923fe2 126 #define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
Pawel Zarembski 0:01f31e923fe2 127 #define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
Pawel Zarembski 0:01f31e923fe2 128 #define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
Pawel Zarembski 0:01f31e923fe2 129 #define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
Pawel Zarembski 0:01f31e923fe2 130 #define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
Pawel Zarembski 0:01f31e923fe2 131 /* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
Pawel Zarembski 0:01f31e923fe2 132 #define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 133 #define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 134 #define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 135 #define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 136 #define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 137 #define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 138 #define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 139 #define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 140 #define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
Pawel Zarembski 0:01f31e923fe2 141 /* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
Pawel Zarembski 0:01f31e923fe2 142 #define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 143 #define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 144 #define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 145 #define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 146 #define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 147 #define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 148 #define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 149 #define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 150 #define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
Pawel Zarembski 0:01f31e923fe2 151 /* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
Pawel Zarembski 0:01f31e923fe2 152 #define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 153 #define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 154 #define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 155 #define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 156 #define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 157 #define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
Pawel Zarembski 0:01f31e923fe2 158 #define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 159 #define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 160 #define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 161 /* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
Pawel Zarembski 0:01f31e923fe2 162 #define SMC_ADDR_ADDR_CYCLE0_Pos 0
Pawel Zarembski 0:01f31e923fe2 163 #define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
Pawel Zarembski 0:01f31e923fe2 164 #define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
Pawel Zarembski 0:01f31e923fe2 165 /* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
Pawel Zarembski 0:01f31e923fe2 166 #define SMC_BANK_BANK_Pos 0
Pawel Zarembski 0:01f31e923fe2 167 #define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
Pawel Zarembski 0:01f31e923fe2 168 #define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
Pawel Zarembski 0:01f31e923fe2 169 /* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 170 #define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
Pawel Zarembski 0:01f31e923fe2 171 #define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
Pawel Zarembski 0:01f31e923fe2 172 /* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 173 #define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
Pawel Zarembski 0:01f31e923fe2 174 #define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
Pawel Zarembski 0:01f31e923fe2 175 #define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
Pawel Zarembski 0:01f31e923fe2 176 #define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
Pawel Zarembski 0:01f31e923fe2 177 #define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
Pawel Zarembski 0:01f31e923fe2 178 #define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
Pawel Zarembski 0:01f31e923fe2 179 #define SMC_ECC_MD_TYPCORREC_Pos 4
Pawel Zarembski 0:01f31e923fe2 180 #define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
Pawel Zarembski 0:01f31e923fe2 181 #define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */
Pawel Zarembski 0:01f31e923fe2 182 #define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
Pawel Zarembski 0:01f31e923fe2 183 #define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
Pawel Zarembski 0:01f31e923fe2 184 /* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
Pawel Zarembski 0:01f31e923fe2 185 #define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
Pawel Zarembski 0:01f31e923fe2 186 #define SMC_ECC_SR1_ECCERR0_Pos 1
Pawel Zarembski 0:01f31e923fe2 187 #define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
Pawel Zarembski 0:01f31e923fe2 188 #define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
Pawel Zarembski 0:01f31e923fe2 189 #define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
Pawel Zarembski 0:01f31e923fe2 190 #define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
Pawel Zarembski 0:01f31e923fe2 191 #define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
Pawel Zarembski 0:01f31e923fe2 192 #define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
Pawel Zarembski 0:01f31e923fe2 193 #define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
Pawel Zarembski 0:01f31e923fe2 194 #define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
Pawel Zarembski 0:01f31e923fe2 195 #define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
Pawel Zarembski 0:01f31e923fe2 196 #define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
Pawel Zarembski 0:01f31e923fe2 197 #define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
Pawel Zarembski 0:01f31e923fe2 198 #define SMC_ECC_SR1_ECCERR4_Pos 17
Pawel Zarembski 0:01f31e923fe2 199 #define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
Pawel Zarembski 0:01f31e923fe2 200 #define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
Pawel Zarembski 0:01f31e923fe2 201 #define SMC_ECC_SR1_ECCERR5_Pos 21
Pawel Zarembski 0:01f31e923fe2 202 #define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
Pawel Zarembski 0:01f31e923fe2 203 #define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
Pawel Zarembski 0:01f31e923fe2 204 #define SMC_ECC_SR1_ECCERR6_Pos 25
Pawel Zarembski 0:01f31e923fe2 205 #define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
Pawel Zarembski 0:01f31e923fe2 206 #define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
Pawel Zarembski 0:01f31e923fe2 207 #define SMC_ECC_SR1_ECCERR7_Pos 29
Pawel Zarembski 0:01f31e923fe2 208 #define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
Pawel Zarembski 0:01f31e923fe2 209 /* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
Pawel Zarembski 0:01f31e923fe2 210 #define SMC_ECC_PR0_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 211 #define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
Pawel Zarembski 0:01f31e923fe2 212 #define SMC_ECC_PR0_WORDADDR_Pos 4
Pawel Zarembski 0:01f31e923fe2 213 #define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
Pawel Zarembski 0:01f31e923fe2 214 #define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
Pawel Zarembski 0:01f31e923fe2 215 #define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 216 #define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 217 #define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 218 #define SMC_ECC_PR0_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 219 #define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
Pawel Zarembski 0:01f31e923fe2 220 #define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
Pawel Zarembski 0:01f31e923fe2 221 #define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 222 #define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 223 #define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 224 #define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 225 #define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
Pawel Zarembski 0:01f31e923fe2 226 /* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
Pawel Zarembski 0:01f31e923fe2 227 #define SMC_ECC_PR1_NPARITY_Pos 0
Pawel Zarembski 0:01f31e923fe2 228 #define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
Pawel Zarembski 0:01f31e923fe2 229 #define SMC_ECC_PR1_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 230 #define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 231 #define SMC_ECC_PR1_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 232 #define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 233 #define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 234 #define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
Pawel Zarembski 0:01f31e923fe2 235 #define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 236 #define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 237 #define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 238 #define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
Pawel Zarembski 0:01f31e923fe2 239 /* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
Pawel Zarembski 0:01f31e923fe2 240 #define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
Pawel Zarembski 0:01f31e923fe2 241 #define SMC_ECC_SR2_ECCERR8_Pos 1
Pawel Zarembski 0:01f31e923fe2 242 #define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
Pawel Zarembski 0:01f31e923fe2 243 #define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
Pawel Zarembski 0:01f31e923fe2 244 #define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
Pawel Zarembski 0:01f31e923fe2 245 #define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
Pawel Zarembski 0:01f31e923fe2 246 #define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
Pawel Zarembski 0:01f31e923fe2 247 #define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
Pawel Zarembski 0:01f31e923fe2 248 #define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
Pawel Zarembski 0:01f31e923fe2 249 #define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
Pawel Zarembski 0:01f31e923fe2 250 #define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
Pawel Zarembski 0:01f31e923fe2 251 #define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
Pawel Zarembski 0:01f31e923fe2 252 #define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
Pawel Zarembski 0:01f31e923fe2 253 #define SMC_ECC_SR2_ECCERR12_Pos 17
Pawel Zarembski 0:01f31e923fe2 254 #define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
Pawel Zarembski 0:01f31e923fe2 255 #define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
Pawel Zarembski 0:01f31e923fe2 256 #define SMC_ECC_SR2_ECCERR13_Pos 21
Pawel Zarembski 0:01f31e923fe2 257 #define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
Pawel Zarembski 0:01f31e923fe2 258 #define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
Pawel Zarembski 0:01f31e923fe2 259 #define SMC_ECC_SR2_ECCERR14_Pos 25
Pawel Zarembski 0:01f31e923fe2 260 #define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
Pawel Zarembski 0:01f31e923fe2 261 #define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
Pawel Zarembski 0:01f31e923fe2 262 #define SMC_ECC_SR2_ECCERR15_Pos 29
Pawel Zarembski 0:01f31e923fe2 263 #define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
Pawel Zarembski 0:01f31e923fe2 264 /* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
Pawel Zarembski 0:01f31e923fe2 265 #define SMC_ECC_PR2_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 266 #define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 267 #define SMC_ECC_PR2_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 268 #define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 269 #define SMC_ECC_PR2_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 270 #define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
Pawel Zarembski 0:01f31e923fe2 271 #define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 272 #define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 273 #define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 274 #define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
Pawel Zarembski 0:01f31e923fe2 275 /* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
Pawel Zarembski 0:01f31e923fe2 276 #define SMC_ECC_PR3_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 277 #define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 278 #define SMC_ECC_PR3_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 279 #define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 280 #define SMC_ECC_PR3_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 281 #define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
Pawel Zarembski 0:01f31e923fe2 282 #define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 283 #define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 284 #define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 285 #define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
Pawel Zarembski 0:01f31e923fe2 286 /* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
Pawel Zarembski 0:01f31e923fe2 287 #define SMC_ECC_PR4_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 288 #define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 289 #define SMC_ECC_PR4_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 290 #define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 291 #define SMC_ECC_PR4_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 292 #define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
Pawel Zarembski 0:01f31e923fe2 293 #define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 294 #define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 295 #define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 296 #define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
Pawel Zarembski 0:01f31e923fe2 297 /* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
Pawel Zarembski 0:01f31e923fe2 298 #define SMC_ECC_PR5_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 299 #define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 300 #define SMC_ECC_PR5_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 301 #define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 302 #define SMC_ECC_PR5_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 303 #define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
Pawel Zarembski 0:01f31e923fe2 304 #define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 305 #define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 306 #define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 307 #define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
Pawel Zarembski 0:01f31e923fe2 308 /* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
Pawel Zarembski 0:01f31e923fe2 309 #define SMC_ECC_PR6_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 310 #define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 311 #define SMC_ECC_PR6_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 312 #define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 313 #define SMC_ECC_PR6_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 314 #define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
Pawel Zarembski 0:01f31e923fe2 315 #define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 316 #define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 317 #define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 318 #define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
Pawel Zarembski 0:01f31e923fe2 319 /* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
Pawel Zarembski 0:01f31e923fe2 320 #define SMC_ECC_PR7_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 321 #define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 322 #define SMC_ECC_PR7_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 323 #define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 324 #define SMC_ECC_PR7_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 325 #define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
Pawel Zarembski 0:01f31e923fe2 326 #define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
Pawel Zarembski 0:01f31e923fe2 327 #define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 328 #define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
Pawel Zarembski 0:01f31e923fe2 329 #define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
Pawel Zarembski 0:01f31e923fe2 330 /* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
Pawel Zarembski 0:01f31e923fe2 331 #define SMC_ECC_PR8_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 332 #define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 333 #define SMC_ECC_PR8_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 334 #define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 335 #define SMC_ECC_PR8_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 336 #define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
Pawel Zarembski 0:01f31e923fe2 337 /* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
Pawel Zarembski 0:01f31e923fe2 338 #define SMC_ECC_PR9_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 339 #define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 340 #define SMC_ECC_PR9_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 341 #define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 342 #define SMC_ECC_PR9_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 343 #define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
Pawel Zarembski 0:01f31e923fe2 344 /* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
Pawel Zarembski 0:01f31e923fe2 345 #define SMC_ECC_PR10_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 346 #define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 347 #define SMC_ECC_PR10_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 348 #define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 349 #define SMC_ECC_PR10_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 350 #define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
Pawel Zarembski 0:01f31e923fe2 351 /* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
Pawel Zarembski 0:01f31e923fe2 352 #define SMC_ECC_PR11_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 353 #define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 354 #define SMC_ECC_PR11_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 355 #define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 356 #define SMC_ECC_PR11_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 357 #define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
Pawel Zarembski 0:01f31e923fe2 358 /* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
Pawel Zarembski 0:01f31e923fe2 359 #define SMC_ECC_PR12_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 360 #define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 361 #define SMC_ECC_PR12_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 362 #define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 363 #define SMC_ECC_PR12_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 364 #define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
Pawel Zarembski 0:01f31e923fe2 365 /* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
Pawel Zarembski 0:01f31e923fe2 366 #define SMC_ECC_PR13_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 367 #define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 368 #define SMC_ECC_PR13_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 369 #define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 370 #define SMC_ECC_PR13_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 371 #define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
Pawel Zarembski 0:01f31e923fe2 372 /* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
Pawel Zarembski 0:01f31e923fe2 373 #define SMC_ECC_PR14_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 374 #define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 375 #define SMC_ECC_PR14_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 376 #define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 377 #define SMC_ECC_PR14_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 378 #define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
Pawel Zarembski 0:01f31e923fe2 379 /* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
Pawel Zarembski 0:01f31e923fe2 380 #define SMC_ECC_PR15_BITADDR_Pos 0
Pawel Zarembski 0:01f31e923fe2 381 #define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 382 #define SMC_ECC_PR15_WORDADDR_Pos 3
Pawel Zarembski 0:01f31e923fe2 383 #define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
Pawel Zarembski 0:01f31e923fe2 384 #define SMC_ECC_PR15_NPARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 385 #define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
Pawel Zarembski 0:01f31e923fe2 386 /* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
Pawel Zarembski 0:01f31e923fe2 387 #define SMC_SETUP_NWE_SETUP_Pos 0
Pawel Zarembski 0:01f31e923fe2 388 #define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
Pawel Zarembski 0:01f31e923fe2 389 #define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
Pawel Zarembski 0:01f31e923fe2 390 #define SMC_SETUP_NCS_WR_SETUP_Pos 8
Pawel Zarembski 0:01f31e923fe2 391 #define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
Pawel Zarembski 0:01f31e923fe2 392 #define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
Pawel Zarembski 0:01f31e923fe2 393 #define SMC_SETUP_NRD_SETUP_Pos 16
Pawel Zarembski 0:01f31e923fe2 394 #define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
Pawel Zarembski 0:01f31e923fe2 395 #define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
Pawel Zarembski 0:01f31e923fe2 396 #define SMC_SETUP_NCS_RD_SETUP_Pos 24
Pawel Zarembski 0:01f31e923fe2 397 #define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
Pawel Zarembski 0:01f31e923fe2 398 #define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
Pawel Zarembski 0:01f31e923fe2 399 /* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
Pawel Zarembski 0:01f31e923fe2 400 #define SMC_PULSE_NWE_PULSE_Pos 0
Pawel Zarembski 0:01f31e923fe2 401 #define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
Pawel Zarembski 0:01f31e923fe2 402 #define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
Pawel Zarembski 0:01f31e923fe2 403 #define SMC_PULSE_NCS_WR_PULSE_Pos 8
Pawel Zarembski 0:01f31e923fe2 404 #define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
Pawel Zarembski 0:01f31e923fe2 405 #define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
Pawel Zarembski 0:01f31e923fe2 406 #define SMC_PULSE_NRD_PULSE_Pos 16
Pawel Zarembski 0:01f31e923fe2 407 #define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
Pawel Zarembski 0:01f31e923fe2 408 #define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
Pawel Zarembski 0:01f31e923fe2 409 #define SMC_PULSE_NCS_RD_PULSE_Pos 24
Pawel Zarembski 0:01f31e923fe2 410 #define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
Pawel Zarembski 0:01f31e923fe2 411 #define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
Pawel Zarembski 0:01f31e923fe2 412 /* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
Pawel Zarembski 0:01f31e923fe2 413 #define SMC_CYCLE_NWE_CYCLE_Pos 0
Pawel Zarembski 0:01f31e923fe2 414 #define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
Pawel Zarembski 0:01f31e923fe2 415 #define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
Pawel Zarembski 0:01f31e923fe2 416 #define SMC_CYCLE_NRD_CYCLE_Pos 16
Pawel Zarembski 0:01f31e923fe2 417 #define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
Pawel Zarembski 0:01f31e923fe2 418 #define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
Pawel Zarembski 0:01f31e923fe2 419 /* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
Pawel Zarembski 0:01f31e923fe2 420 #define SMC_TIMINGS_TCLR_Pos 0
Pawel Zarembski 0:01f31e923fe2 421 #define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
Pawel Zarembski 0:01f31e923fe2 422 #define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
Pawel Zarembski 0:01f31e923fe2 423 #define SMC_TIMINGS_TADL_Pos 4
Pawel Zarembski 0:01f31e923fe2 424 #define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
Pawel Zarembski 0:01f31e923fe2 425 #define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
Pawel Zarembski 0:01f31e923fe2 426 #define SMC_TIMINGS_TAR_Pos 8
Pawel Zarembski 0:01f31e923fe2 427 #define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
Pawel Zarembski 0:01f31e923fe2 428 #define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
Pawel Zarembski 0:01f31e923fe2 429 #define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
Pawel Zarembski 0:01f31e923fe2 430 #define SMC_TIMINGS_TRR_Pos 16
Pawel Zarembski 0:01f31e923fe2 431 #define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
Pawel Zarembski 0:01f31e923fe2 432 #define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
Pawel Zarembski 0:01f31e923fe2 433 #define SMC_TIMINGS_TWB_Pos 24
Pawel Zarembski 0:01f31e923fe2 434 #define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
Pawel Zarembski 0:01f31e923fe2 435 #define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
Pawel Zarembski 0:01f31e923fe2 436 #define SMC_TIMINGS_RBNSEL_Pos 28
Pawel Zarembski 0:01f31e923fe2 437 #define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
Pawel Zarembski 0:01f31e923fe2 438 #define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
Pawel Zarembski 0:01f31e923fe2 439 #define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
Pawel Zarembski 0:01f31e923fe2 440 /* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
Pawel Zarembski 0:01f31e923fe2 441 #define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */
Pawel Zarembski 0:01f31e923fe2 442 #define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
Pawel Zarembski 0:01f31e923fe2 443 #define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
Pawel Zarembski 0:01f31e923fe2 444 #define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */
Pawel Zarembski 0:01f31e923fe2 445 #define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
Pawel Zarembski 0:01f31e923fe2 446 #define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
Pawel Zarembski 0:01f31e923fe2 447 #define SMC_MODE_EXNW_MODE_Pos 4
Pawel Zarembski 0:01f31e923fe2 448 #define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
Pawel Zarembski 0:01f31e923fe2 449 #define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
Pawel Zarembski 0:01f31e923fe2 450 #define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
Pawel Zarembski 0:01f31e923fe2 451 #define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
Pawel Zarembski 0:01f31e923fe2 452 #define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
Pawel Zarembski 0:01f31e923fe2 453 #define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
Pawel Zarembski 0:01f31e923fe2 454 #define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
Pawel Zarembski 0:01f31e923fe2 455 #define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
Pawel Zarembski 0:01f31e923fe2 456 #define SMC_MODE_TDF_CYCLES_Pos 16
Pawel Zarembski 0:01f31e923fe2 457 #define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
Pawel Zarembski 0:01f31e923fe2 458 #define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
Pawel Zarembski 0:01f31e923fe2 459 #define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
Pawel Zarembski 0:01f31e923fe2 460 /* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
Pawel Zarembski 0:01f31e923fe2 461 #define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
Pawel Zarembski 0:01f31e923fe2 462 #define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
Pawel Zarembski 0:01f31e923fe2 463 /* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
Pawel Zarembski 0:01f31e923fe2 464 #define SMC_KEY1_KEY1_Pos 0
Pawel Zarembski 0:01f31e923fe2 465 #define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
Pawel Zarembski 0:01f31e923fe2 466 #define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
Pawel Zarembski 0:01f31e923fe2 467 /* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
Pawel Zarembski 0:01f31e923fe2 468 #define SMC_KEY2_KEY2_Pos 0
Pawel Zarembski 0:01f31e923fe2 469 #define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
Pawel Zarembski 0:01f31e923fe2 470 #define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
Pawel Zarembski 0:01f31e923fe2 471 /* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 472 #define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
Pawel Zarembski 0:01f31e923fe2 473 #define SMC_WPCR_WP_KEY_Pos 8
Pawel Zarembski 0:01f31e923fe2 474 #define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
Pawel Zarembski 0:01f31e923fe2 475 #define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
Pawel Zarembski 0:01f31e923fe2 476 /* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 477 #define SMC_WPSR_WP_VS_Pos 0
Pawel Zarembski 0:01f31e923fe2 478 #define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
Pawel Zarembski 0:01f31e923fe2 479 #define SMC_WPSR_WP_VSRC_Pos 8
Pawel Zarembski 0:01f31e923fe2 480 #define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
Pawel Zarembski 0:01f31e923fe2 481
Pawel Zarembski 0:01f31e923fe2 482 /*@}*/
Pawel Zarembski 0:01f31e923fe2 483
Pawel Zarembski 0:01f31e923fe2 484
Pawel Zarembski 0:01f31e923fe2 485 #endif /* _SAM3U_SMC_COMPONENT_ */