Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/cmsis-core/mpu_armv8.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /******************************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * @file mpu_armv8.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
Pawel Zarembski 0:01f31e923fe2 4 * @version V5.1.1
Pawel Zarembski 0:01f31e923fe2 5 * @date 09. August 2019
Pawel Zarembski 0:01f31e923fe2 6 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 7 /*
Pawel Zarembski 0:01f31e923fe2 8 * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 11 *
Pawel Zarembski 0:01f31e923fe2 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Pawel Zarembski 0:01f31e923fe2 13 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 14 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 15 *
Pawel Zarembski 0:01f31e923fe2 16 * www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 17 *
Pawel Zarembski 0:01f31e923fe2 18 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 21 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 22 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 23 */
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #if defined ( __ICCARM__ )
Pawel Zarembski 0:01f31e923fe2 26 #pragma system_include /* treat file as system include file for MISRA check */
Pawel Zarembski 0:01f31e923fe2 27 #elif defined (__clang__)
Pawel Zarembski 0:01f31e923fe2 28 #pragma clang system_header /* treat file as system include file */
Pawel Zarembski 0:01f31e923fe2 29 #endif
Pawel Zarembski 0:01f31e923fe2 30
Pawel Zarembski 0:01f31e923fe2 31 #ifndef ARM_MPU_ARMV8_H
Pawel Zarembski 0:01f31e923fe2 32 #define ARM_MPU_ARMV8_H
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /** \brief Attribute for device memory (outer only) */
Pawel Zarembski 0:01f31e923fe2 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
Pawel Zarembski 0:01f31e923fe2 36
Pawel Zarembski 0:01f31e923fe2 37 /** \brief Attribute for non-cacheable, normal memory */
Pawel Zarembski 0:01f31e923fe2 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Attribute for normal memory (outer and inner)
Pawel Zarembski 0:01f31e923fe2 41 * \param NT Non-Transient: Set to 1 for non-transient data.
Pawel Zarembski 0:01f31e923fe2 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
Pawel Zarembski 0:01f31e923fe2 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
Pawel Zarembski 0:01f31e923fe2 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
Pawel Zarembski 0:01f31e923fe2 45 */
Pawel Zarembski 0:01f31e923fe2 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
Pawel Zarembski 0:01f31e923fe2 47 ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
Pawel Zarembski 0:01f31e923fe2 48
Pawel Zarembski 0:01f31e923fe2 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
Pawel Zarembski 0:01f31e923fe2 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
Pawel Zarembski 0:01f31e923fe2 51
Pawel Zarembski 0:01f31e923fe2 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
Pawel Zarembski 0:01f31e923fe2 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
Pawel Zarembski 0:01f31e923fe2 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
Pawel Zarembski 0:01f31e923fe2 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
Pawel Zarembski 0:01f31e923fe2 60
Pawel Zarembski 0:01f31e923fe2 61 /** \brief Memory Attribute
Pawel Zarembski 0:01f31e923fe2 62 * \param O Outer memory attributes
Pawel Zarembski 0:01f31e923fe2 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
Pawel Zarembski 0:01f31e923fe2 64 */
Pawel Zarembski 0:01f31e923fe2 65 #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 /** \brief Normal memory non-shareable */
Pawel Zarembski 0:01f31e923fe2 68 #define ARM_MPU_SH_NON (0U)
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 /** \brief Normal memory outer shareable */
Pawel Zarembski 0:01f31e923fe2 71 #define ARM_MPU_SH_OUTER (2U)
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 /** \brief Normal memory inner shareable */
Pawel Zarembski 0:01f31e923fe2 74 #define ARM_MPU_SH_INNER (3U)
Pawel Zarembski 0:01f31e923fe2 75
Pawel Zarembski 0:01f31e923fe2 76 /** \brief Memory access permissions
Pawel Zarembski 0:01f31e923fe2 77 * \param RO Read-Only: Set to 1 for read-only memory.
Pawel Zarembski 0:01f31e923fe2 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
Pawel Zarembski 0:01f31e923fe2 79 */
Pawel Zarembski 0:01f31e923fe2 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
Pawel Zarembski 0:01f31e923fe2 81
Pawel Zarembski 0:01f31e923fe2 82 /** \brief Region Base Address Register value
Pawel Zarembski 0:01f31e923fe2 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
Pawel Zarembski 0:01f31e923fe2 84 * \param SH Defines the Shareability domain for this memory region.
Pawel Zarembski 0:01f31e923fe2 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
Pawel Zarembski 0:01f31e923fe2 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
Pawel Zarembski 0:01f31e923fe2 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
Pawel Zarembski 0:01f31e923fe2 88 */
Pawel Zarembski 0:01f31e923fe2 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
Pawel Zarembski 0:01f31e923fe2 90 (((BASE) & MPU_RBAR_BASE_Msk) | \
Pawel Zarembski 0:01f31e923fe2 91 (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
Pawel Zarembski 0:01f31e923fe2 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
Pawel Zarembski 0:01f31e923fe2 93 (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
Pawel Zarembski 0:01f31e923fe2 94
Pawel Zarembski 0:01f31e923fe2 95 /** \brief Region Limit Address Register value
Pawel Zarembski 0:01f31e923fe2 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
Pawel Zarembski 0:01f31e923fe2 97 * \param IDX The attribute index to be associated with this memory region.
Pawel Zarembski 0:01f31e923fe2 98 */
Pawel Zarembski 0:01f31e923fe2 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
Pawel Zarembski 0:01f31e923fe2 100 (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
Pawel Zarembski 0:01f31e923fe2 101 (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
Pawel Zarembski 0:01f31e923fe2 102 (MPU_RLAR_EN_Msk))
Pawel Zarembski 0:01f31e923fe2 103
Pawel Zarembski 0:01f31e923fe2 104 #if defined(MPU_RLAR_PXN_Pos)
Pawel Zarembski 0:01f31e923fe2 105
Pawel Zarembski 0:01f31e923fe2 106 /** \brief Region Limit Address Register with PXN value
Pawel Zarembski 0:01f31e923fe2 107 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
Pawel Zarembski 0:01f31e923fe2 108 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
Pawel Zarembski 0:01f31e923fe2 109 * \param IDX The attribute index to be associated with this memory region.
Pawel Zarembski 0:01f31e923fe2 110 */
Pawel Zarembski 0:01f31e923fe2 111 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
Pawel Zarembski 0:01f31e923fe2 112 (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
Pawel Zarembski 0:01f31e923fe2 113 (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
Pawel Zarembski 0:01f31e923fe2 114 (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
Pawel Zarembski 0:01f31e923fe2 115 (MPU_RLAR_EN_Msk))
Pawel Zarembski 0:01f31e923fe2 116
Pawel Zarembski 0:01f31e923fe2 117 #endif
Pawel Zarembski 0:01f31e923fe2 118
Pawel Zarembski 0:01f31e923fe2 119 /**
Pawel Zarembski 0:01f31e923fe2 120 * Struct for a single MPU Region
Pawel Zarembski 0:01f31e923fe2 121 */
Pawel Zarembski 0:01f31e923fe2 122 typedef struct {
Pawel Zarembski 0:01f31e923fe2 123 uint32_t RBAR; /*!< Region Base Address Register value */
Pawel Zarembski 0:01f31e923fe2 124 uint32_t RLAR; /*!< Region Limit Address Register value */
Pawel Zarembski 0:01f31e923fe2 125 } ARM_MPU_Region_t;
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 /** Enable the MPU.
Pawel Zarembski 0:01f31e923fe2 128 * \param MPU_Control Default access permissions for unconfigured regions.
Pawel Zarembski 0:01f31e923fe2 129 */
Pawel Zarembski 0:01f31e923fe2 130 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Pawel Zarembski 0:01f31e923fe2 131 {
Pawel Zarembski 0:01f31e923fe2 132 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Pawel Zarembski 0:01f31e923fe2 133 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Pawel Zarembski 0:01f31e923fe2 134 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Pawel Zarembski 0:01f31e923fe2 135 #endif
Pawel Zarembski 0:01f31e923fe2 136 __DSB();
Pawel Zarembski 0:01f31e923fe2 137 __ISB();
Pawel Zarembski 0:01f31e923fe2 138 }
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140 /** Disable the MPU.
Pawel Zarembski 0:01f31e923fe2 141 */
Pawel Zarembski 0:01f31e923fe2 142 __STATIC_INLINE void ARM_MPU_Disable(void)
Pawel Zarembski 0:01f31e923fe2 143 {
Pawel Zarembski 0:01f31e923fe2 144 __DMB();
Pawel Zarembski 0:01f31e923fe2 145 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Pawel Zarembski 0:01f31e923fe2 146 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Pawel Zarembski 0:01f31e923fe2 147 #endif
Pawel Zarembski 0:01f31e923fe2 148 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Pawel Zarembski 0:01f31e923fe2 149 }
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 #ifdef MPU_NS
Pawel Zarembski 0:01f31e923fe2 152 /** Enable the Non-secure MPU.
Pawel Zarembski 0:01f31e923fe2 153 * \param MPU_Control Default access permissions for unconfigured regions.
Pawel Zarembski 0:01f31e923fe2 154 */
Pawel Zarembski 0:01f31e923fe2 155 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
Pawel Zarembski 0:01f31e923fe2 156 {
Pawel Zarembski 0:01f31e923fe2 157 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Pawel Zarembski 0:01f31e923fe2 158 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Pawel Zarembski 0:01f31e923fe2 159 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Pawel Zarembski 0:01f31e923fe2 160 #endif
Pawel Zarembski 0:01f31e923fe2 161 __DSB();
Pawel Zarembski 0:01f31e923fe2 162 __ISB();
Pawel Zarembski 0:01f31e923fe2 163 }
Pawel Zarembski 0:01f31e923fe2 164
Pawel Zarembski 0:01f31e923fe2 165 /** Disable the Non-secure MPU.
Pawel Zarembski 0:01f31e923fe2 166 */
Pawel Zarembski 0:01f31e923fe2 167 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
Pawel Zarembski 0:01f31e923fe2 168 {
Pawel Zarembski 0:01f31e923fe2 169 __DMB();
Pawel Zarembski 0:01f31e923fe2 170 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Pawel Zarembski 0:01f31e923fe2 171 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Pawel Zarembski 0:01f31e923fe2 172 #endif
Pawel Zarembski 0:01f31e923fe2 173 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Pawel Zarembski 0:01f31e923fe2 174 }
Pawel Zarembski 0:01f31e923fe2 175 #endif
Pawel Zarembski 0:01f31e923fe2 176
Pawel Zarembski 0:01f31e923fe2 177 /** Set the memory attribute encoding to the given MPU.
Pawel Zarembski 0:01f31e923fe2 178 * \param mpu Pointer to the MPU to be configured.
Pawel Zarembski 0:01f31e923fe2 179 * \param idx The attribute index to be set [0-7]
Pawel Zarembski 0:01f31e923fe2 180 * \param attr The attribute value to be set.
Pawel Zarembski 0:01f31e923fe2 181 */
Pawel Zarembski 0:01f31e923fe2 182 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
Pawel Zarembski 0:01f31e923fe2 183 {
Pawel Zarembski 0:01f31e923fe2 184 const uint8_t reg = idx / 4U;
Pawel Zarembski 0:01f31e923fe2 185 const uint32_t pos = ((idx % 4U) * 8U);
Pawel Zarembski 0:01f31e923fe2 186 const uint32_t mask = 0xFFU << pos;
Pawel Zarembski 0:01f31e923fe2 187
Pawel Zarembski 0:01f31e923fe2 188 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
Pawel Zarembski 0:01f31e923fe2 189 return; // invalid index
Pawel Zarembski 0:01f31e923fe2 190 }
Pawel Zarembski 0:01f31e923fe2 191
Pawel Zarembski 0:01f31e923fe2 192 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
Pawel Zarembski 0:01f31e923fe2 193 }
Pawel Zarembski 0:01f31e923fe2 194
Pawel Zarembski 0:01f31e923fe2 195 /** Set the memory attribute encoding.
Pawel Zarembski 0:01f31e923fe2 196 * \param idx The attribute index to be set [0-7]
Pawel Zarembski 0:01f31e923fe2 197 * \param attr The attribute value to be set.
Pawel Zarembski 0:01f31e923fe2 198 */
Pawel Zarembski 0:01f31e923fe2 199 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
Pawel Zarembski 0:01f31e923fe2 200 {
Pawel Zarembski 0:01f31e923fe2 201 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
Pawel Zarembski 0:01f31e923fe2 202 }
Pawel Zarembski 0:01f31e923fe2 203
Pawel Zarembski 0:01f31e923fe2 204 #ifdef MPU_NS
Pawel Zarembski 0:01f31e923fe2 205 /** Set the memory attribute encoding to the Non-secure MPU.
Pawel Zarembski 0:01f31e923fe2 206 * \param idx The attribute index to be set [0-7]
Pawel Zarembski 0:01f31e923fe2 207 * \param attr The attribute value to be set.
Pawel Zarembski 0:01f31e923fe2 208 */
Pawel Zarembski 0:01f31e923fe2 209 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
Pawel Zarembski 0:01f31e923fe2 210 {
Pawel Zarembski 0:01f31e923fe2 211 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
Pawel Zarembski 0:01f31e923fe2 212 }
Pawel Zarembski 0:01f31e923fe2 213 #endif
Pawel Zarembski 0:01f31e923fe2 214
Pawel Zarembski 0:01f31e923fe2 215 /** Clear and disable the given MPU region of the given MPU.
Pawel Zarembski 0:01f31e923fe2 216 * \param mpu Pointer to MPU to be used.
Pawel Zarembski 0:01f31e923fe2 217 * \param rnr Region number to be cleared.
Pawel Zarembski 0:01f31e923fe2 218 */
Pawel Zarembski 0:01f31e923fe2 219 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
Pawel Zarembski 0:01f31e923fe2 220 {
Pawel Zarembski 0:01f31e923fe2 221 mpu->RNR = rnr;
Pawel Zarembski 0:01f31e923fe2 222 mpu->RLAR = 0U;
Pawel Zarembski 0:01f31e923fe2 223 }
Pawel Zarembski 0:01f31e923fe2 224
Pawel Zarembski 0:01f31e923fe2 225 /** Clear and disable the given MPU region.
Pawel Zarembski 0:01f31e923fe2 226 * \param rnr Region number to be cleared.
Pawel Zarembski 0:01f31e923fe2 227 */
Pawel Zarembski 0:01f31e923fe2 228 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Pawel Zarembski 0:01f31e923fe2 229 {
Pawel Zarembski 0:01f31e923fe2 230 ARM_MPU_ClrRegionEx(MPU, rnr);
Pawel Zarembski 0:01f31e923fe2 231 }
Pawel Zarembski 0:01f31e923fe2 232
Pawel Zarembski 0:01f31e923fe2 233 #ifdef MPU_NS
Pawel Zarembski 0:01f31e923fe2 234 /** Clear and disable the given Non-secure MPU region.
Pawel Zarembski 0:01f31e923fe2 235 * \param rnr Region number to be cleared.
Pawel Zarembski 0:01f31e923fe2 236 */
Pawel Zarembski 0:01f31e923fe2 237 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
Pawel Zarembski 0:01f31e923fe2 238 {
Pawel Zarembski 0:01f31e923fe2 239 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
Pawel Zarembski 0:01f31e923fe2 240 }
Pawel Zarembski 0:01f31e923fe2 241 #endif
Pawel Zarembski 0:01f31e923fe2 242
Pawel Zarembski 0:01f31e923fe2 243 /** Configure the given MPU region of the given MPU.
Pawel Zarembski 0:01f31e923fe2 244 * \param mpu Pointer to MPU to be used.
Pawel Zarembski 0:01f31e923fe2 245 * \param rnr Region number to be configured.
Pawel Zarembski 0:01f31e923fe2 246 * \param rbar Value for RBAR register.
Pawel Zarembski 0:01f31e923fe2 247 * \param rlar Value for RLAR register.
Pawel Zarembski 0:01f31e923fe2 248 */
Pawel Zarembski 0:01f31e923fe2 249 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
Pawel Zarembski 0:01f31e923fe2 250 {
Pawel Zarembski 0:01f31e923fe2 251 mpu->RNR = rnr;
Pawel Zarembski 0:01f31e923fe2 252 mpu->RBAR = rbar;
Pawel Zarembski 0:01f31e923fe2 253 mpu->RLAR = rlar;
Pawel Zarembski 0:01f31e923fe2 254 }
Pawel Zarembski 0:01f31e923fe2 255
Pawel Zarembski 0:01f31e923fe2 256 /** Configure the given MPU region.
Pawel Zarembski 0:01f31e923fe2 257 * \param rnr Region number to be configured.
Pawel Zarembski 0:01f31e923fe2 258 * \param rbar Value for RBAR register.
Pawel Zarembski 0:01f31e923fe2 259 * \param rlar Value for RLAR register.
Pawel Zarembski 0:01f31e923fe2 260 */
Pawel Zarembski 0:01f31e923fe2 261 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Pawel Zarembski 0:01f31e923fe2 262 {
Pawel Zarembski 0:01f31e923fe2 263 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
Pawel Zarembski 0:01f31e923fe2 264 }
Pawel Zarembski 0:01f31e923fe2 265
Pawel Zarembski 0:01f31e923fe2 266 #ifdef MPU_NS
Pawel Zarembski 0:01f31e923fe2 267 /** Configure the given Non-secure MPU region.
Pawel Zarembski 0:01f31e923fe2 268 * \param rnr Region number to be configured.
Pawel Zarembski 0:01f31e923fe2 269 * \param rbar Value for RBAR register.
Pawel Zarembski 0:01f31e923fe2 270 * \param rlar Value for RLAR register.
Pawel Zarembski 0:01f31e923fe2 271 */
Pawel Zarembski 0:01f31e923fe2 272 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Pawel Zarembski 0:01f31e923fe2 273 {
Pawel Zarembski 0:01f31e923fe2 274 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
Pawel Zarembski 0:01f31e923fe2 275 }
Pawel Zarembski 0:01f31e923fe2 276 #endif
Pawel Zarembski 0:01f31e923fe2 277
Pawel Zarembski 0:01f31e923fe2 278 /** Memcopy with strictly ordered memory access, e.g. for register targets.
Pawel Zarembski 0:01f31e923fe2 279 * \param dst Destination data is copied to.
Pawel Zarembski 0:01f31e923fe2 280 * \param src Source data is copied from.
Pawel Zarembski 0:01f31e923fe2 281 * \param len Amount of data words to be copied.
Pawel Zarembski 0:01f31e923fe2 282 */
Pawel Zarembski 0:01f31e923fe2 283 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
Pawel Zarembski 0:01f31e923fe2 284 {
Pawel Zarembski 0:01f31e923fe2 285 uint32_t i;
Pawel Zarembski 0:01f31e923fe2 286 for (i = 0U; i < len; ++i)
Pawel Zarembski 0:01f31e923fe2 287 {
Pawel Zarembski 0:01f31e923fe2 288 dst[i] = src[i];
Pawel Zarembski 0:01f31e923fe2 289 }
Pawel Zarembski 0:01f31e923fe2 290 }
Pawel Zarembski 0:01f31e923fe2 291
Pawel Zarembski 0:01f31e923fe2 292 /** Load the given number of MPU regions from a table to the given MPU.
Pawel Zarembski 0:01f31e923fe2 293 * \param mpu Pointer to the MPU registers to be used.
Pawel Zarembski 0:01f31e923fe2 294 * \param rnr First region number to be configured.
Pawel Zarembski 0:01f31e923fe2 295 * \param table Pointer to the MPU configuration table.
Pawel Zarembski 0:01f31e923fe2 296 * \param cnt Amount of regions to be configured.
Pawel Zarembski 0:01f31e923fe2 297 */
Pawel Zarembski 0:01f31e923fe2 298 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Pawel Zarembski 0:01f31e923fe2 299 {
Pawel Zarembski 0:01f31e923fe2 300 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Pawel Zarembski 0:01f31e923fe2 301 if (cnt == 1U) {
Pawel Zarembski 0:01f31e923fe2 302 mpu->RNR = rnr;
Pawel Zarembski 0:01f31e923fe2 303 ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
Pawel Zarembski 0:01f31e923fe2 304 } else {
Pawel Zarembski 0:01f31e923fe2 305 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
Pawel Zarembski 0:01f31e923fe2 306 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
Pawel Zarembski 0:01f31e923fe2 307
Pawel Zarembski 0:01f31e923fe2 308 mpu->RNR = rnrBase;
Pawel Zarembski 0:01f31e923fe2 309 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
Pawel Zarembski 0:01f31e923fe2 310 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
Pawel Zarembski 0:01f31e923fe2 311 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
Pawel Zarembski 0:01f31e923fe2 312 table += c;
Pawel Zarembski 0:01f31e923fe2 313 cnt -= c;
Pawel Zarembski 0:01f31e923fe2 314 rnrOffset = 0U;
Pawel Zarembski 0:01f31e923fe2 315 rnrBase += MPU_TYPE_RALIASES;
Pawel Zarembski 0:01f31e923fe2 316 mpu->RNR = rnrBase;
Pawel Zarembski 0:01f31e923fe2 317 }
Pawel Zarembski 0:01f31e923fe2 318
Pawel Zarembski 0:01f31e923fe2 319 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
Pawel Zarembski 0:01f31e923fe2 320 }
Pawel Zarembski 0:01f31e923fe2 321 }
Pawel Zarembski 0:01f31e923fe2 322
Pawel Zarembski 0:01f31e923fe2 323 /** Load the given number of MPU regions from a table.
Pawel Zarembski 0:01f31e923fe2 324 * \param rnr First region number to be configured.
Pawel Zarembski 0:01f31e923fe2 325 * \param table Pointer to the MPU configuration table.
Pawel Zarembski 0:01f31e923fe2 326 * \param cnt Amount of regions to be configured.
Pawel Zarembski 0:01f31e923fe2 327 */
Pawel Zarembski 0:01f31e923fe2 328 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Pawel Zarembski 0:01f31e923fe2 329 {
Pawel Zarembski 0:01f31e923fe2 330 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
Pawel Zarembski 0:01f31e923fe2 331 }
Pawel Zarembski 0:01f31e923fe2 332
Pawel Zarembski 0:01f31e923fe2 333 #ifdef MPU_NS
Pawel Zarembski 0:01f31e923fe2 334 /** Load the given number of MPU regions from a table to the Non-secure MPU.
Pawel Zarembski 0:01f31e923fe2 335 * \param rnr First region number to be configured.
Pawel Zarembski 0:01f31e923fe2 336 * \param table Pointer to the MPU configuration table.
Pawel Zarembski 0:01f31e923fe2 337 * \param cnt Amount of regions to be configured.
Pawel Zarembski 0:01f31e923fe2 338 */
Pawel Zarembski 0:01f31e923fe2 339 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Pawel Zarembski 0:01f31e923fe2 340 {
Pawel Zarembski 0:01f31e923fe2 341 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
Pawel Zarembski 0:01f31e923fe2 342 }
Pawel Zarembski 0:01f31e923fe2 343 #endif
Pawel Zarembski 0:01f31e923fe2 344
Pawel Zarembski 0:01f31e923fe2 345 #endif
Pawel Zarembski 0:01f31e923fe2 346