Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/board/override_blueninja/IO_Config_Override.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Pawel Zarembski |
0:01f31e923fe2 | 1 | /** |
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0:01f31e923fe2 | 2 | * @file IO_Config_Override.c |
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0:01f31e923fe2 | 3 | * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit |
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0:01f31e923fe2 | 4 | * |
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0:01f31e923fe2 | 5 | * DAPLink Interface Firmware |
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0:01f31e923fe2 | 6 | * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved |
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0:01f31e923fe2 | 7 | * SPDX-License-Identifier: Apache-2.0 |
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0:01f31e923fe2 | 8 | * |
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0:01f31e923fe2 | 9 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
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0:01f31e923fe2 | 10 | * not use this file except in compliance with the License. |
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0:01f31e923fe2 | 11 | * You may obtain a copy of the License at |
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0:01f31e923fe2 | 12 | * |
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0:01f31e923fe2 | 13 | * http://www.apache.org/licenses/LICENSE-2.0 |
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0:01f31e923fe2 | 14 | * |
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0:01f31e923fe2 | 15 | * Unless required by applicable law or agreed to in writing, software |
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0:01f31e923fe2 | 16 | * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
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0:01f31e923fe2 | 17 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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0:01f31e923fe2 | 18 | * See the License for the specific language governing permissions and |
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0:01f31e923fe2 | 19 | * limitations under the License. |
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0:01f31e923fe2 | 20 | */ |
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0:01f31e923fe2 | 21 | |
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0:01f31e923fe2 | 22 | #ifndef __IO_CONFIG_H__ |
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0:01f31e923fe2 | 23 | #define __IO_CONFIG_H__ |
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0:01f31e923fe2 | 24 | |
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0:01f31e923fe2 | 25 | #include "LPC11Uxx.h" |
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0:01f31e923fe2 | 26 | #include "daplink.h" |
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0:01f31e923fe2 | 27 | |
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0:01f31e923fe2 | 28 | #define TARGET_POWER_HOLD |
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0:01f31e923fe2 | 29 | #define CONTROLLED_POWER_LED |
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0:01f31e923fe2 | 30 | #define INTEGRATED_STATUS_LED |
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0:01f31e923fe2 | 31 | |
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0:01f31e923fe2 | 32 | // nRESET is FET drive. |
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0:01f31e923fe2 | 33 | #define PIN_nRESET_FET_DRIVE |
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0:01f31e923fe2 | 34 | |
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0:01f31e923fe2 | 35 | // This GPIO configuration is only valid for the LPC11U35 HIC |
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0:01f31e923fe2 | 36 | COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); |
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0:01f31e923fe2 | 37 | |
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0:01f31e923fe2 | 38 | // Peripheral register bit masks (used for pin inits) |
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0:01f31e923fe2 | 39 | #define FUNC_0 0 |
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0:01f31e923fe2 | 40 | #define FUNC_1 1 |
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0:01f31e923fe2 | 41 | #define PULL_DOWN_ENABLED (1 << 3) |
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0:01f31e923fe2 | 42 | #define PULL_UP_ENABLED (2 << 3) |
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0:01f31e923fe2 | 43 | #define OPENDRAIN (1 << 10) |
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0:01f31e923fe2 | 44 | |
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0:01f31e923fe2 | 45 | // POW LED |
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0:01f31e923fe2 | 46 | #define PIN_POW_LED_PORT 0 |
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0:01f31e923fe2 | 47 | #define PIN_POW_LED_BIT 15 |
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0:01f31e923fe2 | 48 | #define PIN_POW_LED (1 << PIN_POW_LED_BIT) |
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0:01f31e923fe2 | 49 | #define PIN_POW_LED_IOCON LPC_IOCON->SWDIO_PIO0_15 |
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0:01f31e923fe2 | 50 | #define PIN_POW_LED_IOCON_INIT (FUNC_1 | OPENDRAIN | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 51 | |
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0:01f31e923fe2 | 52 | // DAP LED PIO0_16 |
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0:01f31e923fe2 | 53 | #define PIN_DAP_LED_PORT 0 |
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0:01f31e923fe2 | 54 | #define PIN_DAP_LED_BIT 16 |
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0:01f31e923fe2 | 55 | #define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) |
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0:01f31e923fe2 | 56 | #define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_16 |
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0:01f31e923fe2 | 57 | #define PIN_DAP_LED_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 58 | |
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0:01f31e923fe2 | 59 | // MSD LED PIO0_16 |
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0:01f31e923fe2 | 60 | #define PIN_MSD_LED_PORT 0 |
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0:01f31e923fe2 | 61 | #define PIN_MSD_LED_BIT 16 |
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0:01f31e923fe2 | 62 | #define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) |
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0:01f31e923fe2 | 63 | #define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_16 |
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0:01f31e923fe2 | 64 | #define PIN_MSD_LED_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 65 | |
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0:01f31e923fe2 | 66 | // CDC LED PIO0_16 |
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0:01f31e923fe2 | 67 | #define PIN_CDC_LED_PORT 0 |
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0:01f31e923fe2 | 68 | #define PIN_CDC_LED_BIT 16 |
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0:01f31e923fe2 | 69 | #define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) |
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0:01f31e923fe2 | 70 | #define PIN_CDC_LED_IOCON LPC_IOCON->PIO0_16 |
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0:01f31e923fe2 | 71 | #define PIN_CDC_LED_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 72 | |
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0:01f31e923fe2 | 73 | // Non-Forwarded Reset in PIN PIO1_19 |
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0:01f31e923fe2 | 74 | #define PIN_RESET_IN_PORT 1 |
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0:01f31e923fe2 | 75 | #define PIN_RESET_IN_BIT 19 |
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0:01f31e923fe2 | 76 | #define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) |
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0:01f31e923fe2 | 77 | #define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 |
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0:01f31e923fe2 | 78 | #define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 79 | |
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0:01f31e923fe2 | 80 | // Forwarded Reset in PIN PIO0_1 |
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0:01f31e923fe2 | 81 | #define PIN_RESET_IN_FWRD_PORT 0 |
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0:01f31e923fe2 | 82 | #define PIN_RESET_IN_FWRD_BIT 1 |
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0:01f31e923fe2 | 83 | #define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) |
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0:01f31e923fe2 | 84 | #define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 |
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0:01f31e923fe2 | 85 | #define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 86 | |
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0:01f31e923fe2 | 87 | // nRESET OUT Pin PIO0_2 |
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0:01f31e923fe2 | 88 | #define PIN_nRESET_PORT 0 |
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0:01f31e923fe2 | 89 | #define PIN_nRESET_BIT 2 |
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0:01f31e923fe2 | 90 | #define PIN_nRESET (1 << PIN_nRESET_BIT) |
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0:01f31e923fe2 | 91 | #define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 |
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0:01f31e923fe2 | 92 | #define PIN_nRESET_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 93 | |
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0:01f31e923fe2 | 94 | // SWCLK/TCK Pin PIO0_7 |
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0:01f31e923fe2 | 95 | #define PIN_SWCLK_PORT 0 |
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0:01f31e923fe2 | 96 | #define PIN_SWCLK_BIT 7 |
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0:01f31e923fe2 | 97 | #define PIN_SWCLK (1 << PIN_SWCLK_BIT) |
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0:01f31e923fe2 | 98 | #define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7 |
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0:01f31e923fe2 | 99 | #define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 100 | |
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0:01f31e923fe2 | 101 | // SWDIO/TMS In/Out Pin PIO0_8 |
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0:01f31e923fe2 | 102 | #define PIN_SWDIO_PORT 0 |
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0:01f31e923fe2 | 103 | #define PIN_SWDIO_BIT 8 |
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0:01f31e923fe2 | 104 | #define PIN_SWDIO (1 << PIN_SWDIO_BIT) |
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0:01f31e923fe2 | 105 | #define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 |
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0:01f31e923fe2 | 106 | #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 107 | |
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0:01f31e923fe2 | 108 | // TDI Pin PIO0_22 |
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0:01f31e923fe2 | 109 | #define PIN_TDI_PORT 0 |
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0:01f31e923fe2 | 110 | #define PIN_TDI_BIT 22 |
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0:01f31e923fe2 | 111 | #define PIN_TDI (1 << PIN_TDI_BIT) |
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0:01f31e923fe2 | 112 | #define PIN_TDI_IOCON LPC_IOCON->PIO0_22 |
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0:01f31e923fe2 | 113 | #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 114 | |
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0:01f31e923fe2 | 115 | // SWO/TDO Pin PIO0_9 |
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0:01f31e923fe2 | 116 | #define PIN_TDO_PORT 0 |
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0:01f31e923fe2 | 117 | #define PIN_TDO_BIT 9 |
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0:01f31e923fe2 | 118 | #define PIN_TDO (1 << PIN_TDO_BIT) |
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0:01f31e923fe2 | 119 | #define PIN_TDO_IOCON LPC_IOCON->PIO0_9 |
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0:01f31e923fe2 | 120 | #define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) |
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0:01f31e923fe2 | 121 | |
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0:01f31e923fe2 | 122 | // PowerSW HOLD Pin PIO0_13 |
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0:01f31e923fe2 | 123 | #define PIN_PWH_PORT 0 |
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0:01f31e923fe2 | 124 | #define PIN_PWH_BIT 13 |
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0:01f31e923fe2 | 125 | #define PIN_PWH (1 << PIN_PWH_BIT) |
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0:01f31e923fe2 | 126 | #define PIN_PWH_IOCON LPC_IOCON->TDO_PIO0_13 |
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0:01f31e923fe2 | 127 | #define PIN_PWH_IOCON_INIT (FUNC_1) |
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0:01f31e923fe2 | 128 | |
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0:01f31e923fe2 | 129 | #endif |