Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/stm32/stm32f103xb/usbreg.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /*
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 5 *
Pawel Zarembski 0:01f31e923fe2 6 * Licensed under the Apache License, Version 2.0 (the License); you may
Pawel Zarembski 0:01f31e923fe2 7 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 8 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 11 *
Pawel Zarembski 0:01f31e923fe2 12 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 15 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 16 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 17 */
Pawel Zarembski 0:01f31e923fe2 18
Pawel Zarembski 0:01f31e923fe2 19 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 20 * RL-ARM - USB
Pawel Zarembski 0:01f31e923fe2 21 *----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 22 * Name: usbreg.h
Pawel Zarembski 0:01f31e923fe2 23 * Purpose: Hardware Layer Definitions for ST STM32F10x
Pawel Zarembski 0:01f31e923fe2 24 *---------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 #ifndef __USBREG_H
Pawel Zarembski 0:01f31e923fe2 27 #define __USBREG_H
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #define REG(x) (*((volatile unsigned int *)(x)))
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 #define USB_BASE_ADDR 0x40005C00 /* USB Registers Base Address */
Pawel Zarembski 0:01f31e923fe2 33 #define USB_PMA_ADDR 0x40006000 /* USB Packet Memory Area Address */
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35
Pawel Zarembski 0:01f31e923fe2 36 /* Common Registers */
Pawel Zarembski 0:01f31e923fe2 37 #define CNTR REG(USB_BASE_ADDR + 0x40) /* Control Register */
Pawel Zarembski 0:01f31e923fe2 38 #define ISTR REG(USB_BASE_ADDR + 0x44) /* Interrupt Status Register */
Pawel Zarembski 0:01f31e923fe2 39 #define FNR REG(USB_BASE_ADDR + 0x48) /* Frame Number Register */
Pawel Zarembski 0:01f31e923fe2 40 #define DADDR REG(USB_BASE_ADDR + 0x4C) /* Device Address Register */
Pawel Zarembski 0:01f31e923fe2 41 #define BTABLE REG(USB_BASE_ADDR + 0x50) /* Buffer Table Address Register */
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 /* CNTR: Control Register Bit Definitions */
Pawel Zarembski 0:01f31e923fe2 44 #define CNTR_CTRM 0x8000 /* Correct Transfer Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 45 #define CNTR_PMAOVRM 0x4000 /* Packet Memory Aerea Over/underrun Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 46 #define CNTR_ERRM 0x2000 /* Error Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 47 #define CNTR_WKUPM 0x1000 /* Wake-up Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 48 #define CNTR_SUSPM 0x0800 /* Suspend Mode Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 49 #define CNTR_RESETM 0x0400 /* USB Reset Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 50 #define CNTR_SOFM 0x0200 /* Start of Frame Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 51 #define CNTR_ESOFM 0x0100 /* Expected Start of Frame Interrupt Mask */
Pawel Zarembski 0:01f31e923fe2 52 #define CNTR_RESUME 0x0010 /* Resume Request */
Pawel Zarembski 0:01f31e923fe2 53 #define CNTR_FSUSP 0x0008 /* Force Suspend */
Pawel Zarembski 0:01f31e923fe2 54 #define CNTR_LPMODE 0x0004 /* Low-power Mode */
Pawel Zarembski 0:01f31e923fe2 55 #define CNTR_PDWN 0x0002 /* Power Down */
Pawel Zarembski 0:01f31e923fe2 56 #define CNTR_FRES 0x0001 /* Force USB Reset */
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 /* ISTR: Interrupt Status Register Bit Definitions */
Pawel Zarembski 0:01f31e923fe2 59 #define ISTR_CTR 0x8000 /* Correct Transfer */
Pawel Zarembski 0:01f31e923fe2 60 #define ISTR_PMAOVR 0x4000 /* Packet Memory Aerea Over/underrun */
Pawel Zarembski 0:01f31e923fe2 61 #define ISTR_ERR 0x2000 /* Error */
Pawel Zarembski 0:01f31e923fe2 62 #define ISTR_WKUP 0x1000 /* Wake-up */
Pawel Zarembski 0:01f31e923fe2 63 #define ISTR_SUSP 0x0800 /* Suspend Mode */
Pawel Zarembski 0:01f31e923fe2 64 #define ISTR_RESET 0x0400 /* USB Reset */
Pawel Zarembski 0:01f31e923fe2 65 #define ISTR_SOF 0x0200 /* Start of Frame */
Pawel Zarembski 0:01f31e923fe2 66 #define ISTR_ESOF 0x0100 /* Expected Start of Frame */
Pawel Zarembski 0:01f31e923fe2 67 #define ISTR_DIR 0x0010 /* Direction of Transaction */
Pawel Zarembski 0:01f31e923fe2 68 #define ISTR_EP_ID 0x000F /* EndPoint Identifier */
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 /* FNR: Frame Number Register Bit Definitions */
Pawel Zarembski 0:01f31e923fe2 71 #define FNR_RXDP 0x8000 /* D+ Data Line Status */
Pawel Zarembski 0:01f31e923fe2 72 #define FNR_RXDM 0x4000 /* D- Data Line Status */
Pawel Zarembski 0:01f31e923fe2 73 #define FNR_LCK 0x2000 /* Locked */
Pawel Zarembski 0:01f31e923fe2 74 #define FNR_LSOF 0x1800 /* Lost SOF */
Pawel Zarembski 0:01f31e923fe2 75 #define FNR_FN 0x07FF /* Frame Number */
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 /* DADDR: Device Address Register Bit Definitions */
Pawel Zarembski 0:01f31e923fe2 78 #define DADDR_EF 0x0080 /* Enable Function */
Pawel Zarembski 0:01f31e923fe2 79 #define DADDR_ADD 0x007F /* Device Address */
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81
Pawel Zarembski 0:01f31e923fe2 82 /* EndPoint Registers */
Pawel Zarembski 0:01f31e923fe2 83 #define EPxREG(x) REG(USB_BASE_ADDR + 4*(x))
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 /* EPxREG: EndPoint Registers Bit Definitions */
Pawel Zarembski 0:01f31e923fe2 86 #define EP_CTR_RX 0x8000 /* Correct RX Transfer */
Pawel Zarembski 0:01f31e923fe2 87 #define EP_DTOG_RX 0x4000 /* RX Data Toggle */
Pawel Zarembski 0:01f31e923fe2 88 #define EP_STAT_RX 0x3000 /* RX Status */
Pawel Zarembski 0:01f31e923fe2 89 #define EP_SETUP 0x0800 /* EndPoint Setup */
Pawel Zarembski 0:01f31e923fe2 90 #define EP_TYPE 0x0600 /* EndPoint Type */
Pawel Zarembski 0:01f31e923fe2 91 #define EP_KIND 0x0100 /* EndPoint Kind */
Pawel Zarembski 0:01f31e923fe2 92 #define EP_CTR_TX 0x0080 /* Correct TX Transfer */
Pawel Zarembski 0:01f31e923fe2 93 #define EP_DTOG_TX 0x0040 /* TX Data Toggle */
Pawel Zarembski 0:01f31e923fe2 94 #define EP_STAT_TX 0x0030 /* TX Status */
Pawel Zarembski 0:01f31e923fe2 95 #define EP_EA 0x000F /* EndPoint Address */
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 /* EndPoint Register Mask (No Toggle Fields) */
Pawel Zarembski 0:01f31e923fe2 98 #define EP_MASK (EP_CTR_RX|EP_SETUP|EP_TYPE|EP_KIND|EP_CTR_TX|EP_EA)
Pawel Zarembski 0:01f31e923fe2 99 /* EndPoint Register Mask (Write zero to clear) */
Pawel Zarembski 0:01f31e923fe2 100 #define EP_MASK_RC_W0 (EP_CTR_RX|EP_CTR_TX)
Pawel Zarembski 0:01f31e923fe2 101 /* Mask off all toggle bits and set write zero to clear bits to 1. */
Pawel Zarembski 0:01f31e923fe2 102 /* This creates a value that can be written back to the EndPoint register */
Pawel Zarembski 0:01f31e923fe2 103 /* which does not change any status bits. */
Pawel Zarembski 0:01f31e923fe2 104 #define EP_VAL_UNCHANGED(val) (((val) & EP_MASK) | EP_MASK_RC_W0)
Pawel Zarembski 0:01f31e923fe2 105
Pawel Zarembski 0:01f31e923fe2 106 /* EP_TYPE: EndPoint Types */
Pawel Zarembski 0:01f31e923fe2 107 #define EP_BULK 0x0000 /* BULK EndPoint */
Pawel Zarembski 0:01f31e923fe2 108 #define EP_CONTROL 0x0200 /* CONTROL EndPoint */
Pawel Zarembski 0:01f31e923fe2 109 #define EP_ISOCHRONOUS 0x0400 /* ISOCHRONOUS EndPoint */
Pawel Zarembski 0:01f31e923fe2 110 #define EP_INTERRUPT 0x0600 /* INTERRUPT EndPoint */
Pawel Zarembski 0:01f31e923fe2 111
Pawel Zarembski 0:01f31e923fe2 112 /* EP_KIND: EndPoint Kind */
Pawel Zarembski 0:01f31e923fe2 113 #define EP_DBL_BUF EP_KIND /* Double Buffer for Bulk Endpoint */
Pawel Zarembski 0:01f31e923fe2 114 #define EP_STATUS_OUT EP_KIND /* Status Out for Control Endpoint */
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 /* EP_STAT_TX: TX Status */
Pawel Zarembski 0:01f31e923fe2 117 #define EP_TX_DIS 0x0000 /* Disabled */
Pawel Zarembski 0:01f31e923fe2 118 #define EP_TX_STALL 0x0010 /* Stalled */
Pawel Zarembski 0:01f31e923fe2 119 #define EP_TX_NAK 0x0020 /* NAKed */
Pawel Zarembski 0:01f31e923fe2 120 #define EP_TX_VALID 0x0030 /* Valid */
Pawel Zarembski 0:01f31e923fe2 121
Pawel Zarembski 0:01f31e923fe2 122 /* EP_STAT_RX: RX Status */
Pawel Zarembski 0:01f31e923fe2 123 #define EP_RX_DIS 0x0000 /* Disabled */
Pawel Zarembski 0:01f31e923fe2 124 #define EP_RX_STALL 0x1000 /* Stalled */
Pawel Zarembski 0:01f31e923fe2 125 #define EP_RX_NAK 0x2000 /* NAKed */
Pawel Zarembski 0:01f31e923fe2 126 #define EP_RX_VALID 0x3000 /* Valid */
Pawel Zarembski 0:01f31e923fe2 127
Pawel Zarembski 0:01f31e923fe2 128
Pawel Zarembski 0:01f31e923fe2 129 /* Endpoint Buffer Descriptor */
Pawel Zarembski 0:01f31e923fe2 130 typedef struct _EP_BUF_DSCR {
Pawel Zarembski 0:01f31e923fe2 131 U32 ADDR_TX;
Pawel Zarembski 0:01f31e923fe2 132 U32 COUNT_TX;
Pawel Zarembski 0:01f31e923fe2 133 U32 ADDR_RX;
Pawel Zarembski 0:01f31e923fe2 134 U32 COUNT_RX;
Pawel Zarembski 0:01f31e923fe2 135 } EP_BUF_DSCR;
Pawel Zarembski 0:01f31e923fe2 136
Pawel Zarembski 0:01f31e923fe2 137 #define EP_ADDR_MASK 0xFFFE /* Address Mask */
Pawel Zarembski 0:01f31e923fe2 138 #define EP_COUNT_MASK 0x03FF /* Count Mask */
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140
Pawel Zarembski 0:01f31e923fe2 141 #endif /* __USBREG_H */