Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/stm32/stm32f103xb/sdk.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file sdk.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include "stm32f1xx.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "DAP_config.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "util.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "cortex_m.h"
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 TIM_HandleTypeDef timer;
Pawel Zarembski 0:01f31e923fe2 30 uint32_t time_count;
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 static uint32_t tim2_clk_div(uint32_t apb1clkdiv);
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /**
Pawel Zarembski 0:01f31e923fe2 35 * @brief Switch the PLL source from HSI to HSE bypass, and select the PLL as SYSCLK
Pawel Zarembski 0:01f31e923fe2 36 * source.
Pawel Zarembski 0:01f31e923fe2 37 * The system Clock is configured as follow :
Pawel Zarembski 0:01f31e923fe2 38 * System Clock source = PLL (HSE bypass)
Pawel Zarembski 0:01f31e923fe2 39 * SYSCLK(Hz) = 72000000
Pawel Zarembski 0:01f31e923fe2 40 * HCLK(Hz) = 72000000
Pawel Zarembski 0:01f31e923fe2 41 * AHB Prescaler = 1
Pawel Zarembski 0:01f31e923fe2 42 * APB1 Prescaler = 2
Pawel Zarembski 0:01f31e923fe2 43 * APB2 Prescaler = 1
Pawel Zarembski 0:01f31e923fe2 44 * HSE Frequency(Hz) = 8000000
Pawel Zarembski 0:01f31e923fe2 45 * HSE PREDIV1 = 1
Pawel Zarembski 0:01f31e923fe2 46 * PLLMUL = 9
Pawel Zarembski 0:01f31e923fe2 47 * Flash Latency(WS) = 2
Pawel Zarembski 0:01f31e923fe2 48 * @param None
Pawel Zarembski 0:01f31e923fe2 49 * @retval None
Pawel Zarembski 0:01f31e923fe2 50 */
Pawel Zarembski 0:01f31e923fe2 51 void sdk_init()
Pawel Zarembski 0:01f31e923fe2 52 {
Pawel Zarembski 0:01f31e923fe2 53 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Pawel Zarembski 0:01f31e923fe2 54 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Pawel Zarembski 0:01f31e923fe2 55
Pawel Zarembski 0:01f31e923fe2 56 SystemCoreClockUpdate();
Pawel Zarembski 0:01f31e923fe2 57 HAL_Init();
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 /* Select HSI as system clock source to allow modification of the PLL configuration */
Pawel Zarembski 0:01f31e923fe2 60 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
Pawel Zarembski 0:01f31e923fe2 61 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
Pawel Zarembski 0:01f31e923fe2 62 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
Pawel Zarembski 0:01f31e923fe2 63 /* Initialization Error */
Pawel Zarembski 0:01f31e923fe2 64 util_assert(0);
Pawel Zarembski 0:01f31e923fe2 65 }
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 /* Enable HSE bypass Oscillator, select it as PLL source and finally activate the PLL */
Pawel Zarembski 0:01f31e923fe2 68 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
Pawel Zarembski 0:01f31e923fe2 69 RCC_OscInitStruct.HSEState = RCC_CR_HSEON;
Pawel Zarembski 0:01f31e923fe2 70 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Pawel Zarembski 0:01f31e923fe2 71 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Pawel Zarembski 0:01f31e923fe2 72 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
Pawel Zarembski 0:01f31e923fe2 73 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
Pawel Zarembski 0:01f31e923fe2 74 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Pawel Zarembski 0:01f31e923fe2 75 /* Initialization Error */
Pawel Zarembski 0:01f31e923fe2 76 util_assert(0);
Pawel Zarembski 0:01f31e923fe2 77 }
Pawel Zarembski 0:01f31e923fe2 78
Pawel Zarembski 0:01f31e923fe2 79 /* Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Pawel Zarembski 0:01f31e923fe2 80 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Pawel Zarembski 0:01f31e923fe2 81 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
Pawel Zarembski 0:01f31e923fe2 82 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
Pawel Zarembski 0:01f31e923fe2 83 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
Pawel Zarembski 0:01f31e923fe2 84 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
Pawel Zarembski 0:01f31e923fe2 85 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
Pawel Zarembski 0:01f31e923fe2 86 /* Initialization Error */
Pawel Zarembski 0:01f31e923fe2 87 util_assert(0);
Pawel Zarembski 0:01f31e923fe2 88 }
Pawel Zarembski 0:01f31e923fe2 89 }
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
Pawel Zarembski 0:01f31e923fe2 92 {
Pawel Zarembski 0:01f31e923fe2 93 HAL_StatusTypeDef ret;
Pawel Zarembski 0:01f31e923fe2 94 RCC_ClkInitTypeDef clk_init;
Pawel Zarembski 0:01f31e923fe2 95 uint32_t unused;
Pawel Zarembski 0:01f31e923fe2 96 uint32_t prescaler;
Pawel Zarembski 0:01f31e923fe2 97 uint32_t source_clock;
Pawel Zarembski 0:01f31e923fe2 98
Pawel Zarembski 0:01f31e923fe2 99 HAL_RCC_GetClockConfig(&clk_init, &unused);
Pawel Zarembski 0:01f31e923fe2 100
Pawel Zarembski 0:01f31e923fe2 101 /* Compute the prescaler value to have TIMx counter clock equal to 4000 Hz */
Pawel Zarembski 0:01f31e923fe2 102 source_clock = SystemCoreClock / tim2_clk_div(clk_init.APB1CLKDivider);
Pawel Zarembski 0:01f31e923fe2 103 prescaler = (uint32_t)(source_clock / 4000) - 1;
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 /* Set TIMx instance */
Pawel Zarembski 0:01f31e923fe2 106 timer.Instance = TIM2;
Pawel Zarembski 0:01f31e923fe2 107
Pawel Zarembski 0:01f31e923fe2 108 timer.Init.Period = 0xFFFF;
Pawel Zarembski 0:01f31e923fe2 109 timer.Init.Prescaler = prescaler;
Pawel Zarembski 0:01f31e923fe2 110 timer.Init.ClockDivision = 0;
Pawel Zarembski 0:01f31e923fe2 111 timer.Init.CounterMode = TIM_COUNTERMODE_UP;
Pawel Zarembski 0:01f31e923fe2 112 timer.Init.RepetitionCounter = 0;
Pawel Zarembski 0:01f31e923fe2 113
Pawel Zarembski 0:01f31e923fe2 114 __HAL_RCC_TIM2_CLK_ENABLE();
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 ret = HAL_TIM_Base_DeInit(&timer);
Pawel Zarembski 0:01f31e923fe2 117 if (ret != HAL_OK) {
Pawel Zarembski 0:01f31e923fe2 118 return ret;
Pawel Zarembski 0:01f31e923fe2 119 }
Pawel Zarembski 0:01f31e923fe2 120
Pawel Zarembski 0:01f31e923fe2 121 time_count = 0;
Pawel Zarembski 0:01f31e923fe2 122 ret = HAL_TIM_Base_Init(&timer);
Pawel Zarembski 0:01f31e923fe2 123 if (ret != HAL_OK) {
Pawel Zarembski 0:01f31e923fe2 124 return ret;
Pawel Zarembski 0:01f31e923fe2 125 }
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 ret = HAL_TIM_Base_Start(&timer);
Pawel Zarembski 0:01f31e923fe2 128 if (ret != HAL_OK) {
Pawel Zarembski 0:01f31e923fe2 129 return ret;
Pawel Zarembski 0:01f31e923fe2 130 }
Pawel Zarembski 0:01f31e923fe2 131
Pawel Zarembski 0:01f31e923fe2 132 return HAL_OK;
Pawel Zarembski 0:01f31e923fe2 133 }
Pawel Zarembski 0:01f31e923fe2 134
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 void HAL_IncTick(void)
Pawel Zarembski 0:01f31e923fe2 137 {
Pawel Zarembski 0:01f31e923fe2 138 // Do nothing
Pawel Zarembski 0:01f31e923fe2 139 }
Pawel Zarembski 0:01f31e923fe2 140
Pawel Zarembski 0:01f31e923fe2 141 uint32_t HAL_GetTick(void)
Pawel Zarembski 0:01f31e923fe2 142 {
Pawel Zarembski 0:01f31e923fe2 143 cortex_int_state_t state;
Pawel Zarembski 0:01f31e923fe2 144 state = cortex_int_get_and_disable();
Pawel Zarembski 0:01f31e923fe2 145 const uint32_t ticks = __HAL_TIM_GET_COUNTER(&timer) / 4;
Pawel Zarembski 0:01f31e923fe2 146 time_count += (ticks - time_count) & 0x3FFF;
Pawel Zarembski 0:01f31e923fe2 147 cortex_int_restore(state);
Pawel Zarembski 0:01f31e923fe2 148 return time_count;
Pawel Zarembski 0:01f31e923fe2 149 }
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 void HAL_SuspendTick(void)
Pawel Zarembski 0:01f31e923fe2 152 {
Pawel Zarembski 0:01f31e923fe2 153 HAL_TIM_Base_Start(&timer);
Pawel Zarembski 0:01f31e923fe2 154 }
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 void HAL_ResumeTick(void)
Pawel Zarembski 0:01f31e923fe2 157 {
Pawel Zarembski 0:01f31e923fe2 158 HAL_TIM_Base_Stop(&timer);
Pawel Zarembski 0:01f31e923fe2 159 }
Pawel Zarembski 0:01f31e923fe2 160
Pawel Zarembski 0:01f31e923fe2 161 static uint32_t tim2_clk_div(uint32_t apb1clkdiv)
Pawel Zarembski 0:01f31e923fe2 162 {
Pawel Zarembski 0:01f31e923fe2 163 switch (apb1clkdiv) {
Pawel Zarembski 0:01f31e923fe2 164 case RCC_CFGR_PPRE1_DIV2:
Pawel Zarembski 0:01f31e923fe2 165 return 1;
Pawel Zarembski 0:01f31e923fe2 166 case RCC_CFGR_PPRE1_DIV4:
Pawel Zarembski 0:01f31e923fe2 167 return 2;
Pawel Zarembski 0:01f31e923fe2 168 case RCC_CFGR_PPRE1_DIV8:
Pawel Zarembski 0:01f31e923fe2 169 return 4;
Pawel Zarembski 0:01f31e923fe2 170 case RCC_CFGR_PPRE1_DIV16:
Pawel Zarembski 0:01f31e923fe2 171 return 8;
Pawel Zarembski 0:01f31e923fe2 172 default:
Pawel Zarembski 0:01f31e923fe2 173 return 1;
Pawel Zarembski 0:01f31e923fe2 174 }
Pawel Zarembski 0:01f31e923fe2 175 }