Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nxp/lpc4322/system_LPC43xx.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**********************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * $Id$ system_lpc43xx.c 2012-05-21
Pawel Zarembski 0:01f31e923fe2 3 *//**
Pawel Zarembski 0:01f31e923fe2 4 * @file system_lpc43xx.c
Pawel Zarembski 0:01f31e923fe2 5 * @brief Cortex-M3 Device System Source File for NXP lpc43xx Series.
Pawel Zarembski 0:01f31e923fe2 6 * @version 1.0
Pawel Zarembski 0:01f31e923fe2 7 * @date 21. May. 2011
Pawel Zarembski 0:01f31e923fe2 8 * @author NXP MCU SW Application Team
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * Copyright(C) 2011, NXP Semiconductor
Pawel Zarembski 0:01f31e923fe2 11 * All rights reserved.
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 ***********************************************************************
Pawel Zarembski 0:01f31e923fe2 14 * Software that is described herein is for illustrative purposes only
Pawel Zarembski 0:01f31e923fe2 15 * which provides customers with programming information regarding the
Pawel Zarembski 0:01f31e923fe2 16 * products. This software is supplied "AS IS" without any warranties.
Pawel Zarembski 0:01f31e923fe2 17 * NXP Semiconductors assumes no responsibility or liability for the
Pawel Zarembski 0:01f31e923fe2 18 * use of the software, conveys no license or title under any patent,
Pawel Zarembski 0:01f31e923fe2 19 * copyright, or mask work right to the product. NXP Semiconductors
Pawel Zarembski 0:01f31e923fe2 20 * reserves the right to make changes in the software without
Pawel Zarembski 0:01f31e923fe2 21 * notification. NXP Semiconductors also make no representation or
Pawel Zarembski 0:01f31e923fe2 22 * warranty that such application will be suitable for the specified
Pawel Zarembski 0:01f31e923fe2 23 * use without further testing or modification.
Pawel Zarembski 0:01f31e923fe2 24 * Permission to use, copy, modify, and distribute this software and its
Pawel Zarembski 0:01f31e923fe2 25 * documentation is hereby granted, under NXP Semiconductors'
Pawel Zarembski 0:01f31e923fe2 26 * relevant copyright in the software, without fee, provided that it
Pawel Zarembski 0:01f31e923fe2 27 * is used in conjunction with NXP Semiconductors microcontrollers. This
Pawel Zarembski 0:01f31e923fe2 28 * copyright, permission, and disclaimer notice must appear in all copies of
Pawel Zarembski 0:01f31e923fe2 29 * this code.
Pawel Zarembski 0:01f31e923fe2 30 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 #include "LPC43xx.h"
Pawel Zarembski 0:01f31e923fe2 33 #include "fpu_enable.h"
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 36 Define clocks
Pawel Zarembski 0:01f31e923fe2 37 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 38 #define __IRC (12000000UL) /* IRC Oscillator frequency */
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 /*----------------------------------------------------------------------------
Pawel Zarembski 0:01f31e923fe2 41 Clock Variable definitions
Pawel Zarembski 0:01f31e923fe2 42 *----------------------------------------------------------------------------*/
Pawel Zarembski 0:01f31e923fe2 43 uint32_t SystemCoreClock = 96000000; /* System Clock Frequency (Core Clock)*/
Pawel Zarembski 0:01f31e923fe2 44
Pawel Zarembski 0:01f31e923fe2 45 extern uint32_t __Vectors;
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 /**
Pawel Zarembski 0:01f31e923fe2 48 * Initialize the system
Pawel Zarembski 0:01f31e923fe2 49 *
Pawel Zarembski 0:01f31e923fe2 50 * @param none
Pawel Zarembski 0:01f31e923fe2 51 * @return none
Pawel Zarembski 0:01f31e923fe2 52 *
Pawel Zarembski 0:01f31e923fe2 53 * @brief Setup the microcontroller system.
Pawel Zarembski 0:01f31e923fe2 54 * Initialize the System.
Pawel Zarembski 0:01f31e923fe2 55 */
Pawel Zarembski 0:01f31e923fe2 56 void SystemInit(void)
Pawel Zarembski 0:01f31e923fe2 57 {
Pawel Zarembski 0:01f31e923fe2 58 // Set up Cortex_M3 or M4 VTOR register to point to vector table
Pawel Zarembski 0:01f31e923fe2 59 SCB->VTOR = (unsigned int)&__Vectors;
Pawel Zarembski 0:01f31e923fe2 60
Pawel Zarembski 0:01f31e923fe2 61 fpuEnable();
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 // In case we are running from internal flash, we configure the flash
Pawel Zarembski 0:01f31e923fe2 64 // accelerator.
Pawel Zarembski 0:01f31e923fe2 65 #define FLASH_ACCELERATOR_SPEED 6
Pawel Zarembski 0:01f31e923fe2 66 {
Pawel Zarembski 0:01f31e923fe2 67 uint32_t *MAM, t;
Pawel Zarembski 0:01f31e923fe2 68 // Set up flash controller for both banks
Pawel Zarembski 0:01f31e923fe2 69 // Bank A
Pawel Zarembski 0:01f31e923fe2 70 MAM = (uint32_t *)(LPC_CREG_BASE + 0x120);
Pawel Zarembski 0:01f31e923fe2 71 t = *MAM;
Pawel Zarembski 0:01f31e923fe2 72 t &= ~(0xF << 12);
Pawel Zarembski 0:01f31e923fe2 73 *MAM = t | (FLASH_ACCELERATOR_SPEED << 12);
Pawel Zarembski 0:01f31e923fe2 74 // Bank B
Pawel Zarembski 0:01f31e923fe2 75 MAM = (uint32_t *)(LPC_CREG_BASE + 0x124);
Pawel Zarembski 0:01f31e923fe2 76 t = *MAM;
Pawel Zarembski 0:01f31e923fe2 77 t &= ~(0xF << 12);
Pawel Zarembski 0:01f31e923fe2 78 *MAM = t | (FLASH_ACCELERATOR_SPEED << 12);
Pawel Zarembski 0:01f31e923fe2 79 }
Pawel Zarembski 0:01f31e923fe2 80 }
Pawel Zarembski 0:01f31e923fe2 81
Pawel Zarembski 0:01f31e923fe2 82 void SystemReset(void)
Pawel Zarembski 0:01f31e923fe2 83 {
Pawel Zarembski 0:01f31e923fe2 84 /* Ensure all outstanding memory accesses included buffered write are completed before reset */
Pawel Zarembski 0:01f31e923fe2 85 __DSB();
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 LPC_WWDT->MOD |= (1 << 1);
Pawel Zarembski 0:01f31e923fe2 88 LPC_WWDT->MOD |= (1 << 0);
Pawel Zarembski 0:01f31e923fe2 89 LPC_WWDT->FEED = 0xAA;
Pawel Zarembski 0:01f31e923fe2 90 LPC_WWDT->FEED = 0x55;
Pawel Zarembski 0:01f31e923fe2 91
Pawel Zarembski 0:01f31e923fe2 92 /* Ensure completion of memory access */
Pawel Zarembski 0:01f31e923fe2 93 __DSB();
Pawel Zarembski 0:01f31e923fe2 94
Pawel Zarembski 0:01f31e923fe2 95 /* wait until reset */
Pawel Zarembski 0:01f31e923fe2 96 while(1);
Pawel Zarembski 0:01f31e923fe2 97 }