Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nxp/lpc4322/lpc43xx_cgu.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file lpc43xx_cgu.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 /* Peripheral group ----------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 23 /** @defgroup CGU CGU (Clock Generation Unit)
Pawel Zarembski 0:01f31e923fe2 24 * @ingroup LPC4300CMSIS_FwLib_Drivers
Pawel Zarembski 0:01f31e923fe2 25 * @{
Pawel Zarembski 0:01f31e923fe2 26 */
Pawel Zarembski 0:01f31e923fe2 27
Pawel Zarembski 0:01f31e923fe2 28 #ifndef lpc43xx_CGU_H_
Pawel Zarembski 0:01f31e923fe2 29 #define lpc43xx_CGU_H_
Pawel Zarembski 0:01f31e923fe2 30
Pawel Zarembski 0:01f31e923fe2 31 /* Includes ------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 32 #include "LPC43xx.h"
Pawel Zarembski 0:01f31e923fe2 33 #include "lpc_types.h"
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 36 extern "C"
Pawel Zarembski 0:01f31e923fe2 37 {
Pawel Zarembski 0:01f31e923fe2 38 #endif
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 /* Private Macros -------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 41 /** @defgroup CGU_Private_Macros CGU Private Macros
Pawel Zarembski 0:01f31e923fe2 42 * @{
Pawel Zarembski 0:01f31e923fe2 43 */
Pawel Zarembski 0:01f31e923fe2 44
Pawel Zarembski 0:01f31e923fe2 45 /** Branch clocks from CGU_BASE_SAFE */
Pawel Zarembski 0:01f31e923fe2 46 #define CGU_ENTITY_NONE CGU_ENTITY_NUM
Pawel Zarembski 0:01f31e923fe2 47
Pawel Zarembski 0:01f31e923fe2 48 /** Check bit at specific position is clear or not */
Pawel Zarembski 0:01f31e923fe2 49 #define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
Pawel Zarembski 0:01f31e923fe2 50 /** Check bit at specific position is set or not */
Pawel Zarembski 0:01f31e923fe2 51 #define ISBITSET(x,bit) (x&(1<<bit))
Pawel Zarembski 0:01f31e923fe2 52 /** Set mask */
Pawel Zarembski 0:01f31e923fe2 53 #define ISMASKSET(x,mask) (x&mask)
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 /** CGU number of clock source */
Pawel Zarembski 0:01f31e923fe2 56 #define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 59 * Macro defines for CGU control mask bit definitions
Pawel Zarembski 0:01f31e923fe2 60 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 61 /** CGU control enable mask bit */
Pawel Zarembski 0:01f31e923fe2 62 #define CGU_CTRL_EN_MASK 1
Pawel Zarembski 0:01f31e923fe2 63 /** CGU control clock-source mask bit */
Pawel Zarembski 0:01f31e923fe2 64 #define CGU_CTRL_SRC_MASK (0xF<<24)
Pawel Zarembski 0:01f31e923fe2 65 /** CGU control auto block mask bit */
Pawel Zarembski 0:01f31e923fe2 66 #define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
Pawel Zarembski 0:01f31e923fe2 67
Pawel Zarembski 0:01f31e923fe2 68 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 69 * Macro defines for CGU PLL1 mask bit definitions
Pawel Zarembski 0:01f31e923fe2 70 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 71 /** CGU PLL1 feedback select mask bit */
Pawel Zarembski 0:01f31e923fe2 72 #define CGU_PLL1_FBSEL_MASK (1<<6)
Pawel Zarembski 0:01f31e923fe2 73 /** CGU PLL1 Input clock bypass control mask bit */
Pawel Zarembski 0:01f31e923fe2 74 #define CGU_PLL1_BYPASS_MASK (1<<1)
Pawel Zarembski 0:01f31e923fe2 75 /** CGU PLL1 direct CCO output mask bit */
Pawel Zarembski 0:01f31e923fe2 76 #define CGU_PLL1_DIRECT_MASK (1<<7)
Pawel Zarembski 0:01f31e923fe2 77
Pawel Zarembski 0:01f31e923fe2 78 /**
Pawel Zarembski 0:01f31e923fe2 79 * @}
Pawel Zarembski 0:01f31e923fe2 80 */
Pawel Zarembski 0:01f31e923fe2 81
Pawel Zarembski 0:01f31e923fe2 82 /* Public Types --------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 83 /** @defgroup CGU_Public_Types CGU Public Types
Pawel Zarembski 0:01f31e923fe2 84 * @{
Pawel Zarembski 0:01f31e923fe2 85 */
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 88 * @brief CGU enumeration
Pawel Zarembski 0:01f31e923fe2 89 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 90 /*
Pawel Zarembski 0:01f31e923fe2 91 * @brief CGU clock source enumerate definition
Pawel Zarembski 0:01f31e923fe2 92 */
Pawel Zarembski 0:01f31e923fe2 93 typedef enum {
Pawel Zarembski 0:01f31e923fe2 94 /* Clock Source */
Pawel Zarembski 0:01f31e923fe2 95 CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
Pawel Zarembski 0:01f31e923fe2 96 CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
Pawel Zarembski 0:01f31e923fe2 97 CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
Pawel Zarembski 0:01f31e923fe2 98 CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
Pawel Zarembski 0:01f31e923fe2 99 CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
Pawel Zarembski 0:01f31e923fe2 100 CGU_CLKSRC_TCK, /**< TCK clock source */
Pawel Zarembski 0:01f31e923fe2 101 CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
Pawel Zarembski 0:01f31e923fe2 102 CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
Pawel Zarembski 0:01f31e923fe2 103 CGU_CLKSRC_PLL0_AUDIO,
Pawel Zarembski 0:01f31e923fe2 104 CGU_CLKSRC_PLL1, /**< PLL1 clock source */
Pawel Zarembski 0:01f31e923fe2 105 CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
Pawel Zarembski 0:01f31e923fe2 106 CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
Pawel Zarembski 0:01f31e923fe2 107 CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
Pawel Zarembski 0:01f31e923fe2 108 CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
Pawel Zarembski 0:01f31e923fe2 109 CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
Pawel Zarembski 0:01f31e923fe2 110
Pawel Zarembski 0:01f31e923fe2 111 /* Base */
Pawel Zarembski 0:01f31e923fe2 112 CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
Pawel Zarembski 0:01f31e923fe2 113 CGU_BASE_USB0, /**< USB0 base clock */
Pawel Zarembski 0:01f31e923fe2 114 CGU_BASE_PERIPH, /** Peripheral bus (SGPIO) */
Pawel Zarembski 0:01f31e923fe2 115 CGU_BASE_USB1, /**< USB1 base clock */
Pawel Zarembski 0:01f31e923fe2 116 CGU_BASE_M4, /**< ARM Cortex-M4 Core base clock */
Pawel Zarembski 0:01f31e923fe2 117 CGU_BASE_SPIFI, /**< SPIFI base clock */
Pawel Zarembski 0:01f31e923fe2 118 CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
Pawel Zarembski 0:01f31e923fe2 119 CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
Pawel Zarembski 0:01f31e923fe2 120 CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
Pawel Zarembski 0:01f31e923fe2 121 CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
Pawel Zarembski 0:01f31e923fe2 122 CGU_BASE_LCD, /**< LCD base clock */
Pawel Zarembski 0:01f31e923fe2 123 CGU_BASE_ENET_CSR,
Pawel Zarembski 0:01f31e923fe2 124 CGU_BASE_SDIO, /**< SDIO base clock */
Pawel Zarembski 0:01f31e923fe2 125 CGU_BASE_SSP0, /**< SSP0 base clock */
Pawel Zarembski 0:01f31e923fe2 126 CGU_BASE_SSP1, /**< SSP1 base clock */
Pawel Zarembski 0:01f31e923fe2 127 CGU_BASE_UART0, /**< UART0 base clock */
Pawel Zarembski 0:01f31e923fe2 128 CGU_BASE_UART1, /**< UART1 base clock */
Pawel Zarembski 0:01f31e923fe2 129 CGU_BASE_UART2, /**< UART2 base clock */
Pawel Zarembski 0:01f31e923fe2 130 CGU_BASE_UART3, /**< UART3 base clock */
Pawel Zarembski 0:01f31e923fe2 131 CGU_BASE_CLKOUT, /**< CLKOUT base clock */
Pawel Zarembski 0:01f31e923fe2 132 CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
Pawel Zarembski 0:01f31e923fe2 133 CGU_BASE_OUT0,
Pawel Zarembski 0:01f31e923fe2 134 CGU_BASE_OUT1,
Pawel Zarembski 0:01f31e923fe2 135 CGU_ENTITY_NUM /**< Number or clock source entity */
Pawel Zarembski 0:01f31e923fe2 136 } CGU_ENTITY_T;
Pawel Zarembski 0:01f31e923fe2 137
Pawel Zarembski 0:01f31e923fe2 138 /*
Pawel Zarembski 0:01f31e923fe2 139 * @brief CGU PPL0 mode enumerate definition
Pawel Zarembski 0:01f31e923fe2 140 */
Pawel Zarembski 0:01f31e923fe2 141 typedef enum {
Pawel Zarembski 0:01f31e923fe2 142 CGU_PLL0_MODE_1d = 0,
Pawel Zarembski 0:01f31e923fe2 143 CGU_PLL0_MODE_1c,
Pawel Zarembski 0:01f31e923fe2 144 CGU_PLL0_MODE_1b,
Pawel Zarembski 0:01f31e923fe2 145 CGU_PLL0_MODE_1a
Pawel Zarembski 0:01f31e923fe2 146 } CGU_PLL0_MODE;
Pawel Zarembski 0:01f31e923fe2 147
Pawel Zarembski 0:01f31e923fe2 148 /*
Pawel Zarembski 0:01f31e923fe2 149 * @brief CGU peripheral enumerate definition
Pawel Zarembski 0:01f31e923fe2 150 */
Pawel Zarembski 0:01f31e923fe2 151 typedef enum {
Pawel Zarembski 0:01f31e923fe2 152 CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
Pawel Zarembski 0:01f31e923fe2 153 CGU_PERIPHERAL_ADC1, /**< ADC1 */
Pawel Zarembski 0:01f31e923fe2 154 CGU_PERIPHERAL_AES, /**< AES */
Pawel Zarembski 0:01f31e923fe2 155 // CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
Pawel Zarembski 0:01f31e923fe2 156 CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
Pawel Zarembski 0:01f31e923fe2 157 CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
Pawel Zarembski 0:01f31e923fe2 158 CGU_PERIPHERAL_CAN, /**< CAN */
Pawel Zarembski 0:01f31e923fe2 159 CGU_PERIPHERAL_CREG, /**< CREG */
Pawel Zarembski 0:01f31e923fe2 160 CGU_PERIPHERAL_DAC, /**< DAC */
Pawel Zarembski 0:01f31e923fe2 161 CGU_PERIPHERAL_DMA, /**< DMA */
Pawel Zarembski 0:01f31e923fe2 162 CGU_PERIPHERAL_EMC, /**< EMC */
Pawel Zarembski 0:01f31e923fe2 163 CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
Pawel Zarembski 0:01f31e923fe2 164 CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
Pawel Zarembski 0:01f31e923fe2 165 CGU_PERIPHERAL_GPIO, /**< GPIO */
Pawel Zarembski 0:01f31e923fe2 166 CGU_PERIPHERAL_I2C0, /**< I2C0 */
Pawel Zarembski 0:01f31e923fe2 167 CGU_PERIPHERAL_I2C1, /**< I2C1 */
Pawel Zarembski 0:01f31e923fe2 168 CGU_PERIPHERAL_I2S, /**< I2S */
Pawel Zarembski 0:01f31e923fe2 169 CGU_PERIPHERAL_LCD, /**< LCD */
Pawel Zarembski 0:01f31e923fe2 170 CGU_PERIPHERAL_M4CORE, /**< ARM Cortex-M4 Core */
Pawel Zarembski 0:01f31e923fe2 171 CGU_PERIPHERAL_M4_BUS, /**< ARM Cortex-M4 Bus */
Pawel Zarembski 0:01f31e923fe2 172 CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
Pawel Zarembski 0:01f31e923fe2 173 CGU_PERIPHERAL_QEI, /**< QEI */
Pawel Zarembski 0:01f31e923fe2 174 CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
Pawel Zarembski 0:01f31e923fe2 175 CGU_PERIPHERAL_SCT, /**< SCT */
Pawel Zarembski 0:01f31e923fe2 176 CGU_PERIPHERAL_SCU, /**< SCU */
Pawel Zarembski 0:01f31e923fe2 177 CGU_PERIPHERAL_SDIO, /**< SDIO */
Pawel Zarembski 0:01f31e923fe2 178 CGU_PERIPHERAL_SPIFI, /**< SPIFI */
Pawel Zarembski 0:01f31e923fe2 179 CGU_PERIPHERAL_SSP0, /**< SSP0 */
Pawel Zarembski 0:01f31e923fe2 180 CGU_PERIPHERAL_SSP1, /**< SSP1 */
Pawel Zarembski 0:01f31e923fe2 181 CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
Pawel Zarembski 0:01f31e923fe2 182 CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
Pawel Zarembski 0:01f31e923fe2 183 CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
Pawel Zarembski 0:01f31e923fe2 184 CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
Pawel Zarembski 0:01f31e923fe2 185 CGU_PERIPHERAL_UART0, /**< UART0 */
Pawel Zarembski 0:01f31e923fe2 186 CGU_PERIPHERAL_UART1, /**< UART1 */
Pawel Zarembski 0:01f31e923fe2 187 CGU_PERIPHERAL_UART2, /**< UART2 */
Pawel Zarembski 0:01f31e923fe2 188 CGU_PERIPHERAL_UART3, /**< UART3 */
Pawel Zarembski 0:01f31e923fe2 189 CGU_PERIPHERAL_USB0, /**< USB0 */
Pawel Zarembski 0:01f31e923fe2 190 CGU_PERIPHERAL_USB1, /**< USB1 */
Pawel Zarembski 0:01f31e923fe2 191 CGU_PERIPHERAL_WWDT, /**< WWDT */
Pawel Zarembski 0:01f31e923fe2 192 CGU_PERIPHERAL_NUM
Pawel Zarembski 0:01f31e923fe2 193 } CGU_PERIPHERAL_T;
Pawel Zarembski 0:01f31e923fe2 194
Pawel Zarembski 0:01f31e923fe2 195 /**
Pawel Zarembski 0:01f31e923fe2 196 * @brief CGU error status enumerate definition
Pawel Zarembski 0:01f31e923fe2 197 */
Pawel Zarembski 0:01f31e923fe2 198 typedef enum {
Pawel Zarembski 0:01f31e923fe2 199 CGU_ERROR_SUCCESS = 0,
Pawel Zarembski 0:01f31e923fe2 200 CGU_ERROR_CONNECT_TOGETHER,
Pawel Zarembski 0:01f31e923fe2 201 CGU_ERROR_INVALID_ENTITY,
Pawel Zarembski 0:01f31e923fe2 202 CGU_ERROR_INVALID_CLOCK_SOURCE,
Pawel Zarembski 0:01f31e923fe2 203 CGU_ERROR_INVALID_PARAM,
Pawel Zarembski 0:01f31e923fe2 204 CGU_ERROR_FREQ_OUTOF_RANGE
Pawel Zarembski 0:01f31e923fe2 205 } CGU_ERROR;
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207 /********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 208 * @brief CGU structure definitions
Pawel Zarembski 0:01f31e923fe2 209 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 210 /*
Pawel Zarembski 0:01f31e923fe2 211 * @brief CGU peripheral clock structure
Pawel Zarembski 0:01f31e923fe2 212 */
Pawel Zarembski 0:01f31e923fe2 213 typedef struct {
Pawel Zarembski 0:01f31e923fe2 214 uint8_t RegBaseEntity; /**< Base register address */
Pawel Zarembski 0:01f31e923fe2 215 uint16_t RegBranchOffset; /**< Branch register offset */
Pawel Zarembski 0:01f31e923fe2 216 uint8_t PerBaseEntity; /**< Base peripheral address */
Pawel Zarembski 0:01f31e923fe2 217 uint16_t PerBranchOffset; /**< Base peripheral offset */
Pawel Zarembski 0:01f31e923fe2 218 uint8_t next; /**< Pointer to next structure */
Pawel Zarembski 0:01f31e923fe2 219 } CGU_PERIPHERAL_S;
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 /**
Pawel Zarembski 0:01f31e923fe2 222 * @}
Pawel Zarembski 0:01f31e923fe2 223 */
Pawel Zarembski 0:01f31e923fe2 224
Pawel Zarembski 0:01f31e923fe2 225
Pawel Zarembski 0:01f31e923fe2 226 /* Public Functions ----------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 227 /** @defgroup CGU_Public_Functions CGU Public Functions
Pawel Zarembski 0:01f31e923fe2 228 * @{
Pawel Zarembski 0:01f31e923fe2 229 */
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 /** Clock generate initialize/de-initialize */
Pawel Zarembski 0:01f31e923fe2 232 uint32_t CGU_Init(uint32_t wantedFreq);
Pawel Zarembski 0:01f31e923fe2 233 uint32_t CGU_DeInit(void);
Pawel Zarembski 0:01f31e923fe2 234
Pawel Zarembski 0:01f31e923fe2 235 /** Clock Generator and Clock Control */
Pawel Zarembski 0:01f31e923fe2 236 uint32_t CGU_ConfigPWR(CGU_PERIPHERAL_T PPType, FunctionalState en);
Pawel Zarembski 0:01f31e923fe2 237 uint32_t CGU_GetPCLKFrequency(CGU_PERIPHERAL_T Clock);
Pawel Zarembski 0:01f31e923fe2 238
Pawel Zarembski 0:01f31e923fe2 239 /** Clock Source and Base Clock operation */
Pawel Zarembski 0:01f31e923fe2 240 uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
Pawel Zarembski 0:01f31e923fe2 241 uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
Pawel Zarembski 0:01f31e923fe2 242 uint32_t CGU_SetPLL0(void);
Pawel Zarembski 0:01f31e923fe2 243 uint32_t CGU_SetPLL0audio(void);
Pawel Zarembski 0:01f31e923fe2 244 uint32_t CGU_SetPLL1(uint32_t mult);
Pawel Zarembski 0:01f31e923fe2 245 uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
Pawel Zarembski 0:01f31e923fe2 246 uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
Pawel Zarembski 0:01f31e923fe2 247 uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
Pawel Zarembski 0:01f31e923fe2 248 void CGU_UpdateClock(void);
Pawel Zarembski 0:01f31e923fe2 249 uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
Pawel Zarembski 0:01f31e923fe2 250
Pawel Zarembski 0:01f31e923fe2 251 /**
Pawel Zarembski 0:01f31e923fe2 252 * @}
Pawel Zarembski 0:01f31e923fe2 253 */
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255
Pawel Zarembski 0:01f31e923fe2 256 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 257 }
Pawel Zarembski 0:01f31e923fe2 258 #endif
Pawel Zarembski 0:01f31e923fe2 259
Pawel Zarembski 0:01f31e923fe2 260 #endif /* lpc43xx_CGU_H_ */
Pawel Zarembski 0:01f31e923fe2 261
Pawel Zarembski 0:01f31e923fe2 262 /**
Pawel Zarembski 0:01f31e923fe2 263 * @}
Pawel Zarembski 0:01f31e923fe2 264 */
Pawel Zarembski 0:01f31e923fe2 265