Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file lpc43xx_cgu.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include "lpc_types.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "lpc43xx_scu.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "lpc43xx_cgu.h"
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 /** This define used to fix mistake when run with IAR compiler */
Pawel Zarembski 0:01f31e923fe2 27 #ifdef __ICCARM__
Pawel Zarembski 0:01f31e923fe2 28 #define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001
Pawel Zarembski 0:01f31e923fe2 29 #else
Pawel Zarembski 0:01f31e923fe2 30 #define CGU_BRANCH_STATUS_ENABLE_MASK 0x01
Pawel Zarembski 0:01f31e923fe2 31 #endif
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /*TODO List:
Pawel Zarembski 0:01f31e923fe2 34 * SET PLL0
Pawel Zarembski 0:01f31e923fe2 35 * UPDATE Clock from PLL0
Pawel Zarembski 0:01f31e923fe2 36 * SetDIV uncheck value
Pawel Zarembski 0:01f31e923fe2 37 * GetBaseStatus BASE_SAFE
Pawel Zarembski 0:01f31e923fe2 38 * */
Pawel Zarembski 0:01f31e923fe2 39 /* Local definition */
Pawel Zarembski 0:01f31e923fe2 40 #define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))
Pawel Zarembski 0:01f31e923fe2 41
Pawel Zarembski 0:01f31e923fe2 42 /* Local Variable */
Pawel Zarembski 0:01f31e923fe2 43 const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {
Pawel Zarembski 0:01f31e923fe2 44 -1, //CGU_CLKSRC_32KHZ_OSC,
Pawel Zarembski 0:01f31e923fe2 45 -1, //CGU_CLKSRC_IRC,
Pawel Zarembski 0:01f31e923fe2 46 -1, //CGU_CLKSRC_ENET_RX_CLK,
Pawel Zarembski 0:01f31e923fe2 47 -1, //CGU_CLKSRC_ENET_TX_CLK,
Pawel Zarembski 0:01f31e923fe2 48 -1, //CGU_CLKSRC_GP_CLKIN,
Pawel Zarembski 0:01f31e923fe2 49 -1, //CGU_CLKSRC_TCK,
Pawel Zarembski 0:01f31e923fe2 50 0x18, //CGU_CLKSRC_XTAL_OSC,
Pawel Zarembski 0:01f31e923fe2 51 0x20, //CGU_CLKSRC_PLL0,
Pawel Zarembski 0:01f31e923fe2 52 0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**
Pawel Zarembski 0:01f31e923fe2 53 0x44, //CGU_CLKSRC_PLL1,
Pawel Zarembski 0:01f31e923fe2 54 -1, //CGU_CLKSRC_RESERVE,
Pawel Zarembski 0:01f31e923fe2 55 -1, //CGU_CLKSRC_RESERVE,
Pawel Zarembski 0:01f31e923fe2 56 0x48, //CGU_CLKSRC_IDIVA,,
Pawel Zarembski 0:01f31e923fe2 57 0x4C, //CGU_CLKSRC_IDIVB,
Pawel Zarembski 0:01f31e923fe2 58 0x50, //CGU_CLKSRC_IDIVC,
Pawel Zarembski 0:01f31e923fe2 59 0x54, //CGU_CLKSRC_IDIVD,
Pawel Zarembski 0:01f31e923fe2 60 0x58, //CGU_CLKSRC_IDIVE,
Pawel Zarembski 0:01f31e923fe2 61
Pawel Zarembski 0:01f31e923fe2 62 0x5C, //CGU_BASE_SAFE,
Pawel Zarembski 0:01f31e923fe2 63 0x60, //CGU_BASE_USB0,
Pawel Zarembski 0:01f31e923fe2 64 0x64, //CGU_BASE_PERIPH, // used for SPGPIO, peripheral control
Pawel Zarembski 0:01f31e923fe2 65 0x68, //CGU_BASE_USB1,
Pawel Zarembski 0:01f31e923fe2 66 0x6C, //CGU_BASE_M4,
Pawel Zarembski 0:01f31e923fe2 67 0x70, //CGU_BASE_SPIFI,
Pawel Zarembski 0:01f31e923fe2 68 -1, //CGU_BASE_RESERVE,
Pawel Zarembski 0:01f31e923fe2 69 0x78, //CGU_BASE_PHY_RX,
Pawel Zarembski 0:01f31e923fe2 70 0x7C, //CGU_BASE_PHY_TX,
Pawel Zarembski 0:01f31e923fe2 71 0x80, //CGU_BASE_APB1,
Pawel Zarembski 0:01f31e923fe2 72 0x84, //CGU_BASE_APB3,
Pawel Zarembski 0:01f31e923fe2 73 0x88, //CGU_BASE_LCD,
Pawel Zarembski 0:01f31e923fe2 74 0X8C, //CGU_BASE_ENET_CSR, **REV A**
Pawel Zarembski 0:01f31e923fe2 75 0x90, //CGU_BASE_SDIO,
Pawel Zarembski 0:01f31e923fe2 76 0x94, //CGU_BASE_SSP0,
Pawel Zarembski 0:01f31e923fe2 77 0x98, //CGU_BASE_SSP1,
Pawel Zarembski 0:01f31e923fe2 78 0x9C, //CGU_BASE_UART0,
Pawel Zarembski 0:01f31e923fe2 79 0xA0, //CGU_BASE_UART1,
Pawel Zarembski 0:01f31e923fe2 80 0xA4, //CGU_BASE_UART2,
Pawel Zarembski 0:01f31e923fe2 81 0xA8, //CGU_BASE_UART3,
Pawel Zarembski 0:01f31e923fe2 82 0xAC, //CGU_BASE_CLKOUT
Pawel Zarembski 0:01f31e923fe2 83 -1,
Pawel Zarembski 0:01f31e923fe2 84 -1,
Pawel Zarembski 0:01f31e923fe2 85 -1,
Pawel Zarembski 0:01f31e923fe2 86 -1,
Pawel Zarembski 0:01f31e923fe2 87 0xC0, //CGU_BASE_APLL
Pawel Zarembski 0:01f31e923fe2 88 0xC4, //CGU_BASE_OUT0
Pawel Zarembski 0:01f31e923fe2 89 0xC8 //CGU_BASE_OUT1
Pawel Zarembski 0:01f31e923fe2 90 };
Pawel Zarembski 0:01f31e923fe2 91
Pawel Zarembski 0:01f31e923fe2 92 const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {
Pawel Zarembski 0:01f31e923fe2 93 // 3 I E E G T X P P P x x D D D D D S U P U M S x P P A A L E S S S U U U U C x x x x A O O
Pawel Zarembski 0:01f31e923fe2 94 // 2 R R T P C T L L L I I I I I A S E S 3 P H H P P C N D S S R R R R O P U U
Pawel Zarembski 0:01f31e923fe2 95 // C X X I K A 0 A 1 A B C D E F B R B F RxTx1 3 D T I 0 1 0 1 2 3 L T T
Pawel Zarembski 0:01f31e923fe2 96 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_32KHZ_OSC = 0,*/
Pawel Zarembski 0:01f31e923fe2 97 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IRC,*/
Pawel Zarembski 0:01f31e923fe2 98 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_ENET_RX_CLK,*/
Pawel Zarembski 0:01f31e923fe2 99 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_ENET_TX_CLK,*/
Pawel Zarembski 0:01f31e923fe2 100 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_GP_CLKIN,*/
Pawel Zarembski 0:01f31e923fe2 101 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}, /*CGU_CLKSRC_TCK,*/
Pawel Zarembski 0:01f31e923fe2 102 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_XTAL_OSC,*/
Pawel Zarembski 0:01f31e923fe2 103 {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1}, /*CGU_CLKSRC_PLL0,*/
Pawel Zarembski 0:01f31e923fe2 104 {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_PLL0_AUDIO,*/
Pawel Zarembski 0:01f31e923fe2 105 {0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_PLL1,*/
Pawel Zarembski 0:01f31e923fe2 106 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
Pawel Zarembski 0:01f31e923fe2 107 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
Pawel Zarembski 0:01f31e923fe2 108 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/
Pawel Zarembski 0:01f31e923fe2 109 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVB,*/
Pawel Zarembski 0:01f31e923fe2 110 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVC,*/
Pawel Zarembski 0:01f31e923fe2 111 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVD,*/
Pawel Zarembski 0:01f31e923fe2 112 {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1} /*CGU_CLKSRC_IDIVE,*/
Pawel Zarembski 0:01f31e923fe2 113 };
Pawel Zarembski 0:01f31e923fe2 114
Pawel Zarembski 0:01f31e923fe2 115 const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {
Pawel Zarembski 0:01f31e923fe2 116 /* Register Clock | Peripheral Clock
Pawel Zarembski 0:01f31e923fe2 117 | BASE | BRANCH | BASE | BRANCH */
Pawel Zarembski 0:01f31e923fe2 118 {CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,
Pawel Zarembski 0:01f31e923fe2 119 {CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,
Pawel Zarembski 0:01f31e923fe2 120 {CGU_BASE_M4, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,
Pawel Zarembski 0:01f31e923fe2 121 //// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
Pawel Zarembski 0:01f31e923fe2 122 {CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,
Pawel Zarembski 0:01f31e923fe2 123 {CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,
Pawel Zarembski 0:01f31e923fe2 124 {CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,
Pawel Zarembski 0:01f31e923fe2 125 {CGU_BASE_M4, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,
Pawel Zarembski 0:01f31e923fe2 126 {CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,
Pawel Zarembski 0:01f31e923fe2 127 {CGU_BASE_M4, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,
Pawel Zarembski 0:01f31e923fe2 128 {CGU_BASE_M4, 0x1430, CGU_BASE_M4, 0x1478, 0},//CGU_PERIPHERAL_EMC,
Pawel Zarembski 0:01f31e923fe2 129 {CGU_BASE_M4, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,
Pawel Zarembski 0:01f31e923fe2 130 {CGU_ENTITY_NONE, 0x0000, CGU_BASE_PHY_TX, 0x0000, 0}, //CGU_PERIPHERAL_ETHERNET_TX
Pawel Zarembski 0:01f31e923fe2 131 {CGU_BASE_M4, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,
Pawel Zarembski 0:01f31e923fe2 132 {CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,
Pawel Zarembski 0:01f31e923fe2 133 {CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,
Pawel Zarembski 0:01f31e923fe2 134 {CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,
Pawel Zarembski 0:01f31e923fe2 135 {CGU_BASE_M4, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,
Pawel Zarembski 0:01f31e923fe2 136 {CGU_BASE_M4, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,
Pawel Zarembski 0:01f31e923fe2 137 {CGU_BASE_M4, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,
Pawel Zarembski 0:01f31e923fe2 138 {CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,
Pawel Zarembski 0:01f31e923fe2 139 {CGU_BASE_M4, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,
Pawel Zarembski 0:01f31e923fe2 140 {CGU_BASE_M4, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,
Pawel Zarembski 0:01f31e923fe2 141 {CGU_BASE_M4, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,
Pawel Zarembski 0:01f31e923fe2 142 {CGU_BASE_M4, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,
Pawel Zarembski 0:01f31e923fe2 143 {CGU_BASE_M4, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,
Pawel Zarembski 0:01f31e923fe2 144 {CGU_BASE_M4, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,
Pawel Zarembski 0:01f31e923fe2 145 {CGU_BASE_M4, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,
Pawel Zarembski 0:01f31e923fe2 146 {CGU_BASE_M4, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,
Pawel Zarembski 0:01f31e923fe2 147 {CGU_BASE_M4, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,
Pawel Zarembski 0:01f31e923fe2 148 {CGU_BASE_M4, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,
Pawel Zarembski 0:01f31e923fe2 149 {CGU_BASE_M4, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,
Pawel Zarembski 0:01f31e923fe2 150 {CGU_BASE_M4, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,
Pawel Zarembski 0:01f31e923fe2 151 {CGU_BASE_M4, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,
Pawel Zarembski 0:01f31e923fe2 152 {CGU_BASE_M4, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,
Pawel Zarembski 0:01f31e923fe2 153 {CGU_BASE_M4, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,
Pawel Zarembski 0:01f31e923fe2 154 {CGU_BASE_M4, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,
Pawel Zarembski 0:01f31e923fe2 155 {CGU_BASE_M4, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,
Pawel Zarembski 0:01f31e923fe2 156 {CGU_BASE_M4, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,
Pawel Zarembski 0:01f31e923fe2 157 {CGU_BASE_M4, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,
Pawel Zarembski 0:01f31e923fe2 158 };
Pawel Zarembski 0:01f31e923fe2 159
Pawel Zarembski 0:01f31e923fe2 160 uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0, 12000000, 0, 0, 0, 0, 0, 480000000, 0, 0, 0, 0, 0, 0, 0, 0, 0};
Pawel Zarembski 0:01f31e923fe2 161
Pawel Zarembski 0:01f31e923fe2 162 #define CGU_CGU_ADDR ((uint32_t)LPC_CGU)
Pawel Zarembski 0:01f31e923fe2 163 #define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))
Pawel Zarembski 0:01f31e923fe2 164 #define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))
Pawel Zarembski 0:01f31e923fe2 165 #define CGU_REG_BRANCH_STATUS(x) (*(volatile uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
Pawel Zarembski 0:01f31e923fe2 166
Pawel Zarembski 0:01f31e923fe2 167 #define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))
Pawel Zarembski 0:01f31e923fe2 168 #define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))
Pawel Zarembski 0:01f31e923fe2 169 #define CGU_PER_BRANCH_STATUS(x) (*(volatile uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))
Pawel Zarembski 0:01f31e923fe2 170
Pawel Zarembski 0:01f31e923fe2 171 /**************************************************************************//**
Pawel Zarembski 0:01f31e923fe2 172 *
Pawel Zarembski 0:01f31e923fe2 173 * @brief Rough approximation of a delay function with microsecond resolution.
Pawel Zarembski 0:01f31e923fe2 174 *
Pawel Zarembski 0:01f31e923fe2 175 * Used during initial clock setup as the Timers are not configured yet.
Pawel Zarembski 0:01f31e923fe2 176 *
Pawel Zarembski 0:01f31e923fe2 177 * @param [in] us The number of microseconds to wait
Pawel Zarembski 0:01f31e923fe2 178 *
Pawel Zarembski 0:01f31e923fe2 179 *****************************************************************************/
Pawel Zarembski 0:01f31e923fe2 180 static void cgu_WaitUS(volatile uint32_t us)
Pawel Zarembski 0:01f31e923fe2 181 {
Pawel Zarembski 0:01f31e923fe2 182 us *= (SystemCoreClock / 1000000) / 3;
Pawel Zarembski 0:01f31e923fe2 183
Pawel Zarembski 0:01f31e923fe2 184 while (us--);
Pawel Zarembski 0:01f31e923fe2 185 }
Pawel Zarembski 0:01f31e923fe2 186
Pawel Zarembski 0:01f31e923fe2 187 /**************************************************************************//**
Pawel Zarembski 0:01f31e923fe2 188 *
Pawel Zarembski 0:01f31e923fe2 189 * @brief Simple lookup of best MSEL and NSEL values for wanted frequency
Pawel Zarembski 0:01f31e923fe2 190 *
Pawel Zarembski 0:01f31e923fe2 191 * Not optimized.
Pawel Zarembski 0:01f31e923fe2 192 *
Pawel Zarembski 0:01f31e923fe2 193 * @param [in] wantedFreq The wanted PLL1 frequency
Pawel Zarembski 0:01f31e923fe2 194 * @param [out] pMsel The best MSEL value for the PLL1_CTRL register
Pawel Zarembski 0:01f31e923fe2 195 * @param [out] pNsel The best NSEL value for the PLL1_CTRL register
Pawel Zarembski 0:01f31e923fe2 196 *
Pawel Zarembski 0:01f31e923fe2 197 *****************************************************************************/
Pawel Zarembski 0:01f31e923fe2 198 static void cgu_findMN(uint32_t wantedFreq, uint32_t *pMsel, uint32_t *pNsel)
Pawel Zarembski 0:01f31e923fe2 199 {
Pawel Zarembski 0:01f31e923fe2 200 uint32_t besterr = wantedFreq;
Pawel Zarembski 0:01f31e923fe2 201 uint32_t m, n, f, tmp, err;
Pawel Zarembski 0:01f31e923fe2 202 #define ABSDIFF(__a, __b) ( ((__a) < (__b)) ? ((__b) - (__a)) : ((__a) - (__b)) )
Pawel Zarembski 0:01f31e923fe2 203
Pawel Zarembski 0:01f31e923fe2 204 for (n = 1; n <= 4; n++) {
Pawel Zarembski 0:01f31e923fe2 205 f = 12000000 / n;
Pawel Zarembski 0:01f31e923fe2 206 tmp = 0;
Pawel Zarembski 0:01f31e923fe2 207
Pawel Zarembski 0:01f31e923fe2 208 for (m = 1; m <= 256; m++) {
Pawel Zarembski 0:01f31e923fe2 209 tmp += f;
Pawel Zarembski 0:01f31e923fe2 210 err = ABSDIFF(tmp, wantedFreq);
Pawel Zarembski 0:01f31e923fe2 211
Pawel Zarembski 0:01f31e923fe2 212 if (err == 0) {
Pawel Zarembski 0:01f31e923fe2 213 // found perfect match
Pawel Zarembski 0:01f31e923fe2 214 *pMsel = m - 1;
Pawel Zarembski 0:01f31e923fe2 215 *pNsel = n - 1;
Pawel Zarembski 0:01f31e923fe2 216 return;
Pawel Zarembski 0:01f31e923fe2 217
Pawel Zarembski 0:01f31e923fe2 218 } else if (err < besterr) {
Pawel Zarembski 0:01f31e923fe2 219 *pMsel = m - 1;
Pawel Zarembski 0:01f31e923fe2 220 *pNsel = n - 1;
Pawel Zarembski 0:01f31e923fe2 221 besterr = err;
Pawel Zarembski 0:01f31e923fe2 222 }
Pawel Zarembski 0:01f31e923fe2 223
Pawel Zarembski 0:01f31e923fe2 224 if (tmp > wantedFreq) {
Pawel Zarembski 0:01f31e923fe2 225 // no point in continuing to increase tmp as value is too high already
Pawel Zarembski 0:01f31e923fe2 226 break;
Pawel Zarembski 0:01f31e923fe2 227 }
Pawel Zarembski 0:01f31e923fe2 228 }
Pawel Zarembski 0:01f31e923fe2 229 }
Pawel Zarembski 0:01f31e923fe2 230 }
Pawel Zarembski 0:01f31e923fe2 231
Pawel Zarembski 0:01f31e923fe2 232 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 233 * @brief Initialize default clock for LPC4300 Eval board
Pawel Zarembski 0:01f31e923fe2 234 * @param[in] None
Pawel Zarembski 0:01f31e923fe2 235 * @return Initialize status, could be:
Pawel Zarembski 0:01f31e923fe2 236 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 237 * - Other: error
Pawel Zarembski 0:01f31e923fe2 238 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 239 uint32_t CGU_Init(uint32_t wantedFreq)
Pawel Zarembski 0:01f31e923fe2 240 {
Pawel Zarembski 0:01f31e923fe2 241 uint32_t msel = 0;
Pawel Zarembski 0:01f31e923fe2 242 uint32_t nsel = 0;
Pawel Zarembski 0:01f31e923fe2 243 uint32_t tmp;
Pawel Zarembski 0:01f31e923fe2 244 // Setup PLL1 to 204MHz
Pawel Zarembski 0:01f31e923fe2 245 // 0. Select IRC as BASE_M4_CLK source
Pawel Zarembski 0:01f31e923fe2 246 CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_BASE_M4);
Pawel Zarembski 0:01f31e923fe2 247 SystemCoreClock = 96000000;
Pawel Zarembski 0:01f31e923fe2 248 // 1. Enable the crystal oscillator
Pawel Zarembski 0:01f31e923fe2 249 CGU_SetXTALOSC(12000000);
Pawel Zarembski 0:01f31e923fe2 250 CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
Pawel Zarembski 0:01f31e923fe2 251 // 2. Wait 250us
Pawel Zarembski 0:01f31e923fe2 252 cgu_WaitUS(250);
Pawel Zarembski 0:01f31e923fe2 253 // 3. Reconfigure PLL1 as follows:
Pawel Zarembski 0:01f31e923fe2 254 // - Select the M and N divider values to produce the final desired
Pawel Zarembski 0:01f31e923fe2 255 // PLL1 output frequency (204MHz => M=17,N=1 => msel=16,nsel=0)
Pawel Zarembski 0:01f31e923fe2 256 // - Select the crystal oscillator as clock source for PLL1
Pawel Zarembski 0:01f31e923fe2 257 cgu_findMN(wantedFreq, &msel, &nsel);
Pawel Zarembski 0:01f31e923fe2 258 tmp = LPC_CGU->PLL1_CTRL & ~((0xFF << 16) | (0x03 << 12));
Pawel Zarembski 0:01f31e923fe2 259 LPC_CGU->PLL1_CTRL = tmp | (msel << 16) | (nsel << 12);
Pawel Zarembski 0:01f31e923fe2 260 CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
Pawel Zarembski 0:01f31e923fe2 261
Pawel Zarembski 0:01f31e923fe2 262 // 4. Wait for the PLL1 to lock
Pawel Zarembski 0:01f31e923fe2 263 while ((LPC_CGU->PLL1_STAT & 1) == 0x0);
Pawel Zarembski 0:01f31e923fe2 264
Pawel Zarembski 0:01f31e923fe2 265 // 5. Set PLL1 P-divider to divide by 2 (DIRECT=0 and PSEL=0)
Pawel Zarembski 0:01f31e923fe2 266 LPC_CGU->PLL1_CTRL &= ~((0x03 << 8) | CGU_PLL1_DIRECT_MASK);
Pawel Zarembski 0:01f31e923fe2 267 // 6. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates at
Pawel Zarembski 0:01f31e923fe2 268 // the mid frequency range
Pawel Zarembski 0:01f31e923fe2 269 CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
Pawel Zarembski 0:01f31e923fe2 270 SystemCoreClock = (12000000 * (msel + 1)) / ((nsel + 1) * 2);
Pawel Zarembski 0:01f31e923fe2 271 // 7. Wait 20us
Pawel Zarembski 0:01f31e923fe2 272 cgu_WaitUS(20);
Pawel Zarembski 0:01f31e923fe2 273 // 8. Set PLL P-divider to direct output mode (DIRECT=1)
Pawel Zarembski 0:01f31e923fe2 274 LPC_CGU->PLL1_CTRL |= CGU_PLL1_DIRECT_MASK;
Pawel Zarembski 0:01f31e923fe2 275 // The BASE_M4_CLK now operates in the high frequency range
Pawel Zarembski 0:01f31e923fe2 276 CGU_UpdateClock();
Pawel Zarembski 0:01f31e923fe2 277 SystemCoreClock = (12000000 * (msel + 1)) / (nsel + 1);
Pawel Zarembski 0:01f31e923fe2 278 return 0;
Pawel Zarembski 0:01f31e923fe2 279 }
Pawel Zarembski 0:01f31e923fe2 280
Pawel Zarembski 0:01f31e923fe2 281 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 282 * @brief Configure power for individual peripheral
Pawel Zarembski 0:01f31e923fe2 283 * @param[in] PPType peripheral type, should be:
Pawel Zarembski 0:01f31e923fe2 284 * - CGU_PERIPHERAL_ADC0 :ADC0
Pawel Zarembski 0:01f31e923fe2 285 * - CGU_PERIPHERAL_ADC1 :ADC1
Pawel Zarembski 0:01f31e923fe2 286 * - CGU_PERIPHERAL_AES :AES
Pawel Zarembski 0:01f31e923fe2 287 * - CGU_PERIPHERAL_APB1_BUS :APB1 bus
Pawel Zarembski 0:01f31e923fe2 288 * - CGU_PERIPHERAL_APB3_BUS :APB3 bus
Pawel Zarembski 0:01f31e923fe2 289 * - CGU_PERIPHERAL_CAN :CAN
Pawel Zarembski 0:01f31e923fe2 290 * - CGU_PERIPHERAL_CREG :CREG
Pawel Zarembski 0:01f31e923fe2 291 * - CGU_PERIPHERAL_DAC :DAC
Pawel Zarembski 0:01f31e923fe2 292 * - CGU_PERIPHERAL_DMA :DMA
Pawel Zarembski 0:01f31e923fe2 293 * - CGU_PERIPHERAL_EMC :EMC
Pawel Zarembski 0:01f31e923fe2 294 * - CGU_PERIPHERAL_ETHERNET :ETHERNET
Pawel Zarembski 0:01f31e923fe2 295 * - CGU_PERIPHERAL_GPIO :GPIO
Pawel Zarembski 0:01f31e923fe2 296 * - CGU_PERIPHERAL_I2C0 :I2C0
Pawel Zarembski 0:01f31e923fe2 297 * - CGU_PERIPHERAL_I2C1 :I2C1
Pawel Zarembski 0:01f31e923fe2 298 * - CGU_PERIPHERAL_I2S :I2S
Pawel Zarembski 0:01f31e923fe2 299 * - CGU_PERIPHERAL_LCD :LCD
Pawel Zarembski 0:01f31e923fe2 300 * - CGU_PERIPHERAL_M3CORE :M3 core
Pawel Zarembski 0:01f31e923fe2 301 * - CGU_PERIPHERAL_M3_BUS :M3 bus
Pawel Zarembski 0:01f31e923fe2 302 * - CGU_PERIPHERAL_MOTOCON :Motor control
Pawel Zarembski 0:01f31e923fe2 303 * - CGU_PERIPHERAL_QEI :QEI
Pawel Zarembski 0:01f31e923fe2 304 * - CGU_PERIPHERAL_RITIMER :RIT timer
Pawel Zarembski 0:01f31e923fe2 305 * - CGU_PERIPHERAL_SCT :SCT
Pawel Zarembski 0:01f31e923fe2 306 * - CGU_PERIPHERAL_SCU :SCU
Pawel Zarembski 0:01f31e923fe2 307 * - CGU_PERIPHERAL_SDIO :SDIO
Pawel Zarembski 0:01f31e923fe2 308 * - CGU_PERIPHERAL_SPIFI :SPIFI
Pawel Zarembski 0:01f31e923fe2 309 * - CGU_PERIPHERAL_SSP0 :SSP0
Pawel Zarembski 0:01f31e923fe2 310 * - CGU_PERIPHERAL_SSP1 :SSP1
Pawel Zarembski 0:01f31e923fe2 311 * - CGU_PERIPHERAL_TIMER0 :TIMER0
Pawel Zarembski 0:01f31e923fe2 312 * - CGU_PERIPHERAL_TIMER1 :TIMER1
Pawel Zarembski 0:01f31e923fe2 313 * - CGU_PERIPHERAL_TIMER2 :TIMER2
Pawel Zarembski 0:01f31e923fe2 314 * - CGU_PERIPHERAL_TIMER3 :TIMER3
Pawel Zarembski 0:01f31e923fe2 315 * - CGU_PERIPHERAL_UART0 :UART0
Pawel Zarembski 0:01f31e923fe2 316 * - CGU_PERIPHERAL_UART1 :UART1
Pawel Zarembski 0:01f31e923fe2 317 * - CGU_PERIPHERAL_UART2 :UART2
Pawel Zarembski 0:01f31e923fe2 318 * - CGU_PERIPHERAL_UART3 :UART3
Pawel Zarembski 0:01f31e923fe2 319 * - CGU_PERIPHERAL_USB0 :USB0
Pawel Zarembski 0:01f31e923fe2 320 * - CGU_PERIPHERAL_USB1 :USB1
Pawel Zarembski 0:01f31e923fe2 321 * - CGU_PERIPHERAL_WWDT :WWDT
Pawel Zarembski 0:01f31e923fe2 322 * @param[in] en status, should be:
Pawel Zarembski 0:01f31e923fe2 323 * - ENABLE: Enable power
Pawel Zarembski 0:01f31e923fe2 324 * - DISABLE: Disable power
Pawel Zarembski 0:01f31e923fe2 325 * @return Configure status, could be:
Pawel Zarembski 0:01f31e923fe2 326 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 327 * - Other: error
Pawel Zarembski 0:01f31e923fe2 328 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 329 uint32_t CGU_ConfigPWR(CGU_PERIPHERAL_T PPType, FunctionalState en)
Pawel Zarembski 0:01f31e923fe2 330 {
Pawel Zarembski 0:01f31e923fe2 331 if (PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0) {
Pawel Zarembski 0:01f31e923fe2 332 return CGU_ERROR_INVALID_PARAM;
Pawel Zarembski 0:01f31e923fe2 333 }
Pawel Zarembski 0:01f31e923fe2 334
Pawel Zarembski 0:01f31e923fe2 335 if (en == DISABLE) { /* Going to disable clock */
Pawel Zarembski 0:01f31e923fe2 336 /*Get Reg branch status */
Pawel Zarembski 0:01f31e923fe2 337 if (CGU_PERIPHERAL_Info[PPType].RegBranchOffset != 0 &&
Pawel Zarembski 0:01f31e923fe2 338 CGU_REG_BRANCH_STATUS(PPType) & 1) {
Pawel Zarembski 0:01f31e923fe2 339 CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
Pawel Zarembski 0:01f31e923fe2 340
Pawel Zarembski 0:01f31e923fe2 341 while (CGU_REG_BRANCH_STATUS(PPType) & 1);
Pawel Zarembski 0:01f31e923fe2 342 }
Pawel Zarembski 0:01f31e923fe2 343
Pawel Zarembski 0:01f31e923fe2 344 /* GetBase Status*/
Pawel Zarembski 0:01f31e923fe2 345 if ((CGU_PERIPHERAL_Info[PPType].RegBaseEntity != CGU_ENTITY_NONE) &&
Pawel Zarembski 0:01f31e923fe2 346 CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0) {
Pawel Zarembski 0:01f31e923fe2 347 /* Disable Base */
Pawel Zarembski 0:01f31e923fe2 348 CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 0);
Pawel Zarembski 0:01f31e923fe2 349 }
Pawel Zarembski 0:01f31e923fe2 350
Pawel Zarembski 0:01f31e923fe2 351 /* Same for Peripheral */
Pawel Zarembski 0:01f31e923fe2 352 if ((CGU_PERIPHERAL_Info[PPType].PerBranchOffset != 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
Pawel Zarembski 0:01f31e923fe2 353 CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
Pawel Zarembski 0:01f31e923fe2 354
Pawel Zarembski 0:01f31e923fe2 355 while (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);
Pawel Zarembski 0:01f31e923fe2 356 }
Pawel Zarembski 0:01f31e923fe2 357
Pawel Zarembski 0:01f31e923fe2 358 /* GetBase Status*/
Pawel Zarembski 0:01f31e923fe2 359 if ((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
Pawel Zarembski 0:01f31e923fe2 360 CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0) {
Pawel Zarembski 0:01f31e923fe2 361 /* Disable Base */
Pawel Zarembski 0:01f31e923fe2 362 CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 0);
Pawel Zarembski 0:01f31e923fe2 363 }
Pawel Zarembski 0:01f31e923fe2 364
Pawel Zarembski 0:01f31e923fe2 365 } else {
Pawel Zarembski 0:01f31e923fe2 366 /* enable */
Pawel Zarembski 0:01f31e923fe2 367 /* GetBase Status*/
Pawel Zarembski 0:01f31e923fe2 368 if ((CGU_PERIPHERAL_Info[PPType].RegBaseEntity != CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK) {
Pawel Zarembski 0:01f31e923fe2 369 /* Enable Base */
Pawel Zarembski 0:01f31e923fe2 370 CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);
Pawel Zarembski 0:01f31e923fe2 371 }
Pawel Zarembski 0:01f31e923fe2 372
Pawel Zarembski 0:01f31e923fe2 373 /*Get Reg branch status */
Pawel Zarembski 0:01f31e923fe2 374 if ((CGU_PERIPHERAL_Info[PPType].RegBranchOffset != 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
Pawel Zarembski 0:01f31e923fe2 375 CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
Pawel Zarembski 0:01f31e923fe2 376
Pawel Zarembski 0:01f31e923fe2 377 while (!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
Pawel Zarembski 0:01f31e923fe2 378 }
Pawel Zarembski 0:01f31e923fe2 379
Pawel Zarembski 0:01f31e923fe2 380 /* Same for Peripheral */
Pawel Zarembski 0:01f31e923fe2 381 /* GetBase Status*/
Pawel Zarembski 0:01f31e923fe2 382 if ((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
Pawel Zarembski 0:01f31e923fe2 383 (CGU_PER_BASE_CTRL(PPType) & 1)) {
Pawel Zarembski 0:01f31e923fe2 384 /* Enable Base */
Pawel Zarembski 0:01f31e923fe2 385 CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);
Pawel Zarembski 0:01f31e923fe2 386 }
Pawel Zarembski 0:01f31e923fe2 387
Pawel Zarembski 0:01f31e923fe2 388 /*Get Reg branch status */
Pawel Zarembski 0:01f31e923fe2 389 if ((CGU_PERIPHERAL_Info[PPType].PerBranchOffset != 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
Pawel Zarembski 0:01f31e923fe2 390 CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
Pawel Zarembski 0:01f31e923fe2 391
Pawel Zarembski 0:01f31e923fe2 392 while (!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
Pawel Zarembski 0:01f31e923fe2 393 }
Pawel Zarembski 0:01f31e923fe2 394 }
Pawel Zarembski 0:01f31e923fe2 395
Pawel Zarembski 0:01f31e923fe2 396 if (CGU_PERIPHERAL_Info[PPType].next) {
Pawel Zarembski 0:01f31e923fe2 397 return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);
Pawel Zarembski 0:01f31e923fe2 398 }
Pawel Zarembski 0:01f31e923fe2 399
Pawel Zarembski 0:01f31e923fe2 400 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 401 }
Pawel Zarembski 0:01f31e923fe2 402
Pawel Zarembski 0:01f31e923fe2 403
Pawel Zarembski 0:01f31e923fe2 404 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 405 * @brief Get peripheral clock frequency
Pawel Zarembski 0:01f31e923fe2 406 * @param[in] Clock Peripheral type, should be:
Pawel Zarembski 0:01f31e923fe2 407 * - CGU_PERIPHERAL_ADC0 :ADC0
Pawel Zarembski 0:01f31e923fe2 408 * - CGU_PERIPHERAL_ADC1 :ADC1
Pawel Zarembski 0:01f31e923fe2 409 * - CGU_PERIPHERAL_AES :AES
Pawel Zarembski 0:01f31e923fe2 410 * - CGU_PERIPHERAL_APB1_BUS :APB1 bus
Pawel Zarembski 0:01f31e923fe2 411 * - CGU_PERIPHERAL_APB3_BUS :APB3 bus
Pawel Zarembski 0:01f31e923fe2 412 * - CGU_PERIPHERAL_CAN :CAN
Pawel Zarembski 0:01f31e923fe2 413 * - CGU_PERIPHERAL_CREG :CREG
Pawel Zarembski 0:01f31e923fe2 414 * - CGU_PERIPHERAL_DAC :DAC
Pawel Zarembski 0:01f31e923fe2 415 * - CGU_PERIPHERAL_DMA :DMA
Pawel Zarembski 0:01f31e923fe2 416 * - CGU_PERIPHERAL_EMC :EMC
Pawel Zarembski 0:01f31e923fe2 417 * - CGU_PERIPHERAL_ETHERNET :ETHERNET
Pawel Zarembski 0:01f31e923fe2 418 * - CGU_PERIPHERAL_GPIO :GPIO
Pawel Zarembski 0:01f31e923fe2 419 * - CGU_PERIPHERAL_I2C0 :I2C0
Pawel Zarembski 0:01f31e923fe2 420 * - CGU_PERIPHERAL_I2C1 :I2C1
Pawel Zarembski 0:01f31e923fe2 421 * - CGU_PERIPHERAL_I2S :I2S
Pawel Zarembski 0:01f31e923fe2 422 * - CGU_PERIPHERAL_LCD :LCD
Pawel Zarembski 0:01f31e923fe2 423 * - CGU_PERIPHERAL_M3CORE :M3 core
Pawel Zarembski 0:01f31e923fe2 424 * - CGU_PERIPHERAL_M3_BUS :M3 bus
Pawel Zarembski 0:01f31e923fe2 425 * - CGU_PERIPHERAL_MOTOCON :Motor control
Pawel Zarembski 0:01f31e923fe2 426 * - CGU_PERIPHERAL_QEI :QEI
Pawel Zarembski 0:01f31e923fe2 427 * - CGU_PERIPHERAL_RITIMER :RIT timer
Pawel Zarembski 0:01f31e923fe2 428 * - CGU_PERIPHERAL_SCT :SCT
Pawel Zarembski 0:01f31e923fe2 429 * - CGU_PERIPHERAL_SCU :SCU
Pawel Zarembski 0:01f31e923fe2 430 * - CGU_PERIPHERAL_SDIO :SDIO
Pawel Zarembski 0:01f31e923fe2 431 * - CGU_PERIPHERAL_SPIFI :SPIFI
Pawel Zarembski 0:01f31e923fe2 432 * - CGU_PERIPHERAL_SSP0 :SSP0
Pawel Zarembski 0:01f31e923fe2 433 * - CGU_PERIPHERAL_SSP1 :SSP1
Pawel Zarembski 0:01f31e923fe2 434 * - CGU_PERIPHERAL_TIMER0 :TIMER0
Pawel Zarembski 0:01f31e923fe2 435 * - CGU_PERIPHERAL_TIMER1 :TIMER1
Pawel Zarembski 0:01f31e923fe2 436 * - CGU_PERIPHERAL_TIMER2 :TIMER2
Pawel Zarembski 0:01f31e923fe2 437 * - CGU_PERIPHERAL_TIMER3 :TIMER3
Pawel Zarembski 0:01f31e923fe2 438 * - CGU_PERIPHERAL_UART0 :UART0
Pawel Zarembski 0:01f31e923fe2 439 * - CGU_PERIPHERAL_UART1 :UART1
Pawel Zarembski 0:01f31e923fe2 440 * - CGU_PERIPHERAL_UART2 :UART2
Pawel Zarembski 0:01f31e923fe2 441 * - CGU_PERIPHERAL_UART3 :UART3
Pawel Zarembski 0:01f31e923fe2 442 * - CGU_PERIPHERAL_USB0 :USB0
Pawel Zarembski 0:01f31e923fe2 443 * - CGU_PERIPHERAL_USB1 :USB1
Pawel Zarembski 0:01f31e923fe2 444 * - CGU_PERIPHERAL_WWDT :WWDT
Pawel Zarembski 0:01f31e923fe2 445 * @return Return frequently value
Pawel Zarembski 0:01f31e923fe2 446 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 447 uint32_t CGU_GetPCLKFrequency(CGU_PERIPHERAL_T Clock)
Pawel Zarembski 0:01f31e923fe2 448 {
Pawel Zarembski 0:01f31e923fe2 449 uint32_t ClkSrc;
Pawel Zarembski 0:01f31e923fe2 450
Pawel Zarembski 0:01f31e923fe2 451 if (Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0) {
Pawel Zarembski 0:01f31e923fe2 452 return CGU_ERROR_INVALID_PARAM;
Pawel Zarembski 0:01f31e923fe2 453 }
Pawel Zarembski 0:01f31e923fe2 454
Pawel Zarembski 0:01f31e923fe2 455 if (CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE) {
Pawel Zarembski 0:01f31e923fe2 456 /* Get Base Clock Source */
Pawel Zarembski 0:01f31e923fe2 457 ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
Pawel Zarembski 0:01f31e923fe2 458
Pawel Zarembski 0:01f31e923fe2 459 /* GetBase Status*/
Pawel Zarembski 0:01f31e923fe2 460 if (CGU_PER_BASE_CTRL(Clock) & 1) {
Pawel Zarembski 0:01f31e923fe2 461 return 0;
Pawel Zarembski 0:01f31e923fe2 462 }
Pawel Zarembski 0:01f31e923fe2 463
Pawel Zarembski 0:01f31e923fe2 464 /* check Branch if it is enabled */
Pawel Zarembski 0:01f31e923fe2 465 if ((CGU_PERIPHERAL_Info[Clock].PerBranchOffset != 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
Pawel Zarembski 0:01f31e923fe2 466 return 0;
Pawel Zarembski 0:01f31e923fe2 467 }
Pawel Zarembski 0:01f31e923fe2 468
Pawel Zarembski 0:01f31e923fe2 469 } else {
Pawel Zarembski 0:01f31e923fe2 470 if (CGU_REG_BASE_CTRL(Clock) & 1) {
Pawel Zarembski 0:01f31e923fe2 471 return 0;
Pawel Zarembski 0:01f31e923fe2 472 }
Pawel Zarembski 0:01f31e923fe2 473
Pawel Zarembski 0:01f31e923fe2 474 ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
Pawel Zarembski 0:01f31e923fe2 475
Pawel Zarembski 0:01f31e923fe2 476 /* check Branch if it is enabled */
Pawel Zarembski 0:01f31e923fe2 477 if ((CGU_PERIPHERAL_Info[Clock].RegBranchOffset != 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
Pawel Zarembski 0:01f31e923fe2 478 return 0;
Pawel Zarembski 0:01f31e923fe2 479 }
Pawel Zarembski 0:01f31e923fe2 480 }
Pawel Zarembski 0:01f31e923fe2 481
Pawel Zarembski 0:01f31e923fe2 482 return CGU_ClockSourceFrequency[ClkSrc];
Pawel Zarembski 0:01f31e923fe2 483 }
Pawel Zarembski 0:01f31e923fe2 484
Pawel Zarembski 0:01f31e923fe2 485
Pawel Zarembski 0:01f31e923fe2 486 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 487 * @brief Update clock
Pawel Zarembski 0:01f31e923fe2 488 * @param[in] None
Pawel Zarembski 0:01f31e923fe2 489 * @return None
Pawel Zarembski 0:01f31e923fe2 490 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 491 void CGU_UpdateClock(void)
Pawel Zarembski 0:01f31e923fe2 492 {
Pawel Zarembski 0:01f31e923fe2 493 uint32_t ClkSrc;
Pawel Zarembski 0:01f31e923fe2 494 uint32_t div;
Pawel Zarembski 0:01f31e923fe2 495 uint32_t divisor;
Pawel Zarembski 0:01f31e923fe2 496 int32_t RegOffset;
Pawel Zarembski 0:01f31e923fe2 497
Pawel Zarembski 0:01f31e923fe2 498 /* 32OSC */
Pawel Zarembski 0:01f31e923fe2 499 if (ISBITSET(LPC_CREG->CREG0, 1) && ISBITCLR(LPC_CREG->CREG0, 3)) {
Pawel Zarembski 0:01f31e923fe2 500 CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;
Pawel Zarembski 0:01f31e923fe2 501
Pawel Zarembski 0:01f31e923fe2 502 } else {
Pawel Zarembski 0:01f31e923fe2 503 CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;
Pawel Zarembski 0:01f31e923fe2 504 }
Pawel Zarembski 0:01f31e923fe2 505
Pawel Zarembski 0:01f31e923fe2 506 /*PLL0*/
Pawel Zarembski 0:01f31e923fe2 507 /* PLL1 */
Pawel Zarembski 0:01f31e923fe2 508 if (ISBITCLR(LPC_CGU->PLL1_CTRL, 0) /* Enabled */ /* EA ANDLI: Original code tested bit 1 which is BYPASS, not PD */
Pawel Zarembski 0:01f31e923fe2 509 && (LPC_CGU->PLL1_STAT & 1)) { /* Locked? */
Pawel Zarembski 0:01f31e923fe2 510 ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK) >> 24;
Pawel Zarembski 0:01f31e923fe2 511 CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *
Pawel Zarembski 0:01f31e923fe2 512 (((LPC_CGU->PLL1_CTRL >> 16) & 0xFF) + 1);
Pawel Zarembski 0:01f31e923fe2 513
Pawel Zarembski 0:01f31e923fe2 514 } else {
Pawel Zarembski 0:01f31e923fe2 515 CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;
Pawel Zarembski 0:01f31e923fe2 516 }
Pawel Zarembski 0:01f31e923fe2 517
Pawel Zarembski 0:01f31e923fe2 518 /* DIV */
Pawel Zarembski 0:01f31e923fe2 519 for (div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++) {
Pawel Zarembski 0:01f31e923fe2 520 RegOffset = CGU_Entity_ControlReg_Offset[div];
Pawel Zarembski 0:01f31e923fe2 521
Pawel Zarembski 0:01f31e923fe2 522 if (ISBITCLR(CGU_ADDRESS32(LPC_CGU, RegOffset), 1)) {
Pawel Zarembski 0:01f31e923fe2 523 ClkSrc = (CGU_ADDRESS32(LPC_CGU, RegOffset) & CGU_CTRL_SRC_MASK) >> 24;
Pawel Zarembski 0:01f31e923fe2 524 divisor = (CGU_ADDRESS32(LPC_CGU, RegOffset) >> 2) & 0xFF;
Pawel Zarembski 0:01f31e923fe2 525 divisor ++;
Pawel Zarembski 0:01f31e923fe2 526 CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;
Pawel Zarembski 0:01f31e923fe2 527
Pawel Zarembski 0:01f31e923fe2 528 } else {
Pawel Zarembski 0:01f31e923fe2 529 CGU_ClockSourceFrequency[div] = 0;
Pawel Zarembski 0:01f31e923fe2 530 }
Pawel Zarembski 0:01f31e923fe2 531 }
Pawel Zarembski 0:01f31e923fe2 532 }
Pawel Zarembski 0:01f31e923fe2 533
Pawel Zarembski 0:01f31e923fe2 534 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 535 * @brief Set XTAL oscillator value
Pawel Zarembski 0:01f31e923fe2 536 * @param[in] ClockFrequency XTAL Frequency value
Pawel Zarembski 0:01f31e923fe2 537 * @return Setting status, could be:
Pawel Zarembski 0:01f31e923fe2 538 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 539 * - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range
Pawel Zarembski 0:01f31e923fe2 540 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 541 uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency)
Pawel Zarembski 0:01f31e923fe2 542 {
Pawel Zarembski 0:01f31e923fe2 543 if (ClockFrequency < 15000000) {
Pawel Zarembski 0:01f31e923fe2 544 LPC_CGU->XTAL_OSC_CTRL &= ~(1 << 2);
Pawel Zarembski 0:01f31e923fe2 545
Pawel Zarembski 0:01f31e923fe2 546 } else if (ClockFrequency < 25000000) {
Pawel Zarembski 0:01f31e923fe2 547 LPC_CGU->XTAL_OSC_CTRL |= (1 << 2);
Pawel Zarembski 0:01f31e923fe2 548
Pawel Zarembski 0:01f31e923fe2 549 } else {
Pawel Zarembski 0:01f31e923fe2 550 return CGU_ERROR_FREQ_OUTOF_RANGE;
Pawel Zarembski 0:01f31e923fe2 551 }
Pawel Zarembski 0:01f31e923fe2 552
Pawel Zarembski 0:01f31e923fe2 553 CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;
Pawel Zarembski 0:01f31e923fe2 554 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 555 }
Pawel Zarembski 0:01f31e923fe2 556
Pawel Zarembski 0:01f31e923fe2 557
Pawel Zarembski 0:01f31e923fe2 558 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 559 * @brief Set clock divider
Pawel Zarembski 0:01f31e923fe2 560 * @param[in] SelectDivider Clock source, should be:
Pawel Zarembski 0:01f31e923fe2 561 * - CGU_CLKSRC_IDIVA :Integer divider register A
Pawel Zarembski 0:01f31e923fe2 562 * - CGU_CLKSRC_IDIVB :Integer divider register B
Pawel Zarembski 0:01f31e923fe2 563 * - CGU_CLKSRC_IDIVC :Integer divider register C
Pawel Zarembski 0:01f31e923fe2 564 * - CGU_CLKSRC_IDIVD :Integer divider register D
Pawel Zarembski 0:01f31e923fe2 565 * - CGU_CLKSRC_IDIVE :Integer divider register E
Pawel Zarembski 0:01f31e923fe2 566 * @param[in] divisor Divisor value, should be: 0..255
Pawel Zarembski 0:01f31e923fe2 567 * @return Setting status, could be:
Pawel Zarembski 0:01f31e923fe2 568 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 569 * - CGU_ERROR_INVALID_ENTITY: Invalid entity
Pawel Zarembski 0:01f31e923fe2 570 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 571 /* divisor number must >=1*/
Pawel Zarembski 0:01f31e923fe2 572 uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor)
Pawel Zarembski 0:01f31e923fe2 573 {
Pawel Zarembski 0:01f31e923fe2 574 int32_t RegOffset;
Pawel Zarembski 0:01f31e923fe2 575 uint32_t tempReg;
Pawel Zarembski 0:01f31e923fe2 576
Pawel Zarembski 0:01f31e923fe2 577 if (SelectDivider >= CGU_CLKSRC_IDIVA && SelectDivider <= CGU_CLKSRC_IDIVE) {
Pawel Zarembski 0:01f31e923fe2 578 RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];
Pawel Zarembski 0:01f31e923fe2 579
Pawel Zarembski 0:01f31e923fe2 580 if (RegOffset == -1) {
Pawel Zarembski 0:01f31e923fe2 581 return CGU_ERROR_INVALID_ENTITY;
Pawel Zarembski 0:01f31e923fe2 582 }
Pawel Zarembski 0:01f31e923fe2 583
Pawel Zarembski 0:01f31e923fe2 584 tempReg = CGU_ADDRESS32(LPC_CGU, RegOffset);
Pawel Zarembski 0:01f31e923fe2 585 tempReg &= ~(0xFF << 2);
Pawel Zarembski 0:01f31e923fe2 586 tempReg |= ((divisor - 1) & 0xFF) << 2;
Pawel Zarembski 0:01f31e923fe2 587 CGU_ADDRESS32(LPC_CGU, RegOffset) = tempReg;
Pawel Zarembski 0:01f31e923fe2 588 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 589 }
Pawel Zarembski 0:01f31e923fe2 590
Pawel Zarembski 0:01f31e923fe2 591 return CGU_ERROR_INVALID_ENTITY;
Pawel Zarembski 0:01f31e923fe2 592 }
Pawel Zarembski 0:01f31e923fe2 593
Pawel Zarembski 0:01f31e923fe2 594 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 595 * @brief Enable clock entity
Pawel Zarembski 0:01f31e923fe2 596 * @param[in] ClockEntity Clock entity, should be:
Pawel Zarembski 0:01f31e923fe2 597 * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
Pawel Zarembski 0:01f31e923fe2 598 * - CGU_CLKSRC_IRC :IRC clock
Pawel Zarembski 0:01f31e923fe2 599 * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
Pawel Zarembski 0:01f31e923fe2 600 * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
Pawel Zarembski 0:01f31e923fe2 601 * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
Pawel Zarembski 0:01f31e923fe2 602 * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
Pawel Zarembski 0:01f31e923fe2 603 * - CGU_CLKSRC_PLL0 :PLL0 clock
Pawel Zarembski 0:01f31e923fe2 604 * - CGU_CLKSRC_PLL1 :PLL1 clock
Pawel Zarembski 0:01f31e923fe2 605 * - CGU_CLKSRC_IDIVA :Integer divider register A
Pawel Zarembski 0:01f31e923fe2 606 * - CGU_CLKSRC_IDIVB :Integer divider register B
Pawel Zarembski 0:01f31e923fe2 607 * - CGU_CLKSRC_IDIVC :Integer divider register C
Pawel Zarembski 0:01f31e923fe2 608 * - CGU_CLKSRC_IDIVD :Integer divider register D
Pawel Zarembski 0:01f31e923fe2 609 * - CGU_CLKSRC_IDIVE :Integer divider register E
Pawel Zarembski 0:01f31e923fe2 610 * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
Pawel Zarembski 0:01f31e923fe2 611 * - CGU_BASE_USB0 :Base clock for USB0
Pawel Zarembski 0:01f31e923fe2 612 * - CGU_BASE_PERIPH :Base clock for Peripheral bus
Pawel Zarembski 0:01f31e923fe2 613 * - CGU_BASE_USB1 :Base clock for USB1
Pawel Zarembski 0:01f31e923fe2 614 * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
Pawel Zarembski 0:01f31e923fe2 615 * and APB peripheral blocks #0 and #2
Pawel Zarembski 0:01f31e923fe2 616 * - CGU_BASE_SPIFI :Base clock for SPIFI
Pawel Zarembski 0:01f31e923fe2 617 * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
Pawel Zarembski 0:01f31e923fe2 618 * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
Pawel Zarembski 0:01f31e923fe2 619 * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
Pawel Zarembski 0:01f31e923fe2 620 * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
Pawel Zarembski 0:01f31e923fe2 621 * - CGU_BASE_LCD :Base clock for LCD
Pawel Zarembski 0:01f31e923fe2 622 * - CGU_BASE_SDIO :Base clock for SDIO card reader
Pawel Zarembski 0:01f31e923fe2 623 * - CGU_BASE_SSP0 :Base clock for SSP0
Pawel Zarembski 0:01f31e923fe2 624 * - CGU_BASE_SSP1 :Base clock for SSP1
Pawel Zarembski 0:01f31e923fe2 625 * - CGU_BASE_UART0 :Base clock for UART0
Pawel Zarembski 0:01f31e923fe2 626 * - CGU_BASE_UART1 :Base clock for UART1
Pawel Zarembski 0:01f31e923fe2 627 * - CGU_BASE_UART2 :Base clock for UART2
Pawel Zarembski 0:01f31e923fe2 628 * - CGU_BASE_UART3 :Base clock for UART3
Pawel Zarembski 0:01f31e923fe2 629 * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
Pawel Zarembski 0:01f31e923fe2 630 * @param[in] en status, should be:
Pawel Zarembski 0:01f31e923fe2 631 * - ENABLE: Enable power
Pawel Zarembski 0:01f31e923fe2 632 * - DISABLE: Disable power
Pawel Zarembski 0:01f31e923fe2 633 * @return Setting status, could be:
Pawel Zarembski 0:01f31e923fe2 634 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 635 * - CGU_ERROR_INVALID_ENTITY: Invalid entity
Pawel Zarembski 0:01f31e923fe2 636 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 637 uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en)
Pawel Zarembski 0:01f31e923fe2 638 {
Pawel Zarembski 0:01f31e923fe2 639 int32_t RegOffset;
Pawel Zarembski 0:01f31e923fe2 640 int32_t i;
Pawel Zarembski 0:01f31e923fe2 641
Pawel Zarembski 0:01f31e923fe2 642 if (ClockEntity == CGU_CLKSRC_32KHZ_OSC) {
Pawel Zarembski 0:01f31e923fe2 643 if (en) {
Pawel Zarembski 0:01f31e923fe2 644 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
Pawel Zarembski 0:01f31e923fe2 645 LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
Pawel Zarembski 0:01f31e923fe2 646
Pawel Zarembski 0:01f31e923fe2 647 } else {
Pawel Zarembski 0:01f31e923fe2 648 LPC_CREG->CREG0 &= ~((1 << 1) | (1 << 0));
Pawel Zarembski 0:01f31e923fe2 649 LPC_CREG->CREG0 |= (1 << 3);
Pawel Zarembski 0:01f31e923fe2 650 }
Pawel Zarembski 0:01f31e923fe2 651
Pawel Zarembski 0:01f31e923fe2 652 for (i = 0; i < 1000000; i++);
Pawel Zarembski 0:01f31e923fe2 653
Pawel Zarembski 0:01f31e923fe2 654 } else if (ClockEntity == CGU_CLKSRC_ENET_RX_CLK) {
Pawel Zarembski 0:01f31e923fe2 655 scu_pinmux(0xC , 0 , MD_PLN, FUNC3);
Pawel Zarembski 0:01f31e923fe2 656
Pawel Zarembski 0:01f31e923fe2 657 } else if (ClockEntity == CGU_CLKSRC_ENET_TX_CLK) {
Pawel Zarembski 0:01f31e923fe2 658 scu_pinmux(0x1 , 19 , MD_PLN, FUNC0);
Pawel Zarembski 0:01f31e923fe2 659
Pawel Zarembski 0:01f31e923fe2 660 } else if (ClockEntity == CGU_CLKSRC_GP_CLKIN) {
Pawel Zarembski 0:01f31e923fe2 661 } else if (ClockEntity == CGU_CLKSRC_TCK) {
Pawel Zarembski 0:01f31e923fe2 662 } else if (ClockEntity == CGU_CLKSRC_XTAL_OSC) {
Pawel Zarembski 0:01f31e923fe2 663 if (!en) {
Pawel Zarembski 0:01f31e923fe2 664 LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;
Pawel Zarembski 0:01f31e923fe2 665
Pawel Zarembski 0:01f31e923fe2 666 } else {
Pawel Zarembski 0:01f31e923fe2 667 LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;
Pawel Zarembski 0:01f31e923fe2 668 }
Pawel Zarembski 0:01f31e923fe2 669
Pawel Zarembski 0:01f31e923fe2 670 /*Delay for stable clock*/
Pawel Zarembski 0:01f31e923fe2 671 for (i = 0; i < 1000000; i++);
Pawel Zarembski 0:01f31e923fe2 672
Pawel Zarembski 0:01f31e923fe2 673 } else {
Pawel Zarembski 0:01f31e923fe2 674 RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
Pawel Zarembski 0:01f31e923fe2 675
Pawel Zarembski 0:01f31e923fe2 676 if (RegOffset == -1) {
Pawel Zarembski 0:01f31e923fe2 677 return CGU_ERROR_INVALID_ENTITY;
Pawel Zarembski 0:01f31e923fe2 678 }
Pawel Zarembski 0:01f31e923fe2 679
Pawel Zarembski 0:01f31e923fe2 680 if (!en) {
Pawel Zarembski 0:01f31e923fe2 681 CGU_ADDRESS32(CGU_CGU_ADDR, RegOffset) |= CGU_CTRL_EN_MASK;
Pawel Zarembski 0:01f31e923fe2 682
Pawel Zarembski 0:01f31e923fe2 683 } else {
Pawel Zarembski 0:01f31e923fe2 684 CGU_ADDRESS32(CGU_CGU_ADDR, RegOffset) &= ~CGU_CTRL_EN_MASK;
Pawel Zarembski 0:01f31e923fe2 685
Pawel Zarembski 0:01f31e923fe2 686 /*if PLL is selected check if it is locked */
Pawel Zarembski 0:01f31e923fe2 687 if (ClockEntity == CGU_CLKSRC_PLL0) {
Pawel Zarembski 0:01f31e923fe2 688 while ((LPC_CGU->PLL0USB_STAT & 1) == 0x0);
Pawel Zarembski 0:01f31e923fe2 689 }
Pawel Zarembski 0:01f31e923fe2 690
Pawel Zarembski 0:01f31e923fe2 691 if (ClockEntity == CGU_CLKSRC_PLL0_AUDIO) {
Pawel Zarembski 0:01f31e923fe2 692 while ((LPC_CGU->PLL0AUDIO_STAT & 1) == 0x0);
Pawel Zarembski 0:01f31e923fe2 693 }
Pawel Zarembski 0:01f31e923fe2 694
Pawel Zarembski 0:01f31e923fe2 695 if (ClockEntity == CGU_CLKSRC_PLL1) {
Pawel Zarembski 0:01f31e923fe2 696 while ((LPC_CGU->PLL1_STAT & 1) == 0x0);
Pawel Zarembski 0:01f31e923fe2 697
Pawel Zarembski 0:01f31e923fe2 698 /*post check lock status */
Pawel Zarembski 0:01f31e923fe2 699 if (!(LPC_CGU->PLL1_STAT & 1))
Pawel Zarembski 0:01f31e923fe2 700 while (1);
Pawel Zarembski 0:01f31e923fe2 701 }
Pawel Zarembski 0:01f31e923fe2 702 }
Pawel Zarembski 0:01f31e923fe2 703 }
Pawel Zarembski 0:01f31e923fe2 704
Pawel Zarembski 0:01f31e923fe2 705 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 706 }
Pawel Zarembski 0:01f31e923fe2 707
Pawel Zarembski 0:01f31e923fe2 708 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 709 * @brief Connect entity clock source
Pawel Zarembski 0:01f31e923fe2 710 * @param[in] ClockSource Clock source, should be:
Pawel Zarembski 0:01f31e923fe2 711 * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
Pawel Zarembski 0:01f31e923fe2 712 * - CGU_CLKSRC_IRC :IRC clock
Pawel Zarembski 0:01f31e923fe2 713 * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
Pawel Zarembski 0:01f31e923fe2 714 * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
Pawel Zarembski 0:01f31e923fe2 715 * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
Pawel Zarembski 0:01f31e923fe2 716 * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
Pawel Zarembski 0:01f31e923fe2 717 * - CGU_CLKSRC_PLL0 :PLL0 clock
Pawel Zarembski 0:01f31e923fe2 718 * - CGU_CLKSRC_PLL1 :PLL1 clock
Pawel Zarembski 0:01f31e923fe2 719 * - CGU_CLKSRC_IDIVA :Integer divider register A
Pawel Zarembski 0:01f31e923fe2 720 * - CGU_CLKSRC_IDIVB :Integer divider register B
Pawel Zarembski 0:01f31e923fe2 721 * - CGU_CLKSRC_IDIVC :Integer divider register C
Pawel Zarembski 0:01f31e923fe2 722 * - CGU_CLKSRC_IDIVD :Integer divider register D
Pawel Zarembski 0:01f31e923fe2 723 * - CGU_CLKSRC_IDIVE :Integer divider register E
Pawel Zarembski 0:01f31e923fe2 724 * @param[in] ClockEntity Clock entity, should be:
Pawel Zarembski 0:01f31e923fe2 725 * - CGU_CLKSRC_PLL0 :PLL0 clock
Pawel Zarembski 0:01f31e923fe2 726 * - CGU_CLKSRC_PLL1 :PLL1 clock
Pawel Zarembski 0:01f31e923fe2 727 * - CGU_CLKSRC_IDIVA :Integer divider register A
Pawel Zarembski 0:01f31e923fe2 728 * - CGU_CLKSRC_IDIVB :Integer divider register B
Pawel Zarembski 0:01f31e923fe2 729 * - CGU_CLKSRC_IDIVC :Integer divider register C
Pawel Zarembski 0:01f31e923fe2 730 * - CGU_CLKSRC_IDIVD :Integer divider register D
Pawel Zarembski 0:01f31e923fe2 731 * - CGU_CLKSRC_IDIVE :Integer divider register E
Pawel Zarembski 0:01f31e923fe2 732 * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
Pawel Zarembski 0:01f31e923fe2 733 * - CGU_BASE_USB0 :Base clock for USB0
Pawel Zarembski 0:01f31e923fe2 734 * - CGU_BASE_USB1 :Base clock for USB1
Pawel Zarembski 0:01f31e923fe2 735 * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
Pawel Zarembski 0:01f31e923fe2 736 * and APB peripheral blocks #0 and #2
Pawel Zarembski 0:01f31e923fe2 737 * - CGU_BASE_SPIFI :Base clock for SPIFI
Pawel Zarembski 0:01f31e923fe2 738 * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
Pawel Zarembski 0:01f31e923fe2 739 * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
Pawel Zarembski 0:01f31e923fe2 740 * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
Pawel Zarembski 0:01f31e923fe2 741 * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
Pawel Zarembski 0:01f31e923fe2 742 * - CGU_BASE_LCD :Base clock for LCD
Pawel Zarembski 0:01f31e923fe2 743 * - CGU_BASE_SDIO :Base clock for SDIO card reader
Pawel Zarembski 0:01f31e923fe2 744 * - CGU_BASE_SSP0 :Base clock for SSP0
Pawel Zarembski 0:01f31e923fe2 745 * - CGU_BASE_SSP1 :Base clock for SSP1
Pawel Zarembski 0:01f31e923fe2 746 * - CGU_BASE_UART0 :Base clock for UART0
Pawel Zarembski 0:01f31e923fe2 747 * - CGU_BASE_UART1 :Base clock for UART1
Pawel Zarembski 0:01f31e923fe2 748 * - CGU_BASE_UART2 :Base clock for UART2
Pawel Zarembski 0:01f31e923fe2 749 * - CGU_BASE_UART3 :Base clock for UART3
Pawel Zarembski 0:01f31e923fe2 750 * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
Pawel Zarembski 0:01f31e923fe2 751 * @return Setting status, could be:
Pawel Zarembski 0:01f31e923fe2 752 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 753 * - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together
Pawel Zarembski 0:01f31e923fe2 754 * - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error
Pawel Zarembski 0:01f31e923fe2 755 * - CGU_ERROR_INVALID_ENTITY: Invalid entity error
Pawel Zarembski 0:01f31e923fe2 756 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 757 /* Connect one entity into clock source */
Pawel Zarembski 0:01f31e923fe2 758 uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity)
Pawel Zarembski 0:01f31e923fe2 759 {
Pawel Zarembski 0:01f31e923fe2 760 int32_t RegOffset;
Pawel Zarembski 0:01f31e923fe2 761 uint32_t tempReg;
Pawel Zarembski 0:01f31e923fe2 762
Pawel Zarembski 0:01f31e923fe2 763 if (ClockSource > CGU_CLKSRC_IDIVE) {
Pawel Zarembski 0:01f31e923fe2 764 return CGU_ERROR_INVALID_CLOCK_SOURCE;
Pawel Zarembski 0:01f31e923fe2 765 }
Pawel Zarembski 0:01f31e923fe2 766
Pawel Zarembski 0:01f31e923fe2 767 if (ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT) {
Pawel Zarembski 0:01f31e923fe2 768 if (CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]) {
Pawel Zarembski 0:01f31e923fe2 769 RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];
Pawel Zarembski 0:01f31e923fe2 770
Pawel Zarembski 0:01f31e923fe2 771 if (RegOffset != -1) {
Pawel Zarembski 0:01f31e923fe2 772 if (ClockEntity <= CGU_CLKSRC_IDIVE &&
Pawel Zarembski 0:01f31e923fe2 773 ClockEntity >= CGU_CLKSRC_PLL0) {
Pawel Zarembski 0:01f31e923fe2 774 //RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;
Pawel Zarembski 0:01f31e923fe2 775 if (((CGU_ADDRESS32(LPC_CGU, RegOffset) >> 24) & 0xF) == ClockEntity) {
Pawel Zarembski 0:01f31e923fe2 776 return CGU_ERROR_CONNECT_TOGETHER;
Pawel Zarembski 0:01f31e923fe2 777 }
Pawel Zarembski 0:01f31e923fe2 778 }
Pawel Zarembski 0:01f31e923fe2 779 }
Pawel Zarembski 0:01f31e923fe2 780
Pawel Zarembski 0:01f31e923fe2 781 RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
Pawel Zarembski 0:01f31e923fe2 782
Pawel Zarembski 0:01f31e923fe2 783 if (RegOffset == -1) {
Pawel Zarembski 0:01f31e923fe2 784 return CGU_ERROR_INVALID_ENTITY;
Pawel Zarembski 0:01f31e923fe2 785 }
Pawel Zarembski 0:01f31e923fe2 786
Pawel Zarembski 0:01f31e923fe2 787 tempReg = CGU_ADDRESS32(LPC_CGU, RegOffset);
Pawel Zarembski 0:01f31e923fe2 788 tempReg &= ~CGU_CTRL_SRC_MASK;
Pawel Zarembski 0:01f31e923fe2 789 tempReg |= ClockSource << 24 | CGU_CTRL_AUTOBLOCK_MASK;
Pawel Zarembski 0:01f31e923fe2 790 CGU_ADDRESS32(LPC_CGU, RegOffset) = tempReg;
Pawel Zarembski 0:01f31e923fe2 791 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 792
Pawel Zarembski 0:01f31e923fe2 793 } else {
Pawel Zarembski 0:01f31e923fe2 794 return CGU_ERROR_INVALID_CLOCK_SOURCE;
Pawel Zarembski 0:01f31e923fe2 795 }
Pawel Zarembski 0:01f31e923fe2 796
Pawel Zarembski 0:01f31e923fe2 797 } else {
Pawel Zarembski 0:01f31e923fe2 798 return CGU_ERROR_INVALID_ENTITY;
Pawel Zarembski 0:01f31e923fe2 799 }
Pawel Zarembski 0:01f31e923fe2 800 }
Pawel Zarembski 0:01f31e923fe2 801
Pawel Zarembski 0:01f31e923fe2 802
Pawel Zarembski 0:01f31e923fe2 803 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 804 * @brief Get current USB PLL clock from XTAL
Pawel Zarembski 0:01f31e923fe2 805 * @param[in] None
Pawel Zarembski 0:01f31e923fe2 806 * @return Returned clock value
Pawel Zarembski 0:01f31e923fe2 807 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 808 uint32_t CGU_SetPLL0(void)
Pawel Zarembski 0:01f31e923fe2 809 {
Pawel Zarembski 0:01f31e923fe2 810 // Setup PLL550 to generate 480MHz from 12 MHz crystal
Pawel Zarembski 0:01f31e923fe2 811 LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL
Pawel Zarembski 0:01f31e923fe2 812 // P N
Pawel Zarembski 0:01f31e923fe2 813 LPC_CGU->PLL0USB_NP_DIV = (98 << 0) | (514 << 12);
Pawel Zarembski 0:01f31e923fe2 814 // SELP SELI SELR MDEC
Pawel Zarembski 0:01f31e923fe2 815 LPC_CGU->PLL0USB_MDIV = (0xB << 17) | (0x10 << 22) | (0 << 28) | (0x7FFA << 0);
Pawel Zarembski 0:01f31e923fe2 816 LPC_CGU->PLL0USB_CTRL = (CGU_CLKSRC_XTAL_OSC << 24) | (0x3 << 2) | (1 << 4);
Pawel Zarembski 0:01f31e923fe2 817 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 818 }
Pawel Zarembski 0:01f31e923fe2 819
Pawel Zarembski 0:01f31e923fe2 820
Pawel Zarembski 0:01f31e923fe2 821
Pawel Zarembski 0:01f31e923fe2 822 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 823 * @brief Get current Audio PLL clock from XTAL
Pawel Zarembski 0:01f31e923fe2 824 * @param[in] None
Pawel Zarembski 0:01f31e923fe2 825 * @return Returned clock value
Pawel Zarembski 0:01f31e923fe2 826 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 827 uint32_t CGU_SetPLL0audio(void)
Pawel Zarembski 0:01f31e923fe2 828 {
Pawel Zarembski 0:01f31e923fe2 829 /* disable clock, disable skew enable, power down pll,
Pawel Zarembski 0:01f31e923fe2 830 * (dis/en)able post divider, (dis/en)able pre-divider,
Pawel Zarembski 0:01f31e923fe2 831 * disable free running mode, disable bandsel,
Pawel Zarembski 0:01f31e923fe2 832 * enable up limmiter, disable bypass
Pawel Zarembski 0:01f31e923fe2 833 */
Pawel Zarembski 0:01f31e923fe2 834 LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
Pawel Zarembski 0:01f31e923fe2 835 | _BIT(0); /* power down */
Pawel Zarembski 0:01f31e923fe2 836 /* PLL should be set to 512fs rate 512 * 48000 = 24576000 Hz */
Pawel Zarembski 0:01f31e923fe2 837 /* set mdec register */
Pawel Zarembski 0:01f31e923fe2 838 #if 1 // results from gcc program
Pawel Zarembski 0:01f31e923fe2 839 LPC_CGU->PLL0AUDIO_MDIV = 0x23e34d3;
Pawel Zarembski 0:01f31e923fe2 840 LPC_CGU->PLL0AUDIO_NP_DIV = 0x3f00e;
Pawel Zarembski 0:01f31e923fe2 841 LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
Pawel Zarembski 0:01f31e923fe2 842 | (6 << 12) // fractional divider off and bypassed
Pawel Zarembski 0:01f31e923fe2 843 | _BIT(4); /* CLKEN */
Pawel Zarembski 0:01f31e923fe2 844 #else
Pawel Zarembski 0:01f31e923fe2 845 LPC_CGU->PLL0AUDIO_MDIV = (0 << 28) /* SELR */
Pawel Zarembski 0:01f31e923fe2 846 | (40 << 22) /* SELI */
Pawel Zarembski 0:01f31e923fe2 847 | (31 << 17) /* SELP */
Pawel Zarembski 0:01f31e923fe2 848 | 11372; /* MDEC */
Pawel Zarembski 0:01f31e923fe2 849 /* set ndec, pdec register */
Pawel Zarembski 0:01f31e923fe2 850 LPC_CGU->PLL0AUDIO_NP_DIV = (22 << 12) /* ndec */
Pawel Zarembski 0:01f31e923fe2 851 | (10); /* pdec */
Pawel Zarembski 0:01f31e923fe2 852 /* set fraction divider register. [21:15] = m, [14:0] = fractional value */
Pawel Zarembski 0:01f31e923fe2 853 LPC_CGU->PLL0AUDIO_FRAC = (86 << 15) | 0x1B7;
Pawel Zarembski 0:01f31e923fe2 854 LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
Pawel Zarembski 0:01f31e923fe2 855 | _BIT(12) /* enable SD modulator to update mdec*/
Pawel Zarembski 0:01f31e923fe2 856 | _BIT(4); /* CLKEN */
Pawel Zarembski 0:01f31e923fe2 857 #endif
Pawel Zarembski 0:01f31e923fe2 858
Pawel Zarembski 0:01f31e923fe2 859 /* wait for lock */
Pawel Zarembski 0:01f31e923fe2 860 while (!(LPC_CGU->PLL0AUDIO_STAT & 1));
Pawel Zarembski 0:01f31e923fe2 861
Pawel Zarembski 0:01f31e923fe2 862 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 863 }
Pawel Zarembski 0:01f31e923fe2 864
Pawel Zarembski 0:01f31e923fe2 865
Pawel Zarembski 0:01f31e923fe2 866 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 867 * @brief Setting PLL1
Pawel Zarembski 0:01f31e923fe2 868 * @param[in] mult Multiple value
Pawel Zarembski 0:01f31e923fe2 869 * @return Setting status, could be:
Pawel Zarembski 0:01f31e923fe2 870 * - CGU_ERROR_SUCCESS: successful
Pawel Zarembski 0:01f31e923fe2 871 * - CGU_ERROR_INVALID_PARAM: Invalid parameter error
Pawel Zarembski 0:01f31e923fe2 872 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 873 uint32_t CGU_SetPLL1(uint32_t mult)
Pawel Zarembski 0:01f31e923fe2 874 {
Pawel Zarembski 0:01f31e923fe2 875 uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
Pawel Zarembski 0:01f31e923fe2 876 uint32_t freq;
Pawel Zarembski 0:01f31e923fe2 877 uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK) >> 24;
Pawel Zarembski 0:01f31e923fe2 878 freq = CGU_ClockSourceFrequency[ClkSrc];
Pawel Zarembski 0:01f31e923fe2 879 freq *= mult;
Pawel Zarembski 0:01f31e923fe2 880 msel = mult - 1;
Pawel Zarembski 0:01f31e923fe2 881 LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |
Pawel Zarembski 0:01f31e923fe2 882 CGU_PLL1_BYPASS_MASK |
Pawel Zarembski 0:01f31e923fe2 883 CGU_PLL1_DIRECT_MASK |
Pawel Zarembski 0:01f31e923fe2 884 (0x03 << 8) | (0xFF << 16) | (0x03 << 12));
Pawel Zarembski 0:01f31e923fe2 885
Pawel Zarembski 0:01f31e923fe2 886 if (freq < 156000000) {
Pawel Zarembski 0:01f31e923fe2 887 //psel is encoded such that 0=1, 1=2, 2=4, 3=8
Pawel Zarembski 0:01f31e923fe2 888 while (2 * (pval)*freq < 156000000) {
Pawel Zarembski 0:01f31e923fe2 889 psel++;
Pawel Zarembski 0:01f31e923fe2 890 pval *= 2;
Pawel Zarembski 0:01f31e923fe2 891 }
Pawel Zarembski 0:01f31e923fe2 892
Pawel Zarembski 0:01f31e923fe2 893 // if(2*(pval)*freq > 320000000) {
Pawel Zarembski 0:01f31e923fe2 894 // //THIS IS OUT OF RANGE!!!
Pawel Zarembski 0:01f31e923fe2 895 // //HOW DO WE ASSERT IN SAMPLE CODE?
Pawel Zarembski 0:01f31e923fe2 896 // //__breakpoint(0);
Pawel Zarembski 0:01f31e923fe2 897 // return CGU_ERROR_INVALID_PARAM;
Pawel Zarembski 0:01f31e923fe2 898 // }
Pawel Zarembski 0:01f31e923fe2 899 LPC_CGU->PLL1_CTRL |= (msel << 16) | (nsel << 12) | (psel << 8) | CGU_PLL1_FBSEL_MASK;
Pawel Zarembski 0:01f31e923fe2 900
Pawel Zarembski 0:01f31e923fe2 901 } else if (freq < 320000000) {
Pawel Zarembski 0:01f31e923fe2 902 LPC_CGU->PLL1_CTRL |= (msel << 16) | (nsel << 12) | (psel << 8) | CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;
Pawel Zarembski 0:01f31e923fe2 903
Pawel Zarembski 0:01f31e923fe2 904 } else {
Pawel Zarembski 0:01f31e923fe2 905 return CGU_ERROR_INVALID_PARAM;
Pawel Zarembski 0:01f31e923fe2 906 }
Pawel Zarembski 0:01f31e923fe2 907
Pawel Zarembski 0:01f31e923fe2 908 return CGU_ERROR_SUCCESS;
Pawel Zarembski 0:01f31e923fe2 909 }
Pawel Zarembski 0:01f31e923fe2 910
Pawel Zarembski 0:01f31e923fe2 911
Pawel Zarembski 0:01f31e923fe2 912 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 913 * @brief Get current base status
Pawel Zarembski 0:01f31e923fe2 914 * @param[in] Base Base type, should be:
Pawel Zarembski 0:01f31e923fe2 915 * - CGU_BASE_USB0 :Base clock for USB0
Pawel Zarembski 0:01f31e923fe2 916 * - CGU_BASE_USB1 :Base clock for USB1
Pawel Zarembski 0:01f31e923fe2 917 * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
Pawel Zarembski 0:01f31e923fe2 918 * and APB peripheral blocks #0 and #2
Pawel Zarembski 0:01f31e923fe2 919 * - CGU_BASE_SPIFI :Base clock for SPIFI
Pawel Zarembski 0:01f31e923fe2 920 * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
Pawel Zarembski 0:01f31e923fe2 921 * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
Pawel Zarembski 0:01f31e923fe2 922 * - CGU_BASE_SDIO :Base clock for SDIO card reader
Pawel Zarembski 0:01f31e923fe2 923 * - CGU_BASE_SSP0 :Base clock for SSP0
Pawel Zarembski 0:01f31e923fe2 924 * - CGU_BASE_SSP1 :Base clock for SSP1
Pawel Zarembski 0:01f31e923fe2 925 * - CGU_BASE_UART0 :Base clock for UART0
Pawel Zarembski 0:01f31e923fe2 926 * - CGU_BASE_UART1 :Base clock for UART1
Pawel Zarembski 0:01f31e923fe2 927 * - CGU_BASE_UART2 :Base clock for UART2
Pawel Zarembski 0:01f31e923fe2 928 * - CGU_BASE_UART3 :Base clock for UART3
Pawel Zarembski 0:01f31e923fe2 929 * @return Always return 0
Pawel Zarembski 0:01f31e923fe2 930 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 931 uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base)
Pawel Zarembski 0:01f31e923fe2 932 {
Pawel Zarembski 0:01f31e923fe2 933 switch (Base) {
Pawel Zarembski 0:01f31e923fe2 934 /*CCU1*/
Pawel Zarembski 0:01f31e923fe2 935 case CGU_BASE_APB3:
Pawel Zarembski 0:01f31e923fe2 936 return LPC_CCU1->BASE_STAT & 1;
Pawel Zarembski 0:01f31e923fe2 937
Pawel Zarembski 0:01f31e923fe2 938 case CGU_BASE_APB1:
Pawel Zarembski 0:01f31e923fe2 939 return (LPC_CCU1->BASE_STAT >> 1) & 1;
Pawel Zarembski 0:01f31e923fe2 940
Pawel Zarembski 0:01f31e923fe2 941 case CGU_BASE_SPIFI:
Pawel Zarembski 0:01f31e923fe2 942 return (LPC_CCU1->BASE_STAT >> 2) & 1;
Pawel Zarembski 0:01f31e923fe2 943
Pawel Zarembski 0:01f31e923fe2 944 case CGU_BASE_M4:
Pawel Zarembski 0:01f31e923fe2 945 return (LPC_CCU1->BASE_STAT >> 3) & 1;
Pawel Zarembski 0:01f31e923fe2 946
Pawel Zarembski 0:01f31e923fe2 947 case CGU_BASE_USB0:
Pawel Zarembski 0:01f31e923fe2 948 return (LPC_CCU1->BASE_STAT >> 7) & 1;
Pawel Zarembski 0:01f31e923fe2 949
Pawel Zarembski 0:01f31e923fe2 950 case CGU_BASE_USB1:
Pawel Zarembski 0:01f31e923fe2 951 return (LPC_CCU1->BASE_STAT >> 8) & 1;
Pawel Zarembski 0:01f31e923fe2 952
Pawel Zarembski 0:01f31e923fe2 953 /*CCU2*/
Pawel Zarembski 0:01f31e923fe2 954 case CGU_BASE_UART3:
Pawel Zarembski 0:01f31e923fe2 955 return (LPC_CCU2->BASE_STAT >> 1) & 1;
Pawel Zarembski 0:01f31e923fe2 956
Pawel Zarembski 0:01f31e923fe2 957 case CGU_BASE_UART2:
Pawel Zarembski 0:01f31e923fe2 958 return (LPC_CCU2->BASE_STAT >> 2) & 1;
Pawel Zarembski 0:01f31e923fe2 959
Pawel Zarembski 0:01f31e923fe2 960 case CGU_BASE_UART1:
Pawel Zarembski 0:01f31e923fe2 961 return (LPC_CCU2->BASE_STAT >> 3) & 1;
Pawel Zarembski 0:01f31e923fe2 962
Pawel Zarembski 0:01f31e923fe2 963 case CGU_BASE_UART0:
Pawel Zarembski 0:01f31e923fe2 964 return (LPC_CCU2->BASE_STAT >> 4) & 1;
Pawel Zarembski 0:01f31e923fe2 965
Pawel Zarembski 0:01f31e923fe2 966 case CGU_BASE_SSP1:
Pawel Zarembski 0:01f31e923fe2 967 return (LPC_CCU2->BASE_STAT >> 5) & 1;
Pawel Zarembski 0:01f31e923fe2 968
Pawel Zarembski 0:01f31e923fe2 969 case CGU_BASE_SSP0:
Pawel Zarembski 0:01f31e923fe2 970 return (LPC_CCU2->BASE_STAT >> 6) & 1;
Pawel Zarembski 0:01f31e923fe2 971
Pawel Zarembski 0:01f31e923fe2 972 case CGU_BASE_SDIO:
Pawel Zarembski 0:01f31e923fe2 973 return (LPC_CCU2->BASE_STAT >> 7) & 1;
Pawel Zarembski 0:01f31e923fe2 974
Pawel Zarembski 0:01f31e923fe2 975 /*BASE SAFE is used by WWDT and RGU*/
Pawel Zarembski 0:01f31e923fe2 976 case CGU_BASE_SAFE:
Pawel Zarembski 0:01f31e923fe2 977 break;
Pawel Zarembski 0:01f31e923fe2 978
Pawel Zarembski 0:01f31e923fe2 979 default:
Pawel Zarembski 0:01f31e923fe2 980 break;
Pawel Zarembski 0:01f31e923fe2 981 }
Pawel Zarembski 0:01f31e923fe2 982
Pawel Zarembski 0:01f31e923fe2 983 return 0;
Pawel Zarembski 0:01f31e923fe2 984 }
Pawel Zarembski 0:01f31e923fe2 985
Pawel Zarembski 0:01f31e923fe2 986
Pawel Zarembski 0:01f31e923fe2 987 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 988 * @brief Compare one source clock to IRC clock
Pawel Zarembski 0:01f31e923fe2 989 * @param[in] Clock Clock entity that will be compared to IRC, should be:
Pawel Zarembski 0:01f31e923fe2 990 * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
Pawel Zarembski 0:01f31e923fe2 991 * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
Pawel Zarembski 0:01f31e923fe2 992 * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
Pawel Zarembski 0:01f31e923fe2 993 * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
Pawel Zarembski 0:01f31e923fe2 994 * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
Pawel Zarembski 0:01f31e923fe2 995 * - CGU_CLKSRC_PLL0 :PLL0 clock
Pawel Zarembski 0:01f31e923fe2 996 * - CGU_CLKSRC_PLL1 :PLL1 clock
Pawel Zarembski 0:01f31e923fe2 997 * - CGU_CLKSRC_IDIVA :Integer divider register A
Pawel Zarembski 0:01f31e923fe2 998 * - CGU_CLKSRC_IDIVB :Integer divider register B
Pawel Zarembski 0:01f31e923fe2 999 * - CGU_CLKSRC_IDIVC :Integer divider register C
Pawel Zarembski 0:01f31e923fe2 1000 * - CGU_CLKSRC_IDIVD :Integer divider register D
Pawel Zarembski 0:01f31e923fe2 1001 * - CGU_CLKSRC_IDIVE :Integer divider register E
Pawel Zarembski 0:01f31e923fe2 1002 * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
Pawel Zarembski 0:01f31e923fe2 1003 * - CGU_BASE_USB0 :Base clock for USB0
Pawel Zarembski 0:01f31e923fe2 1004 * - CGU_BASE_USB1 :Base clock for USB1
Pawel Zarembski 0:01f31e923fe2 1005 * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
Pawel Zarembski 0:01f31e923fe2 1006 * and APB peripheral blocks #0 and #2
Pawel Zarembski 0:01f31e923fe2 1007 * - CGU_BASE_SPIFI :Base clock for SPIFI
Pawel Zarembski 0:01f31e923fe2 1008 * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
Pawel Zarembski 0:01f31e923fe2 1009 * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
Pawel Zarembski 0:01f31e923fe2 1010 * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
Pawel Zarembski 0:01f31e923fe2 1011 * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
Pawel Zarembski 0:01f31e923fe2 1012 * - CGU_BASE_LCD :Base clock for LCD
Pawel Zarembski 0:01f31e923fe2 1013 * - CGU_BASE_SDIO :Base clock for SDIO card reader
Pawel Zarembski 0:01f31e923fe2 1014 * - CGU_BASE_SSP0 :Base clock for SSP0
Pawel Zarembski 0:01f31e923fe2 1015 * - CGU_BASE_SSP1 :Base clock for SSP1
Pawel Zarembski 0:01f31e923fe2 1016 * - CGU_BASE_UART0 :Base clock for UART0
Pawel Zarembski 0:01f31e923fe2 1017 * - CGU_BASE_UART1 :Base clock for UART1
Pawel Zarembski 0:01f31e923fe2 1018 * - CGU_BASE_UART2 :Base clock for UART2
Pawel Zarembski 0:01f31e923fe2 1019 * - CGU_BASE_UART3 :Base clock for UART3
Pawel Zarembski 0:01f31e923fe2 1020 * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
Pawel Zarembski 0:01f31e923fe2 1021 * @param[in] m Multiple value pointer
Pawel Zarembski 0:01f31e923fe2 1022 * @param[in] d Divider value pointer
Pawel Zarembski 0:01f31e923fe2 1023 * @return Compare status, could be:
Pawel Zarembski 0:01f31e923fe2 1024 * - (-1): fail
Pawel Zarembski 0:01f31e923fe2 1025 * - 0: successful
Pawel Zarembski 0:01f31e923fe2 1026 * @note Formula used to compare:
Pawel Zarembski 0:01f31e923fe2 1027 * FClock = F_IRC* m / d
Pawel Zarembski 0:01f31e923fe2 1028 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 1029 int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d)
Pawel Zarembski 0:01f31e923fe2 1030 {
Pawel Zarembski 0:01f31e923fe2 1031 uint32_t n, c, temp;
Pawel Zarembski 0:01f31e923fe2 1032 int i;
Pawel Zarembski 0:01f31e923fe2 1033 /* Maximum allow RCOUNT number */
Pawel Zarembski 0:01f31e923fe2 1034 c = 511;
Pawel Zarembski 0:01f31e923fe2 1035 /* Check Source Clock Freq is larger or smaller */
Pawel Zarembski 0:01f31e923fe2 1036 LPC_CGU->FREQ_MON = (Clock << 24) | 1 << 23 | c;
Pawel Zarembski 0:01f31e923fe2 1037
Pawel Zarembski 0:01f31e923fe2 1038 while (LPC_CGU->FREQ_MON & (1 << 23));
Pawel Zarembski 0:01f31e923fe2 1039
Pawel Zarembski 0:01f31e923fe2 1040 for (i = 0; i < 10000; i++);
Pawel Zarembski 0:01f31e923fe2 1041
Pawel Zarembski 0:01f31e923fe2 1042 temp = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
Pawel Zarembski 0:01f31e923fe2 1043
Pawel Zarembski 0:01f31e923fe2 1044 if (temp == 0) { /* too low F < 12000000/511*/
Pawel Zarembski 0:01f31e923fe2 1045 return -1;
Pawel Zarembski 0:01f31e923fe2 1046 }
Pawel Zarembski 0:01f31e923fe2 1047
Pawel Zarembski 0:01f31e923fe2 1048 if (temp > 511) { /* larger */
Pawel Zarembski 0:01f31e923fe2 1049 c = 511 - (LPC_CGU->FREQ_MON & 0x1FF);
Pawel Zarembski 0:01f31e923fe2 1050
Pawel Zarembski 0:01f31e923fe2 1051 } else {
Pawel Zarembski 0:01f31e923fe2 1052 do {
Pawel Zarembski 0:01f31e923fe2 1053 c--;
Pawel Zarembski 0:01f31e923fe2 1054 LPC_CGU->FREQ_MON = (Clock << 24) | 1 << 23 | c;
Pawel Zarembski 0:01f31e923fe2 1055
Pawel Zarembski 0:01f31e923fe2 1056 while (LPC_CGU->FREQ_MON & (1 << 23));
Pawel Zarembski 0:01f31e923fe2 1057
Pawel Zarembski 0:01f31e923fe2 1058 for (i = 0; i < 10000; i++);
Pawel Zarembski 0:01f31e923fe2 1059
Pawel Zarembski 0:01f31e923fe2 1060 n = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
Pawel Zarembski 0:01f31e923fe2 1061 } while (n == temp);
Pawel Zarembski 0:01f31e923fe2 1062
Pawel Zarembski 0:01f31e923fe2 1063 c++;
Pawel Zarembski 0:01f31e923fe2 1064 }
Pawel Zarembski 0:01f31e923fe2 1065
Pawel Zarembski 0:01f31e923fe2 1066 *m = temp;
Pawel Zarembski 0:01f31e923fe2 1067 *d = c;
Pawel Zarembski 0:01f31e923fe2 1068 return 0;
Pawel Zarembski 0:01f31e923fe2 1069 }
Pawel Zarembski 0:01f31e923fe2 1070
Pawel Zarembski 0:01f31e923fe2 1071 /*********************************************************************//**
Pawel Zarembski 0:01f31e923fe2 1072 * @brief Compare one source clock to another source clock
Pawel Zarembski 0:01f31e923fe2 1073 * @param[in] Clock Clock entity that will be compared to second source, should be:
Pawel Zarembski 0:01f31e923fe2 1074 * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
Pawel Zarembski 0:01f31e923fe2 1075 * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
Pawel Zarembski 0:01f31e923fe2 1076 * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
Pawel Zarembski 0:01f31e923fe2 1077 * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
Pawel Zarembski 0:01f31e923fe2 1078 * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
Pawel Zarembski 0:01f31e923fe2 1079 * - CGU_CLKSRC_PLL0 :PLL0 clock
Pawel Zarembski 0:01f31e923fe2 1080 * - CGU_CLKSRC_PLL1 :PLL1 clock
Pawel Zarembski 0:01f31e923fe2 1081 * - CGU_CLKSRC_IDIVA :Integer divider register A
Pawel Zarembski 0:01f31e923fe2 1082 * - CGU_CLKSRC_IDIVB :Integer divider register B
Pawel Zarembski 0:01f31e923fe2 1083 * - CGU_CLKSRC_IDIVC :Integer divider register C
Pawel Zarembski 0:01f31e923fe2 1084 * - CGU_CLKSRC_IDIVD :Integer divider register D
Pawel Zarembski 0:01f31e923fe2 1085 * - CGU_CLKSRC_IDIVE :Integer divider register E
Pawel Zarembski 0:01f31e923fe2 1086 * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
Pawel Zarembski 0:01f31e923fe2 1087 * - CGU_BASE_USB0 :Base clock for USB0
Pawel Zarembski 0:01f31e923fe2 1088 * - CGU_BASE_USB1 :Base clock for USB1
Pawel Zarembski 0:01f31e923fe2 1089 * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
Pawel Zarembski 0:01f31e923fe2 1090 * and APB peripheral blocks #0 and #2
Pawel Zarembski 0:01f31e923fe2 1091 * - CGU_BASE_SPIFI :Base clock for SPIFI
Pawel Zarembski 0:01f31e923fe2 1092 * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
Pawel Zarembski 0:01f31e923fe2 1093 * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
Pawel Zarembski 0:01f31e923fe2 1094 * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
Pawel Zarembski 0:01f31e923fe2 1095 * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
Pawel Zarembski 0:01f31e923fe2 1096 * - CGU_BASE_LCD :Base clock for LCD
Pawel Zarembski 0:01f31e923fe2 1097 * - CGU_BASE_SDIO :Base clock for SDIO card reader
Pawel Zarembski 0:01f31e923fe2 1098 * - CGU_BASE_SSP0 :Base clock for SSP0
Pawel Zarembski 0:01f31e923fe2 1099 * - CGU_BASE_SSP1 :Base clock for SSP1
Pawel Zarembski 0:01f31e923fe2 1100 * - CGU_BASE_UART0 :Base clock for UART0
Pawel Zarembski 0:01f31e923fe2 1101 * - CGU_BASE_UART1 :Base clock for UART1
Pawel Zarembski 0:01f31e923fe2 1102 * - CGU_BASE_UART2 :Base clock for UART2
Pawel Zarembski 0:01f31e923fe2 1103 * - CGU_BASE_UART3 :Base clock for UART3
Pawel Zarembski 0:01f31e923fe2 1104 * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
Pawel Zarembski 0:01f31e923fe2 1105 * @param[in] CompareToClock Clock source that to be compared to first source, should be different
Pawel Zarembski 0:01f31e923fe2 1106 * to first source.
Pawel Zarembski 0:01f31e923fe2 1107 * @param[in] m Multiple value pointer
Pawel Zarembski 0:01f31e923fe2 1108 * @param[in] d Divider value pointer
Pawel Zarembski 0:01f31e923fe2 1109 * @return Compare status, could be:
Pawel Zarembski 0:01f31e923fe2 1110 * - (-1): fail
Pawel Zarembski 0:01f31e923fe2 1111 * - 0: successful
Pawel Zarembski 0:01f31e923fe2 1112 * @note Formula used to compare:
Pawel Zarembski 0:01f31e923fe2 1113 * FClock = m*FCompareToClock/d
Pawel Zarembski 0:01f31e923fe2 1114 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 1115 uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d)
Pawel Zarembski 0:01f31e923fe2 1116 {
Pawel Zarembski 0:01f31e923fe2 1117 uint32_t m1, m2, d1, d2;
Pawel Zarembski 0:01f31e923fe2 1118
Pawel Zarembski 0:01f31e923fe2 1119 /* Check Parameter */
Pawel Zarembski 0:01f31e923fe2 1120 if ((Clock > CGU_CLKSRC_IDIVE) || (CompareToClock > CGU_CLKSRC_IDIVE)) {
Pawel Zarembski 0:01f31e923fe2 1121 return CGU_ERROR_INVALID_PARAM;
Pawel Zarembski 0:01f31e923fe2 1122 }
Pawel Zarembski 0:01f31e923fe2 1123
Pawel Zarembski 0:01f31e923fe2 1124 /* Check for Clock Enable - Not yet implement
Pawel Zarembski 0:01f31e923fe2 1125 * The Comparator will hang if Clock has not been set*/
Pawel Zarembski 0:01f31e923fe2 1126 CGU_FrequencyMonitor(Clock, &m1, &d1);
Pawel Zarembski 0:01f31e923fe2 1127 CGU_FrequencyMonitor(CompareToClock, &m2, &d2);
Pawel Zarembski 0:01f31e923fe2 1128 *m = m1 * d2;
Pawel Zarembski 0:01f31e923fe2 1129 *d = d1 * m2;
Pawel Zarembski 0:01f31e923fe2 1130 return 0;
Pawel Zarembski 0:01f31e923fe2 1131 }
Pawel Zarembski 0:01f31e923fe2 1132