Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nxp/lpc4322/fpu_enable.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /***********************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * $Id: fpu_enable.c
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Project: LPC43xx
Pawel Zarembski 0:01f31e923fe2 5 *
Pawel Zarembski 0:01f31e923fe2 6 * Description: fpu initialization routine
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * Copyright(C) 2011, NXP Semiconductor
Pawel Zarembski 0:01f31e923fe2 9 * All rights reserved.
Pawel Zarembski 0:01f31e923fe2 10 *
Pawel Zarembski 0:01f31e923fe2 11 ***********************************************************************
Pawel Zarembski 0:01f31e923fe2 12 * Software that is described herein is for illustrative purposes only
Pawel Zarembski 0:01f31e923fe2 13 * which provides customers with programming information regarding the
Pawel Zarembski 0:01f31e923fe2 14 * products. This software is supplied "AS IS" without any warranties.
Pawel Zarembski 0:01f31e923fe2 15 * NXP Semiconductors assumes no responsibility or liability for the
Pawel Zarembski 0:01f31e923fe2 16 * use of the software, conveys no license or title under any patent,
Pawel Zarembski 0:01f31e923fe2 17 * copyright, or mask work right to the product. NXP Semiconductors
Pawel Zarembski 0:01f31e923fe2 18 * reserves the right to make changes in the software without
Pawel Zarembski 0:01f31e923fe2 19 * notification. NXP Semiconductors also make no representation or
Pawel Zarembski 0:01f31e923fe2 20 * warranty that such application will be suitable for the specified
Pawel Zarembski 0:01f31e923fe2 21 * use without further testing or modification.
Pawel Zarembski 0:01f31e923fe2 22 **********************************************************************/
Pawel Zarembski 0:01f31e923fe2 23
Pawel Zarembski 0:01f31e923fe2 24 #define LPC_CPACR 0xE000ED88
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 #define SCB_MVFR0 0xE000EF40
Pawel Zarembski 0:01f31e923fe2 27 #define SCB_MVFR0_RESET 0x10110021
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 #define SCB_MVFR1 0xE000EF44
Pawel Zarembski 0:01f31e923fe2 30 #define SCB_MVFR1_RESET 0x11000011
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 #include "stdint.h"
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 void fpuEnable(void)
Pawel Zarembski 0:01f31e923fe2 35 {
Pawel Zarembski 0:01f31e923fe2 36 /* from arm trm manual, howto enable the FPU :
Pawel Zarembski 0:01f31e923fe2 37 ; CPACR is located at address 0xE000ED88
Pawel Zarembski 0:01f31e923fe2 38 LDR.W R0, =0xE000ED88
Pawel Zarembski 0:01f31e923fe2 39 ; Read CPACR
Pawel Zarembski 0:01f31e923fe2 40 LDR R1, [R0]
Pawel Zarembski 0:01f31e923fe2 41 ; Set bits 20-23 to enable CP10 and CP11 coprocessors
Pawel Zarembski 0:01f31e923fe2 42 ORR R1, R1, #(0xF << 20)
Pawel Zarembski 0:01f31e923fe2 43 ; Write back the modified value to the CPACR
Pawel Zarembski 0:01f31e923fe2 44 STR R1, [R0]
Pawel Zarembski 0:01f31e923fe2 45 */
Pawel Zarembski 0:01f31e923fe2 46 volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
Pawel Zarembski 0:01f31e923fe2 47 volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
Pawel Zarembski 0:01f31e923fe2 48 volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
Pawel Zarembski 0:01f31e923fe2 49 volatile uint32_t Cpacr;
Pawel Zarembski 0:01f31e923fe2 50 volatile uint32_t Mvfr0;
Pawel Zarembski 0:01f31e923fe2 51 volatile uint32_t Mvfr1;
Pawel Zarembski 0:01f31e923fe2 52 char vfpPresent = 0;
Pawel Zarembski 0:01f31e923fe2 53 Mvfr0 = *regMvfr0;
Pawel Zarembski 0:01f31e923fe2 54 Mvfr1 = *regMvfr1;
Pawel Zarembski 0:01f31e923fe2 55 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
Pawel Zarembski 0:01f31e923fe2 56
Pawel Zarembski 0:01f31e923fe2 57 /* enable the FPU if present on target */
Pawel Zarembski 0:01f31e923fe2 58 if (vfpPresent) {
Pawel Zarembski 0:01f31e923fe2 59 Cpacr = *regCpacr;
Pawel Zarembski 0:01f31e923fe2 60 Cpacr |= (0xF << 20);
Pawel Zarembski 0:01f31e923fe2 61 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
Pawel Zarembski 0:01f31e923fe2 62 }
Pawel Zarembski 0:01f31e923fe2 63 }
Pawel Zarembski 0:01f31e923fe2 64
Pawel Zarembski 0:01f31e923fe2 65