Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /****************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * @file system_LPC11Uxx.c |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * for the NXP LPC13xx Device Series |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * @version V1.10 |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * @date 24. November 2010 |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * @note |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Copyright (C) 2009-2010 ARM Limited. All rights reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * @par |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * processor based microcontrollers. This file can be freely distributed |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * within development tools that are supporting such ARM based processors. |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * @par |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | ******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | #include "stdint.h" |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | #include "LPC11Uxx.h" |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | /*--------------------- Clock Configuration ---------------------------------- |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | // |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | // <e> Clock Configuration |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | // <h> System Oscillator Control Register (SYSOSCCTRL) |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | // <o1.0> BYPASS: System Oscillator Bypass Enable |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | // <i> If enabled then PLL input (sys_osc_clk) is fed |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | // <i> directly from XTALIN and XTALOUT pins. |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | // <o1.9> FREQRANGE: System Oscillator Frequency Range |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | // <i> Determines frequency range for Low-power oscillator. |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | // <0=> 1 - 20 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | // <1=> 15 - 25 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | // </h> |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | // |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | // <h> Watchdog Oscillator Control Register (WDTOSCCTRL) |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | // <o2.0..4> DIVSEL: Select Divider for Fclkana |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | // <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL)) |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | // <0-31> |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | // <0=> Undefined |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | // <1=> 0.5 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | // <2=> 0.8 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | // <3=> 1.1 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | // <4=> 1.4 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | // <5=> 1.6 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | // <6=> 1.8 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | // <7=> 2.0 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | // <8=> 2.2 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | // <9=> 2.4 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | // <10=> 2.6 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | // <11=> 2.7 MHz |
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0:01f31e923fe2 | 63 | // <12=> 2.9 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | // <13=> 3.1 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | // <14=> 3.2 MHz |
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0:01f31e923fe2 | 66 | // <15=> 3.4 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | // </h> |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | // |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | // <h> System PLL Control Register (SYSPLLCTRL) |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | // <o3.0..4> MSEL: Feedback Divider Selection |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | // <i> M = MSEL + 1 |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | // <0-31> |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | // <o3.5..6> PSEL: Post Divider Selection |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | // <0=> P = 1 |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | // <1=> P = 2 |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | // <2=> P = 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | // <3=> P = 8 |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | // </h> |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | // |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL) |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | // <o4.0..1> SEL: System PLL Clock Source |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | // <0=> IRC Oscillator |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | // <1=> System Oscillator |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | // <2=> Reserved |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | // <3=> Reserved |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | // </h> |
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0:01f31e923fe2 | 90 | // |
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0:01f31e923fe2 | 91 | // <h> Main Clock Source Select Register (MAINCLKSEL) |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | // <o5.0..1> SEL: Clock Source for Main Clock |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | // <0=> IRC Oscillator |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | // <1=> Input Clock to System PLL |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | // <2=> WDT Oscillator |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | // <3=> System PLL Clock Out |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | // </h> |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | // |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | // <h> System AHB Clock Divider Register (SYSAHBCLKDIV) |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | // <o6.0..7> DIV: System AHB Clock Divider |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | // <i> Divides main clock to provide system clock to core, memories, and peripherals. |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | // <i> 0 = is disabled |
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0:01f31e923fe2 | 103 | // <0-255> |
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0:01f31e923fe2 | 104 | // </h> |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | // |
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0:01f31e923fe2 | 106 | // <h> USB PLL Control Register (USBPLLCTRL) |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | // <o7.0..4> MSEL: Feedback Divider Selection |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | // <i> M = MSEL + 1 |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | // <0-31> |
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0:01f31e923fe2 | 113 | // <o7.5..6> PSEL: Post Divider Selection |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | // <0=> P = 1 |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | // <1=> P = 2 |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | // <2=> P = 4 |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | // <3=> P = 8 |
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0:01f31e923fe2 | 118 | // </h> |
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0:01f31e923fe2 | 119 | // |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | // <h> USB PLL Clock Source Select Register (USBPLLCLKSEL) |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | // <o8.0..1> SEL: USB PLL Clock Source |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | // <0=> IRC Oscillator |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | // <1=> System Oscillator |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | // <2=> Reserved |
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0:01f31e923fe2 | 126 | // <3=> Reserved |
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0:01f31e923fe2 | 127 | // </h> |
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0:01f31e923fe2 | 128 | // |
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0:01f31e923fe2 | 129 | // <h> USB Clock Source Select Register (USBCLKSEL) |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | // <o9.0..1> SEL: System PLL Clock Source |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | // <0=> USB PLL out |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | // <1=> Main clock |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | // <2=> Reserved |
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0:01f31e923fe2 | 134 | // <3=> Reserved |
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0:01f31e923fe2 | 135 | // </h> |
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0:01f31e923fe2 | 136 | // |
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0:01f31e923fe2 | 137 | // <h> USB Clock Divider Register (USBCLKDIV) |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | // <o10.0..7> DIV: USB Clock Divider |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | // <i> Divides USB clock to 48 MHz. |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | // <i> 0 = is disabled |
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0:01f31e923fe2 | 141 | // <0-255> |
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0:01f31e923fe2 | 142 | // </h> |
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0:01f31e923fe2 | 143 | // </e> |
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0:01f31e923fe2 | 144 | */ |
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0:01f31e923fe2 | 145 | #define CLOCK_SETUP 1 |
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0:01f31e923fe2 | 146 | #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 |
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0:01f31e923fe2 | 147 | #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 |
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0:01f31e923fe2 | 148 | #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 |
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0:01f31e923fe2 | 149 | #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 |
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0:01f31e923fe2 | 150 | #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 |
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0:01f31e923fe2 | 151 | #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 |
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0:01f31e923fe2 | 152 | #define USBPLLCTRL_Val 0x00000023 // Reset: 0x000 |
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0:01f31e923fe2 | 153 | #define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000 |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define USBCLKSEL_Val 0x00000000 // Reset: 0x000 |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define USBCLKDIV_Val 0x00000001 // Reset: 0x001 |
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0:01f31e923fe2 | 156 | |
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0:01f31e923fe2 | 157 | /* |
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0:01f31e923fe2 | 158 | //-------- <<< end of configuration section >>> ------------------------------ |
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0:01f31e923fe2 | 159 | */ |
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0:01f31e923fe2 | 160 | |
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0:01f31e923fe2 | 161 | /*---------------------------------------------------------------------------- |
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0:01f31e923fe2 | 162 | Check the register settings |
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0:01f31e923fe2 | 163 | *----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 164 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
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0:01f31e923fe2 | 165 | #define CHECK_RSVD(val, mask) (val & mask) |
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0:01f31e923fe2 | 166 | |
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0:01f31e923fe2 | 167 | /* Clock Configuration -------------------------------------------------------*/ |
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0:01f31e923fe2 | 168 | #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) |
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0:01f31e923fe2 | 169 | #error "SYSOSCCTRL: Invalid values of reserved bits!" |
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0:01f31e923fe2 | 170 | #endif |
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0:01f31e923fe2 | 171 | |
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0:01f31e923fe2 | 172 | #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) |
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0:01f31e923fe2 | 173 | #error "WDTOSCCTRL: Invalid values of reserved bits!" |
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0:01f31e923fe2 | 174 | #endif |
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0:01f31e923fe2 | 175 | |
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0:01f31e923fe2 | 176 | #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) |
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0:01f31e923fe2 | 177 | #error "SYSPLLCLKSEL: Value out of range!" |
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0:01f31e923fe2 | 178 | #endif |
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0:01f31e923fe2 | 179 | |
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0:01f31e923fe2 | 180 | #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) |
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0:01f31e923fe2 | 181 | #error "SYSPLLCTRL: Invalid values of reserved bits!" |
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0:01f31e923fe2 | 182 | #endif |
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0:01f31e923fe2 | 183 | |
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0:01f31e923fe2 | 184 | #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) |
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0:01f31e923fe2 | 185 | #error "MAINCLKSEL: Invalid values of reserved bits!" |
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0:01f31e923fe2 | 186 | #endif |
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0:01f31e923fe2 | 187 | |
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0:01f31e923fe2 | 188 | #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) |
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0:01f31e923fe2 | 189 | #error "SYSAHBCLKDIV: Value out of range!" |
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0:01f31e923fe2 | 190 | #endif |
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0:01f31e923fe2 | 191 | |
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0:01f31e923fe2 | 192 | #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) |
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0:01f31e923fe2 | 193 | #error "USBPLLCLKSEL: Value out of range!" |
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0:01f31e923fe2 | 194 | #endif |
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0:01f31e923fe2 | 195 | |
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0:01f31e923fe2 | 196 | #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) |
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0:01f31e923fe2 | 197 | #error "USBPLLCTRL: Invalid values of reserved bits!" |
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0:01f31e923fe2 | 198 | #endif |
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0:01f31e923fe2 | 199 | |
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0:01f31e923fe2 | 200 | #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1)) |
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0:01f31e923fe2 | 201 | #error "USBCLKSEL: Value out of range!" |
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0:01f31e923fe2 | 202 | #endif |
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0:01f31e923fe2 | 203 | |
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0:01f31e923fe2 | 204 | #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255)) |
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0:01f31e923fe2 | 205 | #error "USBCLKDIV: Value out of range!" |
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0:01f31e923fe2 | 206 | #endif |
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0:01f31e923fe2 | 207 | |
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0:01f31e923fe2 | 208 | |
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0:01f31e923fe2 | 209 | /*---------------------------------------------------------------------------- |
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0:01f31e923fe2 | 210 | DEFINES |
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0:01f31e923fe2 | 211 | *----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 212 | |
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0:01f31e923fe2 | 213 | /*---------------------------------------------------------------------------- |
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0:01f31e923fe2 | 214 | Define clocks |
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0:01f31e923fe2 | 215 | *----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 216 | #define __XTAL (12000000UL) /* Oscillator frequency */ |
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0:01f31e923fe2 | 217 | #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ |
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0:01f31e923fe2 | 218 | #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ |
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0:01f31e923fe2 | 219 | |
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0:01f31e923fe2 | 220 | |
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0:01f31e923fe2 | 221 | #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) |
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0:01f31e923fe2 | 222 | #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) |
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0:01f31e923fe2 | 223 | |
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0:01f31e923fe2 | 224 | #if (CLOCK_SETUP) /* Clock Setup */ |
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0:01f31e923fe2 | 225 | #if (__FREQSEL == 0) |
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0:01f31e923fe2 | 226 | #define __WDT_OSC_CLK ( 0) /* undefined */ |
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0:01f31e923fe2 | 227 | #elif (__FREQSEL == 1) |
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0:01f31e923fe2 | 228 | #define __WDT_OSC_CLK ( 500000 / __DIVSEL) |
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0:01f31e923fe2 | 229 | #elif (__FREQSEL == 2) |
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0:01f31e923fe2 | 230 | #define __WDT_OSC_CLK ( 800000 / __DIVSEL) |
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0:01f31e923fe2 | 231 | #elif (__FREQSEL == 3) |
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0:01f31e923fe2 | 232 | #define __WDT_OSC_CLK (1100000 / __DIVSEL) |
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0:01f31e923fe2 | 233 | #elif (__FREQSEL == 4) |
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0:01f31e923fe2 | 234 | #define __WDT_OSC_CLK (1400000 / __DIVSEL) |
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0:01f31e923fe2 | 235 | #elif (__FREQSEL == 5) |
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0:01f31e923fe2 | 236 | #define __WDT_OSC_CLK (1600000 / __DIVSEL) |
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0:01f31e923fe2 | 237 | #elif (__FREQSEL == 6) |
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0:01f31e923fe2 | 238 | #define __WDT_OSC_CLK (1800000 / __DIVSEL) |
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0:01f31e923fe2 | 239 | #elif (__FREQSEL == 7) |
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0:01f31e923fe2 | 240 | #define __WDT_OSC_CLK (2000000 / __DIVSEL) |
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0:01f31e923fe2 | 241 | #elif (__FREQSEL == 8) |
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0:01f31e923fe2 | 242 | #define __WDT_OSC_CLK (2200000 / __DIVSEL) |
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0:01f31e923fe2 | 243 | #elif (__FREQSEL == 9) |
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0:01f31e923fe2 | 244 | #define __WDT_OSC_CLK (2400000 / __DIVSEL) |
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0:01f31e923fe2 | 245 | #elif (__FREQSEL == 10) |
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0:01f31e923fe2 | 246 | #define __WDT_OSC_CLK (2600000 / __DIVSEL) |
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0:01f31e923fe2 | 247 | #elif (__FREQSEL == 11) |
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0:01f31e923fe2 | 248 | #define __WDT_OSC_CLK (2700000 / __DIVSEL) |
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0:01f31e923fe2 | 249 | #elif (__FREQSEL == 12) |
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0:01f31e923fe2 | 250 | #define __WDT_OSC_CLK (2900000 / __DIVSEL) |
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0:01f31e923fe2 | 251 | #elif (__FREQSEL == 13) |
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0:01f31e923fe2 | 252 | #define __WDT_OSC_CLK (3100000 / __DIVSEL) |
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0:01f31e923fe2 | 253 | #elif (__FREQSEL == 14) |
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0:01f31e923fe2 | 254 | #define __WDT_OSC_CLK (3200000 / __DIVSEL) |
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0:01f31e923fe2 | 255 | #else |
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0:01f31e923fe2 | 256 | #define __WDT_OSC_CLK (3400000 / __DIVSEL) |
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0:01f31e923fe2 | 257 | #endif |
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0:01f31e923fe2 | 258 | |
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0:01f31e923fe2 | 259 | /* sys_pllclkin calculation */ |
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0:01f31e923fe2 | 260 | #if ((SYSPLLCLKSEL_Val & 0x03) == 0) |
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0:01f31e923fe2 | 261 | #define __SYS_PLLCLKIN (__IRC_OSC_CLK) |
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0:01f31e923fe2 | 262 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) |
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0:01f31e923fe2 | 263 | #define __SYS_PLLCLKIN (__SYS_OSC_CLK) |
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0:01f31e923fe2 | 264 | #else |
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0:01f31e923fe2 | 265 | #define __SYS_PLLCLKIN (0) |
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0:01f31e923fe2 | 266 | #endif |
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0:01f31e923fe2 | 267 | |
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0:01f31e923fe2 | 268 | #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) |
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0:01f31e923fe2 | 269 | |
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0:01f31e923fe2 | 270 | /* main clock calculation */ |
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0:01f31e923fe2 | 271 | #if ((MAINCLKSEL_Val & 0x03) == 0) |
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0:01f31e923fe2 | 272 | #define __MAIN_CLOCK (__IRC_OSC_CLK) |
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0:01f31e923fe2 | 273 | #elif ((MAINCLKSEL_Val & 0x03) == 1) |
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0:01f31e923fe2 | 274 | #define __MAIN_CLOCK (__SYS_PLLCLKIN) |
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0:01f31e923fe2 | 275 | #elif ((MAINCLKSEL_Val & 0x03) == 2) |
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0:01f31e923fe2 | 276 | #if (__FREQSEL == 0) |
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0:01f31e923fe2 | 277 | #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" |
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0:01f31e923fe2 | 278 | #else |
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0:01f31e923fe2 | 279 | #define __MAIN_CLOCK (__WDT_OSC_CLK) |
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0:01f31e923fe2 | 280 | #endif |
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0:01f31e923fe2 | 281 | #elif ((MAINCLKSEL_Val & 0x03) == 3) |
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0:01f31e923fe2 | 282 | #define __MAIN_CLOCK (__SYS_PLLCLKOUT) |
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0:01f31e923fe2 | 283 | #else |
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0:01f31e923fe2 | 284 | #define __MAIN_CLOCK (0) |
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0:01f31e923fe2 | 285 | #endif |
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0:01f31e923fe2 | 286 | |
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0:01f31e923fe2 | 287 | #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) |
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0:01f31e923fe2 | 288 | |
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0:01f31e923fe2 | 289 | #else |
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0:01f31e923fe2 | 290 | #define __SYSTEM_CLOCK (__IRC_OSC_CLK) |
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0:01f31e923fe2 | 291 | #endif // CLOCK_SETUP |
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0:01f31e923fe2 | 292 | |
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0:01f31e923fe2 | 293 | |
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0:01f31e923fe2 | 294 | /*---------------------------------------------------------------------------- |
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0:01f31e923fe2 | 295 | Clock Variable definitions |
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0:01f31e923fe2 | 296 | *----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 297 | uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ |
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0:01f31e923fe2 | 298 | |
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0:01f31e923fe2 | 299 | |
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0:01f31e923fe2 | 300 | /*---------------------------------------------------------------------------- |
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0:01f31e923fe2 | 301 | Clock functions |
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0:01f31e923fe2 | 302 | *----------------------------------------------------------------------------*/ |
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0:01f31e923fe2 | 303 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
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0:01f31e923fe2 | 304 | { |
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0:01f31e923fe2 | 305 | uint32_t wdt_osc = 0; |
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0:01f31e923fe2 | 306 | |
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0:01f31e923fe2 | 307 | /* Determine clock frequency according to clock register values */ |
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0:01f31e923fe2 | 308 | switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { |
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0:01f31e923fe2 | 309 | case 0: wdt_osc = 0; break; |
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0:01f31e923fe2 | 310 | case 1: wdt_osc = 500000; break; |
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0:01f31e923fe2 | 311 | case 2: wdt_osc = 800000; break; |
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0:01f31e923fe2 | 312 | case 3: wdt_osc = 1100000; break; |
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0:01f31e923fe2 | 313 | case 4: wdt_osc = 1400000; break; |
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0:01f31e923fe2 | 314 | case 5: wdt_osc = 1600000; break; |
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0:01f31e923fe2 | 315 | case 6: wdt_osc = 1800000; break; |
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0:01f31e923fe2 | 316 | case 7: wdt_osc = 2000000; break; |
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0:01f31e923fe2 | 317 | case 8: wdt_osc = 2200000; break; |
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0:01f31e923fe2 | 318 | case 9: wdt_osc = 2400000; break; |
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0:01f31e923fe2 | 319 | case 10: wdt_osc = 2600000; break; |
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0:01f31e923fe2 | 320 | case 11: wdt_osc = 2700000; break; |
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0:01f31e923fe2 | 321 | case 12: wdt_osc = 2900000; break; |
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0:01f31e923fe2 | 322 | case 13: wdt_osc = 3100000; break; |
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0:01f31e923fe2 | 323 | case 14: wdt_osc = 3200000; break; |
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0:01f31e923fe2 | 324 | case 15: wdt_osc = 3400000; break; |
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0:01f31e923fe2 | 325 | } |
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0:01f31e923fe2 | 326 | wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; |
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0:01f31e923fe2 | 327 | |
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0:01f31e923fe2 | 328 | switch (LPC_SYSCON->MAINCLKSEL & 0x03) { |
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0:01f31e923fe2 | 329 | case 0: /* Internal RC oscillator */ |
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0:01f31e923fe2 | 330 | SystemCoreClock = __IRC_OSC_CLK; |
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0:01f31e923fe2 | 331 | break; |
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0:01f31e923fe2 | 332 | case 1: /* Input Clock to System PLL */ |
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0:01f31e923fe2 | 333 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
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0:01f31e923fe2 | 334 | case 0: /* Internal RC oscillator */ |
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0:01f31e923fe2 | 335 | SystemCoreClock = __IRC_OSC_CLK; |
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0:01f31e923fe2 | 336 | break; |
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0:01f31e923fe2 | 337 | case 1: /* System oscillator */ |
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0:01f31e923fe2 | 338 | SystemCoreClock = __SYS_OSC_CLK; |
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0:01f31e923fe2 | 339 | break; |
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0:01f31e923fe2 | 340 | case 2: /* Reserved */ |
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0:01f31e923fe2 | 341 | case 3: /* Reserved */ |
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0:01f31e923fe2 | 342 | SystemCoreClock = 0; |
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0:01f31e923fe2 | 343 | break; |
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0:01f31e923fe2 | 344 | } |
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0:01f31e923fe2 | 345 | break; |
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0:01f31e923fe2 | 346 | case 2: /* WDT Oscillator */ |
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0:01f31e923fe2 | 347 | SystemCoreClock = wdt_osc; |
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0:01f31e923fe2 | 348 | break; |
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0:01f31e923fe2 | 349 | case 3: /* System PLL Clock Out */ |
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0:01f31e923fe2 | 350 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
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0:01f31e923fe2 | 351 | case 0: /* Internal RC oscillator */ |
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0:01f31e923fe2 | 352 | if (LPC_SYSCON->SYSPLLCTRL & 0x180) { |
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0:01f31e923fe2 | 353 | SystemCoreClock = __IRC_OSC_CLK; |
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0:01f31e923fe2 | 354 | } else { |
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0:01f31e923fe2 | 355 | SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
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0:01f31e923fe2 | 356 | } |
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0:01f31e923fe2 | 357 | break; |
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0:01f31e923fe2 | 358 | case 1: /* System oscillator */ |
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0:01f31e923fe2 | 359 | if (LPC_SYSCON->SYSPLLCTRL & 0x180) { |
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0:01f31e923fe2 | 360 | SystemCoreClock = __SYS_OSC_CLK; |
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0:01f31e923fe2 | 361 | } else { |
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0:01f31e923fe2 | 362 | SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
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0:01f31e923fe2 | 363 | } |
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0:01f31e923fe2 | 364 | break; |
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0:01f31e923fe2 | 365 | case 2: /* Reserved */ |
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0:01f31e923fe2 | 366 | case 3: /* Reserved */ |
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0:01f31e923fe2 | 367 | SystemCoreClock = 0; |
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0:01f31e923fe2 | 368 | break; |
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0:01f31e923fe2 | 369 | } |
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0:01f31e923fe2 | 370 | break; |
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0:01f31e923fe2 | 371 | } |
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0:01f31e923fe2 | 372 | |
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0:01f31e923fe2 | 373 | SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; |
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0:01f31e923fe2 | 374 | |
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0:01f31e923fe2 | 375 | } |
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0:01f31e923fe2 | 376 | |
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0:01f31e923fe2 | 377 | /** |
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0:01f31e923fe2 | 378 | * Initialize the system |
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0:01f31e923fe2 | 379 | * |
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0:01f31e923fe2 | 380 | * @param none |
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0:01f31e923fe2 | 381 | * @return none |
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0:01f31e923fe2 | 382 | * |
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0:01f31e923fe2 | 383 | * @brief Setup the microcontroller system. |
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0:01f31e923fe2 | 384 | * Initialize the System. |
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0:01f31e923fe2 | 385 | */ |
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0:01f31e923fe2 | 386 | void SystemInit (void) { |
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0:01f31e923fe2 | 387 | volatile uint32_t i; |
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0:01f31e923fe2 | 388 | |
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0:01f31e923fe2 | 389 | // Enable USBRAM and SRAM1 |
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0:01f31e923fe2 | 390 | LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 26) | (1 << 27); |
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0:01f31e923fe2 | 391 | |
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0:01f31e923fe2 | 392 | #if (CLOCK_SETUP) /* Clock Setup */ |
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0:01f31e923fe2 | 393 | |
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0:01f31e923fe2 | 394 | #if ((SYSPLLCLKSEL_Val & 0x03) == 1) |
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0:01f31e923fe2 | 395 | LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ |
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0:01f31e923fe2 | 396 | LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; |
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0:01f31e923fe2 | 397 | for (i = 0; i < 200; i++) __NOP(); |
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0:01f31e923fe2 | 398 | #endif |
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0:01f31e923fe2 | 399 | |
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0:01f31e923fe2 | 400 | LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ |
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0:01f31e923fe2 | 401 | LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ |
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0:01f31e923fe2 | 402 | LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ |
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0:01f31e923fe2 | 403 | LPC_SYSCON->SYSPLLCLKUEN = 0x01; |
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0:01f31e923fe2 | 404 | while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
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0:01f31e923fe2 | 405 | #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ |
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0:01f31e923fe2 | 406 | LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; |
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0:01f31e923fe2 | 407 | LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ |
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0:01f31e923fe2 | 408 | while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
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0:01f31e923fe2 | 409 | #endif |
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0:01f31e923fe2 | 410 | |
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0:01f31e923fe2 | 411 | #if (((MAINCLKSEL_Val & 0x03) == 2) ) |
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0:01f31e923fe2 | 412 | LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; |
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0:01f31e923fe2 | 413 | LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ |
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0:01f31e923fe2 | 414 | for (i = 0; i < 200; i++) __NOP(); |
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0:01f31e923fe2 | 415 | #endif |
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0:01f31e923fe2 | 416 | |
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0:01f31e923fe2 | 417 | LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ |
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0:01f31e923fe2 | 418 | LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ |
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0:01f31e923fe2 | 419 | LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ |
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0:01f31e923fe2 | 420 | LPC_SYSCON->MAINCLKUEN = 0x01; |
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0:01f31e923fe2 | 421 | while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ |
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0:01f31e923fe2 | 422 | |
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0:01f31e923fe2 | 423 | LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; |
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0:01f31e923fe2 | 424 | |
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0:01f31e923fe2 | 425 | #if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */ |
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0:01f31e923fe2 | 426 | LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ |
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0:01f31e923fe2 | 427 | |
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0:01f31e923fe2 | 428 | #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */ |
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0:01f31e923fe2 | 429 | LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ |
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0:01f31e923fe2 | 430 | LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ |
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0:01f31e923fe2 | 431 | LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ |
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0:01f31e923fe2 | 432 | LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ |
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0:01f31e923fe2 | 433 | LPC_SYSCON->USBPLLCLKUEN = 0x01; |
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0:01f31e923fe2 | 434 | while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
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0:01f31e923fe2 | 435 | LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; |
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0:01f31e923fe2 | 436 | while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
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0:01f31e923fe2 | 437 | LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ |
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0:01f31e923fe2 | 438 | #endif |
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0:01f31e923fe2 | 439 | |
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0:01f31e923fe2 | 440 | LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ |
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0:01f31e923fe2 | 441 | LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ |
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0:01f31e923fe2 | 442 | |
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0:01f31e923fe2 | 443 | #else /* USB clock is not used */ |
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0:01f31e923fe2 | 444 | LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ |
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0:01f31e923fe2 | 445 | LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ |
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0:01f31e923fe2 | 446 | #endif |
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0:01f31e923fe2 | 447 | |
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0:01f31e923fe2 | 448 | #endif |
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0:01f31e923fe2 | 449 | |
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0:01f31e923fe2 | 450 | /* System clock to the IOCON needs to be enabled or |
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0:01f31e923fe2 | 451 | most of the I/O related peripherals won't work. */ |
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0:01f31e923fe2 | 452 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); |
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0:01f31e923fe2 | 453 | |
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0:01f31e923fe2 | 454 | } |