Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nxp/lpc11u35/DAP_config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file DAP_config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 27 /**
Pawel Zarembski 0:01f31e923fe2 28 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
Pawel Zarembski 0:01f31e923fe2 29 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 30 @{
Pawel Zarembski 0:01f31e923fe2 31 Provides definitions about:
Pawel Zarembski 0:01f31e923fe2 32 - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 33 - Debug Unit communication packet size.
Pawel Zarembski 0:01f31e923fe2 34 - Debug Access Port communication mode (JTAG or SWD).
Pawel Zarembski 0:01f31e923fe2 35 - Optional information about a connected Target Device (for Evaluation Boards).
Pawel Zarembski 0:01f31e923fe2 36 */
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 // Board configuration options
Pawel Zarembski 0:01f31e923fe2 41
Pawel Zarembski 0:01f31e923fe2 42 // Configure JTAG option
Pawel Zarembski 0:01f31e923fe2 43 #if defined(BOARD_BAMBINO_210) || defined(BOARD_BAMBINO_210E)
Pawel Zarembski 0:01f31e923fe2 44 // LPC43xx multicore targets require JTAG to debug slave cores
Pawel Zarembski 0:01f31e923fe2 45 #define CONF_JTAG
Pawel Zarembski 0:01f31e923fe2 46 #endif
Pawel Zarembski 0:01f31e923fe2 47
Pawel Zarembski 0:01f31e923fe2 48 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
Pawel Zarembski 0:01f31e923fe2 49 /// This value is used to calculate the SWD/JTAG clock speed.
Pawel Zarembski 0:01f31e923fe2 50 #define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz
Pawel Zarembski 0:01f31e923fe2 51
Pawel Zarembski 0:01f31e923fe2 52 /// Number of processor cycles for I/O Port write operations.
Pawel Zarembski 0:01f31e923fe2 53 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
Pawel Zarembski 0:01f31e923fe2 54 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
Pawel Zarembski 0:01f31e923fe2 55 /// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
Pawel Zarembski 0:01f31e923fe2 56 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
Pawel Zarembski 0:01f31e923fe2 57 /// required.
Pawel Zarembski 0:01f31e923fe2 58 #define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
Pawel Zarembski 0:01f31e923fe2 59
Pawel Zarembski 0:01f31e923fe2 60 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 61 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 62 #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 63
Pawel Zarembski 0:01f31e923fe2 64 /// Indicate that JTAG communication mode is available at the Debug Port.
Pawel Zarembski 0:01f31e923fe2 65 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 66 #if defined(CONF_JTAG)
Pawel Zarembski 0:01f31e923fe2 67 #define DAP_JTAG 1 ///< JTAG Mode: 1 = available
Pawel Zarembski 0:01f31e923fe2 68 #else
Pawel Zarembski 0:01f31e923fe2 69 #define DAP_JTAG 0 ///< JTAG Mode: 0 = not available
Pawel Zarembski 0:01f31e923fe2 70 #endif
Pawel Zarembski 0:01f31e923fe2 71
Pawel Zarembski 0:01f31e923fe2 72 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 73 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
Pawel Zarembski 0:01f31e923fe2 74 #define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
Pawel Zarembski 0:01f31e923fe2 75
Pawel Zarembski 0:01f31e923fe2 76 /// Default communication mode on the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 77 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
Pawel Zarembski 0:01f31e923fe2 78 #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
Pawel Zarembski 0:01f31e923fe2 79
Pawel Zarembski 0:01f31e923fe2 80 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
Pawel Zarembski 0:01f31e923fe2 81 /// Used to initialize the default SWD/JTAG clock frequency.
Pawel Zarembski 0:01f31e923fe2 82 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
Pawel Zarembski 0:01f31e923fe2 83 #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 /// Maximum Package Size for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 86 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 87 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 88 #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 89
Pawel Zarembski 0:01f31e923fe2 90 /// Maximum Package Buffers for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 91 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 92 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
Pawel Zarembski 0:01f31e923fe2 93 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 94 #define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 95
Pawel Zarembski 0:01f31e923fe2 96 /// Indicate that UART Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 97 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 98 #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 /// Maximum SWO UART Baudrate
Pawel Zarembski 0:01f31e923fe2 101 #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
Pawel Zarembski 0:01f31e923fe2 102
Pawel Zarembski 0:01f31e923fe2 103 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 104 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 105 #define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 106
Pawel Zarembski 0:01f31e923fe2 107 /// SWO Trace Buffer Size.
Pawel Zarembski 0:01f31e923fe2 108 #define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
Pawel Zarembski 0:01f31e923fe2 109
Pawel Zarembski 0:01f31e923fe2 110 /// SWO Streaming Trace.
Pawel Zarembski 0:01f31e923fe2 111 #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
Pawel Zarembski 0:01f31e923fe2 114 #define TIMESTAMP_CLOCK 0 //100000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 /// Debug Unit is connected to fixed Target Device.
Pawel Zarembski 0:01f31e923fe2 117 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
Pawel Zarembski 0:01f31e923fe2 118 /// known device. In this case a Device Vendor and Device Name string is stored which
Pawel Zarembski 0:01f31e923fe2 119 /// may be used by the debugger or IDE to configure device parameters.
Pawel Zarembski 0:01f31e923fe2 120 #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
Pawel Zarembski 0:01f31e923fe2 121
Pawel Zarembski 0:01f31e923fe2 122 #if TARGET_DEVICE_FIXED
Pawel Zarembski 0:01f31e923fe2 123 #define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
Pawel Zarembski 0:01f31e923fe2 124 #define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
Pawel Zarembski 0:01f31e923fe2 125 #endif
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 ///@}
Pawel Zarembski 0:01f31e923fe2 128
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 131 /**
Pawel Zarembski 0:01f31e923fe2 132 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
Pawel Zarembski 0:01f31e923fe2 133 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 134 @{
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
Pawel Zarembski 0:01f31e923fe2 137 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
Pawel Zarembski 0:01f31e923fe2 138 interface of a device. The following I/O Pins are provided:
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140 JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
Pawel Zarembski 0:01f31e923fe2 141 ---------------------------- | -------------------- | ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 142 TCK: Test Clock | SWCLK: Clock | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 143 TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
Pawel Zarembski 0:01f31e923fe2 144 TDI: Test Data Input | | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 145 TDO: Test Data Output | | Input
Pawel Zarembski 0:01f31e923fe2 146 nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 147 nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 148
Pawel Zarembski 0:01f31e923fe2 149
Pawel Zarembski 0:01f31e923fe2 150 DAP Hardware I/O Pin Access Functions
Pawel Zarembski 0:01f31e923fe2 151 -------------------------------------
Pawel Zarembski 0:01f31e923fe2 152 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
Pawel Zarembski 0:01f31e923fe2 153 these I/O Pins.
Pawel Zarembski 0:01f31e923fe2 154
Pawel Zarembski 0:01f31e923fe2 155 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
Pawel Zarembski 0:01f31e923fe2 156 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
Pawel Zarembski 0:01f31e923fe2 157 peripherals that can independently write/read a single I/O pin without affecting any other pins
Pawel Zarembski 0:01f31e923fe2 158 of the same I/O port. The following SWDIO I/O Pin functions are provided:
Pawel Zarembski 0:01f31e923fe2 159 - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 160 - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 161 - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 162 - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 163 */
Pawel Zarembski 0:01f31e923fe2 164
Pawel Zarembski 0:01f31e923fe2 165
Pawel Zarembski 0:01f31e923fe2 166 // Configure DAP I/O pins ------------------------------
Pawel Zarembski 0:01f31e923fe2 167
Pawel Zarembski 0:01f31e923fe2 168 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Pawel Zarembski 0:01f31e923fe2 169 Configures the DAP Hardware I/O pins for JTAG mode:
Pawel Zarembski 0:01f31e923fe2 170 - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
Pawel Zarembski 0:01f31e923fe2 171 - TDO to input mode.
Pawel Zarembski 0:01f31e923fe2 172 */
Pawel Zarembski 0:01f31e923fe2 173 __STATIC_INLINE void PORT_JTAG_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 174 {
Pawel Zarembski 0:01f31e923fe2 175 #if (DAP_JTAG != 0)
Pawel Zarembski 0:01f31e923fe2 176 LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI;
Pawel Zarembski 0:01f31e923fe2 177 LPC_GPIO->DIR[PIN_TDI_PORT] |= PIN_TDI;
Pawel Zarembski 0:01f31e923fe2 178 LPC_GPIO->DIR[PIN_TDO_PORT] &= ~PIN_TDO;
Pawel Zarembski 0:01f31e923fe2 179 #endif
Pawel Zarembski 0:01f31e923fe2 180 }
Pawel Zarembski 0:01f31e923fe2 181
Pawel Zarembski 0:01f31e923fe2 182 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Pawel Zarembski 0:01f31e923fe2 183 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
Pawel Zarembski 0:01f31e923fe2 184 - SWCLK, SWDIO, nRESET to output mode and set to default high level.
Pawel Zarembski 0:01f31e923fe2 185 - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
Pawel Zarembski 0:01f31e923fe2 186 */
Pawel Zarembski 0:01f31e923fe2 187 __STATIC_INLINE void PORT_SWD_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 188 {
Pawel Zarembski 0:01f31e923fe2 189 LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 190 LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 191 #if !defined(PIN_nRESET_FET_DRIVE)
Pawel Zarembski 0:01f31e923fe2 192 // open drain logic
Pawel Zarembski 0:01f31e923fe2 193 LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 194 LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 195 #else
Pawel Zarembski 0:01f31e923fe2 196 // FET drive logic
Pawel Zarembski 0:01f31e923fe2 197 LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 198 LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 199 #endif
Pawel Zarembski 0:01f31e923fe2 200 LPC_GPIO->DIR[PIN_SWCLK_PORT] |= PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 201 LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 202 }
Pawel Zarembski 0:01f31e923fe2 203
Pawel Zarembski 0:01f31e923fe2 204 /** Disable JTAG/SWD I/O Pins.
Pawel Zarembski 0:01f31e923fe2 205 Disables the DAP Hardware I/O pins which configures:
Pawel Zarembski 0:01f31e923fe2 206 - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
Pawel Zarembski 0:01f31e923fe2 207 */
Pawel Zarembski 0:01f31e923fe2 208 __STATIC_INLINE void PORT_OFF(void)
Pawel Zarembski 0:01f31e923fe2 209 {
Pawel Zarembski 0:01f31e923fe2 210 #if !defined(PIN_nRESET_FET_DRIVE)
Pawel Zarembski 0:01f31e923fe2 211 // open drain logic
Pawel Zarembski 0:01f31e923fe2 212 LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 213 #else
Pawel Zarembski 0:01f31e923fe2 214 // FET drive logic
Pawel Zarembski 0:01f31e923fe2 215 LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 216 LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 217 #endif
Pawel Zarembski 0:01f31e923fe2 218 LPC_GPIO->DIR[PIN_SWCLK_PORT] &= ~PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 219 LPC_GPIO->DIR[PIN_SWDIO_PORT] &= ~PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 #if defined(TARGET_POWER_HOLD)
Pawel Zarembski 0:01f31e923fe2 222 //Release Target PowerHold
Pawel Zarembski 0:01f31e923fe2 223 LPC_GPIO->CLR[PIN_PWH_PORT] = PIN_PWH;
Pawel Zarembski 0:01f31e923fe2 224 #endif
Pawel Zarembski 0:01f31e923fe2 225 }
Pawel Zarembski 0:01f31e923fe2 226
Pawel Zarembski 0:01f31e923fe2 227
Pawel Zarembski 0:01f31e923fe2 228 // SWCLK/TCK I/O pin -------------------------------------
Pawel Zarembski 0:01f31e923fe2 229
Pawel Zarembski 0:01f31e923fe2 230 /** SWCLK/TCK I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 231 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 232 */
Pawel Zarembski 0:01f31e923fe2 233 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
Pawel Zarembski 0:01f31e923fe2 234 {
Pawel Zarembski 0:01f31e923fe2 235 return LPC_GPIO->B[PIN_SWCLK_BIT + PIN_SWCLK_PORT * 32] & 0x1;
Pawel Zarembski 0:01f31e923fe2 236 }
Pawel Zarembski 0:01f31e923fe2 237
Pawel Zarembski 0:01f31e923fe2 238 /** SWCLK/TCK I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 239 Set the SWCLK/TCK DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 240 */
Pawel Zarembski 0:01f31e923fe2 241 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
Pawel Zarembski 0:01f31e923fe2 242 {
Pawel Zarembski 0:01f31e923fe2 243 LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 244 }
Pawel Zarembski 0:01f31e923fe2 245
Pawel Zarembski 0:01f31e923fe2 246 /** SWCLK/TCK I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 247 Set the SWCLK/TCK DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 248 */
Pawel Zarembski 0:01f31e923fe2 249 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
Pawel Zarembski 0:01f31e923fe2 250 {
Pawel Zarembski 0:01f31e923fe2 251 LPC_GPIO->CLR[PIN_SWCLK_PORT] = PIN_SWCLK;
Pawel Zarembski 0:01f31e923fe2 252 }
Pawel Zarembski 0:01f31e923fe2 253
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255 // SWDIO/TMS Pin I/O --------------------------------------
Pawel Zarembski 0:01f31e923fe2 256
Pawel Zarembski 0:01f31e923fe2 257 /** SWDIO/TMS I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 258 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 259 */
Pawel Zarembski 0:01f31e923fe2 260 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
Pawel Zarembski 0:01f31e923fe2 261 {
Pawel Zarembski 0:01f31e923fe2 262 return LPC_GPIO->B[PIN_SWDIO_BIT + PIN_SWDIO_PORT * 32] & 0x1;
Pawel Zarembski 0:01f31e923fe2 263 }
Pawel Zarembski 0:01f31e923fe2 264
Pawel Zarembski 0:01f31e923fe2 265 /** SWDIO/TMS I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 266 Set the SWDIO/TMS DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 267 */
Pawel Zarembski 0:01f31e923fe2 268 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
Pawel Zarembski 0:01f31e923fe2 269 {
Pawel Zarembski 0:01f31e923fe2 270 LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 271 }
Pawel Zarembski 0:01f31e923fe2 272
Pawel Zarembski 0:01f31e923fe2 273 /** SWDIO/TMS I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 274 Set the SWDIO/TMS DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 275 */
Pawel Zarembski 0:01f31e923fe2 276 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
Pawel Zarembski 0:01f31e923fe2 277 {
Pawel Zarembski 0:01f31e923fe2 278 LPC_GPIO->CLR[PIN_SWDIO_PORT] = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 279 }
Pawel Zarembski 0:01f31e923fe2 280
Pawel Zarembski 0:01f31e923fe2 281 /** SWDIO I/O pin: Get Input (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 282 \return Current status of the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 283 */
Pawel Zarembski 0:01f31e923fe2 284 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
Pawel Zarembski 0:01f31e923fe2 285 {
Pawel Zarembski 0:01f31e923fe2 286 return LPC_GPIO->B[PIN_SWDIO_BIT + PIN_SWDIO_PORT * 32] & 0x1;
Pawel Zarembski 0:01f31e923fe2 287 }
Pawel Zarembski 0:01f31e923fe2 288
Pawel Zarembski 0:01f31e923fe2 289 /** SWDIO I/O pin: Set Output (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 290 \param bit Output value for the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 291 */
Pawel Zarembski 0:01f31e923fe2 292 __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 293 {
Pawel Zarembski 0:01f31e923fe2 294 if (bit & 0x1) {
Pawel Zarembski 0:01f31e923fe2 295 LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 296 } else {
Pawel Zarembski 0:01f31e923fe2 297 LPC_GPIO->CLR[PIN_SWDIO_PORT] = PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 298 }
Pawel Zarembski 0:01f31e923fe2 299 }
Pawel Zarembski 0:01f31e923fe2 300
Pawel Zarembski 0:01f31e923fe2 301 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 302 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
Pawel Zarembski 0:01f31e923fe2 303 called prior \ref PIN_SWDIO_OUT function calls.
Pawel Zarembski 0:01f31e923fe2 304 */
Pawel Zarembski 0:01f31e923fe2 305 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
Pawel Zarembski 0:01f31e923fe2 306 {
Pawel Zarembski 0:01f31e923fe2 307 LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO;
Pawel Zarembski 0:01f31e923fe2 308 }
Pawel Zarembski 0:01f31e923fe2 309
Pawel Zarembski 0:01f31e923fe2 310 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 311 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
Pawel Zarembski 0:01f31e923fe2 312 called prior \ref PIN_SWDIO_IN function calls.
Pawel Zarembski 0:01f31e923fe2 313 */
Pawel Zarembski 0:01f31e923fe2 314 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
Pawel Zarembski 0:01f31e923fe2 315 {
Pawel Zarembski 0:01f31e923fe2 316 LPC_GPIO->DIR[PIN_SWDIO_PORT] &= ~(PIN_SWDIO);
Pawel Zarembski 0:01f31e923fe2 317 }
Pawel Zarembski 0:01f31e923fe2 318
Pawel Zarembski 0:01f31e923fe2 319
Pawel Zarembski 0:01f31e923fe2 320 // TDI Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 321
Pawel Zarembski 0:01f31e923fe2 322 /** TDI I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 323 \return Current status of the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 324 */
Pawel Zarembski 0:01f31e923fe2 325 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
Pawel Zarembski 0:01f31e923fe2 326 {
Pawel Zarembski 0:01f31e923fe2 327 #if (DAP_JTAG != 0)
Pawel Zarembski 0:01f31e923fe2 328 return LPC_GPIO->B[PIN_TDI_BIT + PIN_TDI_PORT * 32] & 0x1;
Pawel Zarembski 0:01f31e923fe2 329 #else
Pawel Zarembski 0:01f31e923fe2 330 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 331 #endif
Pawel Zarembski 0:01f31e923fe2 332 }
Pawel Zarembski 0:01f31e923fe2 333
Pawel Zarembski 0:01f31e923fe2 334 /** TDI I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 335 \param bit Output value for the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 336 */
Pawel Zarembski 0:01f31e923fe2 337 __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 338 {
Pawel Zarembski 0:01f31e923fe2 339 #if (DAP_JTAG != 0)
Pawel Zarembski 0:01f31e923fe2 340
Pawel Zarembski 0:01f31e923fe2 341 if (bit & 0x1) {
Pawel Zarembski 0:01f31e923fe2 342 LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI;
Pawel Zarembski 0:01f31e923fe2 343 } else {
Pawel Zarembski 0:01f31e923fe2 344 LPC_GPIO->CLR[PIN_TDI_PORT] = PIN_TDI;
Pawel Zarembski 0:01f31e923fe2 345 }
Pawel Zarembski 0:01f31e923fe2 346
Pawel Zarembski 0:01f31e923fe2 347 #else
Pawel Zarembski 0:01f31e923fe2 348 ; // Not available
Pawel Zarembski 0:01f31e923fe2 349 #endif
Pawel Zarembski 0:01f31e923fe2 350 }
Pawel Zarembski 0:01f31e923fe2 351
Pawel Zarembski 0:01f31e923fe2 352
Pawel Zarembski 0:01f31e923fe2 353 // TDO Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 354
Pawel Zarembski 0:01f31e923fe2 355 /** TDO I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 356 \return Current status of the TDO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 357 */
Pawel Zarembski 0:01f31e923fe2 358 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
Pawel Zarembski 0:01f31e923fe2 359 {
Pawel Zarembski 0:01f31e923fe2 360 #if (DAP_JTAG != 0)
Pawel Zarembski 0:01f31e923fe2 361 return LPC_GPIO->B[PIN_TDO_BIT + PIN_TDO_PORT * 32] & 0x1;
Pawel Zarembski 0:01f31e923fe2 362 #else
Pawel Zarembski 0:01f31e923fe2 363 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 364 #endif
Pawel Zarembski 0:01f31e923fe2 365 }
Pawel Zarembski 0:01f31e923fe2 366
Pawel Zarembski 0:01f31e923fe2 367
Pawel Zarembski 0:01f31e923fe2 368 // nTRST Pin I/O -------------------------------------------
Pawel Zarembski 0:01f31e923fe2 369
Pawel Zarembski 0:01f31e923fe2 370 /** nTRST I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 371 \return Current status of the nTRST DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 372 */
Pawel Zarembski 0:01f31e923fe2 373 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
Pawel Zarembski 0:01f31e923fe2 374 {
Pawel Zarembski 0:01f31e923fe2 375 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 376 }
Pawel Zarembski 0:01f31e923fe2 377
Pawel Zarembski 0:01f31e923fe2 378 /** nTRST I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 379 \param bit JTAG TRST Test Reset pin status:
Pawel Zarembski 0:01f31e923fe2 380 - 0: issue a JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 381 - 1: release JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 382 */
Pawel Zarembski 0:01f31e923fe2 383 __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 384 {
Pawel Zarembski 0:01f31e923fe2 385 ; // Not available
Pawel Zarembski 0:01f31e923fe2 386 }
Pawel Zarembski 0:01f31e923fe2 387
Pawel Zarembski 0:01f31e923fe2 388 // nRESET Pin I/O------------------------------------------
Pawel Zarembski 0:01f31e923fe2 389
Pawel Zarembski 0:01f31e923fe2 390 /** nRESET I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 391 \return Current status of the nRESET DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 392 */
Pawel Zarembski 0:01f31e923fe2 393 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
Pawel Zarembski 0:01f31e923fe2 394 {
Pawel Zarembski 0:01f31e923fe2 395 return LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1;
Pawel Zarembski 0:01f31e923fe2 396 }
Pawel Zarembski 0:01f31e923fe2 397
Pawel Zarembski 0:01f31e923fe2 398 /** nRESET I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 399 \param bit target device hardware reset pin status:
Pawel Zarembski 0:01f31e923fe2 400 - 0: issue a device hardware reset.
Pawel Zarembski 0:01f31e923fe2 401 - 1: release device hardware reset.
Pawel Zarembski 0:01f31e923fe2 402 */
Pawel Zarembski 0:01f31e923fe2 403 __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 404 {
Pawel Zarembski 0:01f31e923fe2 405 #if !defined(PIN_nRESET_FET_DRIVE)
Pawel Zarembski 0:01f31e923fe2 406 // open drain logic
Pawel Zarembski 0:01f31e923fe2 407 if (bit) {
Pawel Zarembski 0:01f31e923fe2 408 LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET; // input (pulled high external)
Pawel Zarembski 0:01f31e923fe2 409 } else {
Pawel Zarembski 0:01f31e923fe2 410 LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET; // output (low)
Pawel Zarembski 0:01f31e923fe2 411 }
Pawel Zarembski 0:01f31e923fe2 412 #else
Pawel Zarembski 0:01f31e923fe2 413 // FET drive logic
Pawel Zarembski 0:01f31e923fe2 414 if (bit) {
Pawel Zarembski 0:01f31e923fe2 415 LPC_GPIO->CLR[PIN_nRESET_PORT] = (PIN_nRESET);
Pawel Zarembski 0:01f31e923fe2 416 } else {
Pawel Zarembski 0:01f31e923fe2 417 LPC_GPIO->SET[PIN_nRESET_PORT] = (PIN_nRESET);
Pawel Zarembski 0:01f31e923fe2 418 }
Pawel Zarembski 0:01f31e923fe2 419 #endif
Pawel Zarembski 0:01f31e923fe2 420 }
Pawel Zarembski 0:01f31e923fe2 421
Pawel Zarembski 0:01f31e923fe2 422 ///@}
Pawel Zarembski 0:01f31e923fe2 423
Pawel Zarembski 0:01f31e923fe2 424
Pawel Zarembski 0:01f31e923fe2 425 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 426 /**
Pawel Zarembski 0:01f31e923fe2 427 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
Pawel Zarembski 0:01f31e923fe2 428 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 429 @{
Pawel Zarembski 0:01f31e923fe2 430
Pawel Zarembski 0:01f31e923fe2 431 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 432
Pawel Zarembski 0:01f31e923fe2 433 It is recommended to provide the following LEDs for status indication:
Pawel Zarembski 0:01f31e923fe2 434 - Connect LED: is active when the DAP hardware is connected to a debugger.
Pawel Zarembski 0:01f31e923fe2 435 - Running LED: is active when the debugger has put the target device into running state.
Pawel Zarembski 0:01f31e923fe2 436 */
Pawel Zarembski 0:01f31e923fe2 437
Pawel Zarembski 0:01f31e923fe2 438 /** Debug Unit: Set status of Connected LED.
Pawel Zarembski 0:01f31e923fe2 439 \param bit status of the Connect LED.
Pawel Zarembski 0:01f31e923fe2 440 - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 441 - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 442 */
Pawel Zarembski 0:01f31e923fe2 443 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 444 {
Pawel Zarembski 0:01f31e923fe2 445 }
Pawel Zarembski 0:01f31e923fe2 446
Pawel Zarembski 0:01f31e923fe2 447 /** Debug Unit: Set status Target Running LED.
Pawel Zarembski 0:01f31e923fe2 448 \param bit status of the Target Running LED.
Pawel Zarembski 0:01f31e923fe2 449 - 1: Target Running LED ON: program execution in target started.
Pawel Zarembski 0:01f31e923fe2 450 - 0: Target Running LED OFF: program execution in target stopped.
Pawel Zarembski 0:01f31e923fe2 451 */
Pawel Zarembski 0:01f31e923fe2 452 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 453 {
Pawel Zarembski 0:01f31e923fe2 454 ; // Not available
Pawel Zarembski 0:01f31e923fe2 455 }
Pawel Zarembski 0:01f31e923fe2 456
Pawel Zarembski 0:01f31e923fe2 457 ///@}
Pawel Zarembski 0:01f31e923fe2 458
Pawel Zarembski 0:01f31e923fe2 459
Pawel Zarembski 0:01f31e923fe2 460 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 461 /**
Pawel Zarembski 0:01f31e923fe2 462 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
Pawel Zarembski 0:01f31e923fe2 463 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 464 @{
Pawel Zarembski 0:01f31e923fe2 465 Access function for Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 466
Pawel Zarembski 0:01f31e923fe2 467 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
Pawel Zarembski 0:01f31e923fe2 468 default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
Pawel Zarembski 0:01f31e923fe2 469
Pawel Zarembski 0:01f31e923fe2 470 */
Pawel Zarembski 0:01f31e923fe2 471
Pawel Zarembski 0:01f31e923fe2 472 /** Get timestamp of Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 473 \return Current timestamp value.
Pawel Zarembski 0:01f31e923fe2 474 */
Pawel Zarembski 0:01f31e923fe2 475 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
Pawel Zarembski 0:01f31e923fe2 476 return 0; //(DWT->CYCCNT);
Pawel Zarembski 0:01f31e923fe2 477 }
Pawel Zarembski 0:01f31e923fe2 478
Pawel Zarembski 0:01f31e923fe2 479 ///@}
Pawel Zarembski 0:01f31e923fe2 480
Pawel Zarembski 0:01f31e923fe2 481
Pawel Zarembski 0:01f31e923fe2 482 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 483 /**
Pawel Zarembski 0:01f31e923fe2 484 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
Pawel Zarembski 0:01f31e923fe2 485 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 486 @{
Pawel Zarembski 0:01f31e923fe2 487
Pawel Zarembski 0:01f31e923fe2 488 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
Pawel Zarembski 0:01f31e923fe2 489 */
Pawel Zarembski 0:01f31e923fe2 490
Pawel Zarembski 0:01f31e923fe2 491 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
Pawel Zarembski 0:01f31e923fe2 492 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Pawel Zarembski 0:01f31e923fe2 493 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
Pawel Zarembski 0:01f31e923fe2 494 - I/O clock system enabled.
Pawel Zarembski 0:01f31e923fe2 495 - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
Pawel Zarembski 0:01f31e923fe2 496 - for nTRST, nRESET a weak pull-up (if available) is enabled.
Pawel Zarembski 0:01f31e923fe2 497 - LED output pins are enabled and LEDs are turned off.
Pawel Zarembski 0:01f31e923fe2 498 */
Pawel Zarembski 0:01f31e923fe2 499 __STATIC_INLINE void DAP_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 500 {
Pawel Zarembski 0:01f31e923fe2 501 // Configure I/O pins
Pawel Zarembski 0:01f31e923fe2 502 PIN_SWCLK_TCK_IOCON = PIN_SWCLK_TCK_IOCON_INIT; // SWCLK/TCK
Pawel Zarembski 0:01f31e923fe2 503 PIN_SWDIO_TMS_IOCON = PIN_SWDIO_TMS_IOCON_INIT; // SWDIO/TMS
Pawel Zarembski 0:01f31e923fe2 504 PIN_nRESET_IOCON = PIN_nRESET_IOCON_INIT; // nRESET
Pawel Zarembski 0:01f31e923fe2 505 #if (DAP_JTAG != 0)
Pawel Zarembski 0:01f31e923fe2 506 PIN_TDI_IOCON = PIN_TDI_IOCON_INIT; // TDI
Pawel Zarembski 0:01f31e923fe2 507 PIN_TDO_IOCON = PIN_TDO_IOCON_INIT; // TDO
Pawel Zarembski 0:01f31e923fe2 508 #endif
Pawel Zarembski 0:01f31e923fe2 509 }
Pawel Zarembski 0:01f31e923fe2 510
Pawel Zarembski 0:01f31e923fe2 511 /** Reset Target Device with custom specific I/O pin or command sequence.
Pawel Zarembski 0:01f31e923fe2 512 This function allows the optional implementation of a device specific reset sequence.
Pawel Zarembski 0:01f31e923fe2 513 It is called when the command \ref DAP_ResetTarget and is for example required
Pawel Zarembski 0:01f31e923fe2 514 when a device needs a time-critical unlock sequence that enables the debug port.
Pawel Zarembski 0:01f31e923fe2 515 \return 0 = no device specific reset sequence is implemented.\n
Pawel Zarembski 0:01f31e923fe2 516 1 = a device specific reset sequence is implemented.
Pawel Zarembski 0:01f31e923fe2 517 */
Pawel Zarembski 0:01f31e923fe2 518 __STATIC_INLINE uint32_t RESET_TARGET(void)
Pawel Zarembski 0:01f31e923fe2 519 {
Pawel Zarembski 0:01f31e923fe2 520 return (0); // change to '1' when a device reset sequence is implemented
Pawel Zarembski 0:01f31e923fe2 521 }
Pawel Zarembski 0:01f31e923fe2 522
Pawel Zarembski 0:01f31e923fe2 523 ///@}
Pawel Zarembski 0:01f31e923fe2 524
Pawel Zarembski 0:01f31e923fe2 525
Pawel Zarembski 0:01f31e923fe2 526 #endif /* __DAP_CONFIG_H__ */