Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nuvoton/m48ssidae/DAP_config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file DAP_config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "stdint.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "cmsis_os2.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 28 #include "uart.h"
Pawel Zarembski 0:01f31e923fe2 29 //#include "debug_cm.h"
Pawel Zarembski 0:01f31e923fe2 30 //#include "swd_host.h"
Pawel Zarembski 0:01f31e923fe2 31 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 32 /**
Pawel Zarembski 0:01f31e923fe2 33 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
Pawel Zarembski 0:01f31e923fe2 34 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 35 @{
Pawel Zarembski 0:01f31e923fe2 36 Provides definitions about:
Pawel Zarembski 0:01f31e923fe2 37 - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 38 - Debug Unit communication packet size.
Pawel Zarembski 0:01f31e923fe2 39 - Debug Access Port communication mode (JTAG or SWD).
Pawel Zarembski 0:01f31e923fe2 40 - Optional information about a connected Target Device (for Evaluation Boards).
Pawel Zarembski 0:01f31e923fe2 41 */
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
Pawel Zarembski 0:01f31e923fe2 44 /// This value is used to calculate the SWD/JTAG clock speed.
Pawel Zarembski 0:01f31e923fe2 45 #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 /// Number of processor cycles for I/O Port write operations.
Pawel Zarembski 0:01f31e923fe2 48 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
Pawel Zarembski 0:01f31e923fe2 49 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
Pawel Zarembski 0:01f31e923fe2 50 /// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
Pawel Zarembski 0:01f31e923fe2 51 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
Pawel Zarembski 0:01f31e923fe2 52 /// requrired.
Pawel Zarembski 0:01f31e923fe2 53 #define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 56 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 57 #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 /// Indicate that JTAG communication mode is available at the Debug Port.
Pawel Zarembski 0:01f31e923fe2 60 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 61 #define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 64 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
Pawel Zarembski 0:01f31e923fe2 65 #define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 /// Default communication mode on the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 68 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
Pawel Zarembski 0:01f31e923fe2 69 #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
Pawel Zarembski 0:01f31e923fe2 72 /// Used to initialize the default SWD/JTAG clock frequency.
Pawel Zarembski 0:01f31e923fe2 73 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
Pawel Zarembski 0:01f31e923fe2 74 #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
Pawel Zarembski 0:01f31e923fe2 75
Pawel Zarembski 0:01f31e923fe2 76 /// Maximum Package Size for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 77 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 78 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 79 #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 /// Maximum Package Buffers for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 82 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 83 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
Pawel Zarembski 0:01f31e923fe2 84 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 85 #define DAP_PACKET_COUNT 64 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 /// Indicate that UART Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 88 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 89 #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91 /// Maximum SWO UART Baudrate
Pawel Zarembski 0:01f31e923fe2 92 #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 95 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 96 #define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 97
Pawel Zarembski 0:01f31e923fe2 98 /// SWO Trace Buffer Size.
Pawel Zarembski 0:01f31e923fe2 99 #define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
Pawel Zarembski 0:01f31e923fe2 100
Pawel Zarembski 0:01f31e923fe2 101 /// SWO Streaming Trace.
Pawel Zarembski 0:01f31e923fe2 102 #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 103
Pawel Zarembski 0:01f31e923fe2 104 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
Pawel Zarembski 0:01f31e923fe2 105 #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
Pawel Zarembski 0:01f31e923fe2 106
Pawel Zarembski 0:01f31e923fe2 107 /// Debug Unit is connected to fixed Target Device.
Pawel Zarembski 0:01f31e923fe2 108 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
Pawel Zarembski 0:01f31e923fe2 109 /// known device. In this case a Device Vendor and Device Name string is stored which
Pawel Zarembski 0:01f31e923fe2 110 /// may be used by the debugger or IDE to configure device parameters.
Pawel Zarembski 0:01f31e923fe2 111 #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 #if TARGET_DEVICE_FIXED
Pawel Zarembski 0:01f31e923fe2 114 #define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
Pawel Zarembski 0:01f31e923fe2 115 #define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
Pawel Zarembski 0:01f31e923fe2 116 #endif
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118 ///@}
Pawel Zarembski 0:01f31e923fe2 119
Pawel Zarembski 0:01f31e923fe2 120 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 121 /**
Pawel Zarembski 0:01f31e923fe2 122 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
Pawel Zarembski 0:01f31e923fe2 123 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 124 @{
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
Pawel Zarembski 0:01f31e923fe2 127 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
Pawel Zarembski 0:01f31e923fe2 128 interface of a device. The following I/O Pins are provided:
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
Pawel Zarembski 0:01f31e923fe2 131 ---------------------------- | -------------------- | ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 132 TCK: Test Clock | SWCLK: Clock | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 133 TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
Pawel Zarembski 0:01f31e923fe2 134 TDI: Test Data Input | | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 135 TDO: Test Data Output | | Input
Pawel Zarembski 0:01f31e923fe2 136 nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 137 nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 138
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140 DAP Hardware I/O Pin Access Functions
Pawel Zarembski 0:01f31e923fe2 141 -------------------------------------
Pawel Zarembski 0:01f31e923fe2 142 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
Pawel Zarembski 0:01f31e923fe2 143 these I/O Pins.
Pawel Zarembski 0:01f31e923fe2 144
Pawel Zarembski 0:01f31e923fe2 145 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
Pawel Zarembski 0:01f31e923fe2 146 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
Pawel Zarembski 0:01f31e923fe2 147 peripherals that can independently write/read a single I/O pin without affecting any other pins
Pawel Zarembski 0:01f31e923fe2 148 of the same I/O port. The following SWDIO I/O Pin functions are provided:
Pawel Zarembski 0:01f31e923fe2 149 - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 150 - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 151 - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 152 - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 153 */
Pawel Zarembski 0:01f31e923fe2 154
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 // Configure DAP I/O pins ------------------------------
Pawel Zarembski 0:01f31e923fe2 157
Pawel Zarembski 0:01f31e923fe2 158 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Pawel Zarembski 0:01f31e923fe2 159 Configures the DAP Hardware I/O pins for JTAG mode:
Pawel Zarembski 0:01f31e923fe2 160 - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
Pawel Zarembski 0:01f31e923fe2 161 - TDO to input mode.
Pawel Zarembski 0:01f31e923fe2 162 */
Pawel Zarembski 0:01f31e923fe2 163 __STATIC_INLINE void PORT_JTAG_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 164 {
Pawel Zarembski 0:01f31e923fe2 165 #if (DAP_JTAG != 0)
Pawel Zarembski 0:01f31e923fe2 166 #endif
Pawel Zarembski 0:01f31e923fe2 167 }
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Pawel Zarembski 0:01f31e923fe2 170 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
Pawel Zarembski 0:01f31e923fe2 171 - SWCLK, SWDIO, nRESET to output mode and set to default high level.
Pawel Zarembski 0:01f31e923fe2 172 - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
Pawel Zarembski 0:01f31e923fe2 173 */
Pawel Zarembski 0:01f31e923fe2 174 __STATIC_INLINE void PORT_SWD_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 175 {
Pawel Zarembski 0:01f31e923fe2 176 SWD_DAT_IO = 1;
Pawel Zarembski 0:01f31e923fe2 177 SWD_CLK_IO = 1;
Pawel Zarembski 0:01f31e923fe2 178 DBG_RST_IO = 1;
Pawel Zarembski 0:01f31e923fe2 179 GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 180 GPIO_SetMode(SWD_CLK_GRP, (1 << SWD_CLK_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 181 GPIO_SetMode(DBG_RST_GRP, (1 << DBG_RST_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 182 }
Pawel Zarembski 0:01f31e923fe2 183
Pawel Zarembski 0:01f31e923fe2 184 /** Disable JTAG/SWD I/O Pins.
Pawel Zarembski 0:01f31e923fe2 185 Disables the DAP Hardware I/O pins which configures:
Pawel Zarembski 0:01f31e923fe2 186 - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
Pawel Zarembski 0:01f31e923fe2 187 */
Pawel Zarembski 0:01f31e923fe2 188 __STATIC_INLINE void PORT_OFF(void)
Pawel Zarembski 0:01f31e923fe2 189 {
Pawel Zarembski 0:01f31e923fe2 190 GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_INPUT);
Pawel Zarembski 0:01f31e923fe2 191 GPIO_SetMode(SWD_CLK_GRP, (1 << SWD_CLK_BIT), GPIO_MODE_INPUT);
Pawel Zarembski 0:01f31e923fe2 192 GPIO_SetMode(DBG_RST_GRP, (1 << DBG_RST_BIT), GPIO_MODE_INPUT);
Pawel Zarembski 0:01f31e923fe2 193 }
Pawel Zarembski 0:01f31e923fe2 194
Pawel Zarembski 0:01f31e923fe2 195 // SWCLK/TCK I/O pin -------------------------------------
Pawel Zarembski 0:01f31e923fe2 196
Pawel Zarembski 0:01f31e923fe2 197 /** SWCLK/TCK I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 198 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 199 */
Pawel Zarembski 0:01f31e923fe2 200 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
Pawel Zarembski 0:01f31e923fe2 201 {
Pawel Zarembski 0:01f31e923fe2 202 return SWD_CLK_IO;
Pawel Zarembski 0:01f31e923fe2 203 }
Pawel Zarembski 0:01f31e923fe2 204
Pawel Zarembski 0:01f31e923fe2 205 /** SWCLK/TCK I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 206 Set the SWCLK/TCK DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 207 */
Pawel Zarembski 0:01f31e923fe2 208 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
Pawel Zarembski 0:01f31e923fe2 209 {
Pawel Zarembski 0:01f31e923fe2 210 SWD_CLK_IO = 1;
Pawel Zarembski 0:01f31e923fe2 211 }
Pawel Zarembski 0:01f31e923fe2 212
Pawel Zarembski 0:01f31e923fe2 213 /** SWCLK/TCK I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 214 Set the SWCLK/TCK DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 215 */
Pawel Zarembski 0:01f31e923fe2 216 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
Pawel Zarembski 0:01f31e923fe2 217 {
Pawel Zarembski 0:01f31e923fe2 218 SWD_CLK_IO = 0;
Pawel Zarembski 0:01f31e923fe2 219 }
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 // SWDIO/TMS Pin I/O --------------------------------------
Pawel Zarembski 0:01f31e923fe2 222
Pawel Zarembski 0:01f31e923fe2 223 /** SWDIO/TMS I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 224 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 225 */
Pawel Zarembski 0:01f31e923fe2 226 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
Pawel Zarembski 0:01f31e923fe2 227 {
Pawel Zarembski 0:01f31e923fe2 228 return SWD_DAT_IO;
Pawel Zarembski 0:01f31e923fe2 229 }
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 /** SWDIO/TMS I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 232 Set the SWDIO/TMS DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 233 */
Pawel Zarembski 0:01f31e923fe2 234 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
Pawel Zarembski 0:01f31e923fe2 235 {
Pawel Zarembski 0:01f31e923fe2 236 SWD_DAT_IO = 1;
Pawel Zarembski 0:01f31e923fe2 237 }
Pawel Zarembski 0:01f31e923fe2 238
Pawel Zarembski 0:01f31e923fe2 239 /** SWDIO/TMS I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 240 Set the SWDIO/TMS DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 241 */
Pawel Zarembski 0:01f31e923fe2 242 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
Pawel Zarembski 0:01f31e923fe2 243 {
Pawel Zarembski 0:01f31e923fe2 244 SWD_DAT_IO = 0;
Pawel Zarembski 0:01f31e923fe2 245 }
Pawel Zarembski 0:01f31e923fe2 246
Pawel Zarembski 0:01f31e923fe2 247 /** SWDIO I/O pin: Get Input (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 248 \return Current status of the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 249 */
Pawel Zarembski 0:01f31e923fe2 250 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
Pawel Zarembski 0:01f31e923fe2 251 {
Pawel Zarembski 0:01f31e923fe2 252 return SWD_DAT_IO;
Pawel Zarembski 0:01f31e923fe2 253 }
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255 /** SWDIO I/O pin: Set Output (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 256 \param bit Output value for the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 257 */
Pawel Zarembski 0:01f31e923fe2 258 __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 259 {
Pawel Zarembski 0:01f31e923fe2 260 SWD_DAT_IO = bit;
Pawel Zarembski 0:01f31e923fe2 261 }
Pawel Zarembski 0:01f31e923fe2 262
Pawel Zarembski 0:01f31e923fe2 263 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 264 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
Pawel Zarembski 0:01f31e923fe2 265 called prior \ref PIN_SWDIO_OUT function calls.
Pawel Zarembski 0:01f31e923fe2 266 */
Pawel Zarembski 0:01f31e923fe2 267 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
Pawel Zarembski 0:01f31e923fe2 268 {
Pawel Zarembski 0:01f31e923fe2 269 GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 270 }
Pawel Zarembski 0:01f31e923fe2 271
Pawel Zarembski 0:01f31e923fe2 272 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 273 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
Pawel Zarembski 0:01f31e923fe2 274 called prior \ref PIN_SWDIO_IN function calls.
Pawel Zarembski 0:01f31e923fe2 275 */
Pawel Zarembski 0:01f31e923fe2 276 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
Pawel Zarembski 0:01f31e923fe2 277 {
Pawel Zarembski 0:01f31e923fe2 278 GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_INPUT);
Pawel Zarembski 0:01f31e923fe2 279 }
Pawel Zarembski 0:01f31e923fe2 280
Pawel Zarembski 0:01f31e923fe2 281
Pawel Zarembski 0:01f31e923fe2 282 // TDI Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 283
Pawel Zarembski 0:01f31e923fe2 284 /** TDI I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 285 \return Current status of the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 286 */
Pawel Zarembski 0:01f31e923fe2 287 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
Pawel Zarembski 0:01f31e923fe2 288 {
Pawel Zarembski 0:01f31e923fe2 289 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 290 }
Pawel Zarembski 0:01f31e923fe2 291
Pawel Zarembski 0:01f31e923fe2 292 /** TDI I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 293 \param bit Output value for the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 294 */
Pawel Zarembski 0:01f31e923fe2 295 __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 296 {
Pawel Zarembski 0:01f31e923fe2 297 ; // Not available
Pawel Zarembski 0:01f31e923fe2 298 }
Pawel Zarembski 0:01f31e923fe2 299
Pawel Zarembski 0:01f31e923fe2 300
Pawel Zarembski 0:01f31e923fe2 301 // TDO Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 302
Pawel Zarembski 0:01f31e923fe2 303 /** TDO I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 304 \return Current status of the TDO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 305 */
Pawel Zarembski 0:01f31e923fe2 306 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
Pawel Zarembski 0:01f31e923fe2 307 {
Pawel Zarembski 0:01f31e923fe2 308 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 309 }
Pawel Zarembski 0:01f31e923fe2 310
Pawel Zarembski 0:01f31e923fe2 311
Pawel Zarembski 0:01f31e923fe2 312 // nTRST Pin I/O -------------------------------------------
Pawel Zarembski 0:01f31e923fe2 313
Pawel Zarembski 0:01f31e923fe2 314 /** nTRST I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 315 \return Current status of the nTRST DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 316 */
Pawel Zarembski 0:01f31e923fe2 317 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
Pawel Zarembski 0:01f31e923fe2 318 {
Pawel Zarembski 0:01f31e923fe2 319 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 320 }
Pawel Zarembski 0:01f31e923fe2 321
Pawel Zarembski 0:01f31e923fe2 322 /** nTRST I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 323 \param bit JTAG TRST Test Reset pin status:
Pawel Zarembski 0:01f31e923fe2 324 - 0: issue a JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 325 - 1: release JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 326 */
Pawel Zarembski 0:01f31e923fe2 327 __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 328 {
Pawel Zarembski 0:01f31e923fe2 329 ; // Not available
Pawel Zarembski 0:01f31e923fe2 330 }
Pawel Zarembski 0:01f31e923fe2 331
Pawel Zarembski 0:01f31e923fe2 332 // nRESET Pin I/O------------------------------------------
Pawel Zarembski 0:01f31e923fe2 333
Pawel Zarembski 0:01f31e923fe2 334 /** nRESET I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 335 \return Current status of the nRESET DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 336 */
Pawel Zarembski 0:01f31e923fe2 337 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
Pawel Zarembski 0:01f31e923fe2 338 {
Pawel Zarembski 0:01f31e923fe2 339 return DBG_RST_IO;
Pawel Zarembski 0:01f31e923fe2 340 }
Pawel Zarembski 0:01f31e923fe2 341
Pawel Zarembski 0:01f31e923fe2 342 /** nRESET I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 343 \param bit target device hardware reset pin status:
Pawel Zarembski 0:01f31e923fe2 344 - 0: issue a device hardware reset.
Pawel Zarembski 0:01f31e923fe2 345 - 1: release device hardware reset.
Pawel Zarembski 0:01f31e923fe2 346 */
Pawel Zarembski 0:01f31e923fe2 347 // TODO - sw specific implementation should be created
Pawel Zarembski 0:01f31e923fe2 348
Pawel Zarembski 0:01f31e923fe2 349 __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 350 {
Pawel Zarembski 0:01f31e923fe2 351 DBG_RST_IO = bit;
Pawel Zarembski 0:01f31e923fe2 352 }
Pawel Zarembski 0:01f31e923fe2 353
Pawel Zarembski 0:01f31e923fe2 354 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 355 /**
Pawel Zarembski 0:01f31e923fe2 356 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
Pawel Zarembski 0:01f31e923fe2 357 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 358 @{
Pawel Zarembski 0:01f31e923fe2 359
Pawel Zarembski 0:01f31e923fe2 360 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 361
Pawel Zarembski 0:01f31e923fe2 362 It is recommended to provide the following LEDs for status indication:
Pawel Zarembski 0:01f31e923fe2 363 - Connect LED: is active when the DAP hardware is connected to a debugger.
Pawel Zarembski 0:01f31e923fe2 364 - Running LED: is active when the debugger has put the target device into running state.
Pawel Zarembski 0:01f31e923fe2 365 */
Pawel Zarembski 0:01f31e923fe2 366
Pawel Zarembski 0:01f31e923fe2 367 /** Debug Unit: Set status of Connected LED.
Pawel Zarembski 0:01f31e923fe2 368 \param bit status of the Connect LED.
Pawel Zarembski 0:01f31e923fe2 369 - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 370 - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 371 */
Pawel Zarembski 0:01f31e923fe2 372 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 373 {
Pawel Zarembski 0:01f31e923fe2 374 LED_ISP_IO = bit ? 0 : 1;
Pawel Zarembski 0:01f31e923fe2 375 }
Pawel Zarembski 0:01f31e923fe2 376
Pawel Zarembski 0:01f31e923fe2 377 /** Debug Unit: Set status Target Running LED.
Pawel Zarembski 0:01f31e923fe2 378 \param bit status of the Target Running LED.
Pawel Zarembski 0:01f31e923fe2 379 - 1: Target Running LED ON: program execution in target started.
Pawel Zarembski 0:01f31e923fe2 380 - 0: Target Running LED OFF: program execution in target stopped.
Pawel Zarembski 0:01f31e923fe2 381 */
Pawel Zarembski 0:01f31e923fe2 382 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 383 {
Pawel Zarembski 0:01f31e923fe2 384 LED_GRE_IO = bit ? 0 : 1;
Pawel Zarembski 0:01f31e923fe2 385 }
Pawel Zarembski 0:01f31e923fe2 386
Pawel Zarembski 0:01f31e923fe2 387 ///@}
Pawel Zarembski 0:01f31e923fe2 388
Pawel Zarembski 0:01f31e923fe2 389
Pawel Zarembski 0:01f31e923fe2 390 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 391 /**
Pawel Zarembski 0:01f31e923fe2 392 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
Pawel Zarembski 0:01f31e923fe2 393 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 394 @{
Pawel Zarembski 0:01f31e923fe2 395 Access function for Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 396
Pawel Zarembski 0:01f31e923fe2 397 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
Pawel Zarembski 0:01f31e923fe2 398 default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
Pawel Zarembski 0:01f31e923fe2 399
Pawel Zarembski 0:01f31e923fe2 400 */
Pawel Zarembski 0:01f31e923fe2 401
Pawel Zarembski 0:01f31e923fe2 402 /** Get timestamp of Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 403 \return Current timestamp value.
Pawel Zarembski 0:01f31e923fe2 404 */
Pawel Zarembski 0:01f31e923fe2 405 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
Pawel Zarembski 0:01f31e923fe2 406 return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
Pawel Zarembski 0:01f31e923fe2 407 }
Pawel Zarembski 0:01f31e923fe2 408
Pawel Zarembski 0:01f31e923fe2 409 ///@}
Pawel Zarembski 0:01f31e923fe2 410
Pawel Zarembski 0:01f31e923fe2 411
Pawel Zarembski 0:01f31e923fe2 412 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 413 /**
Pawel Zarembski 0:01f31e923fe2 414 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
Pawel Zarembski 0:01f31e923fe2 415 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 416 @{
Pawel Zarembski 0:01f31e923fe2 417
Pawel Zarembski 0:01f31e923fe2 418 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
Pawel Zarembski 0:01f31e923fe2 419 */
Pawel Zarembski 0:01f31e923fe2 420
Pawel Zarembski 0:01f31e923fe2 421 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
Pawel Zarembski 0:01f31e923fe2 422 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Pawel Zarembski 0:01f31e923fe2 423 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
Pawel Zarembski 0:01f31e923fe2 424 - I/O clock system enabled.
Pawel Zarembski 0:01f31e923fe2 425 - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
Pawel Zarembski 0:01f31e923fe2 426 - for nTRST, nRESET a weak pull-up (if available) is enabled.
Pawel Zarembski 0:01f31e923fe2 427 - LED output pins are enabled and LEDs are turned off.
Pawel Zarembski 0:01f31e923fe2 428 */
Pawel Zarembski 0:01f31e923fe2 429 __STATIC_INLINE void DAP_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 430 {
Pawel Zarembski 0:01f31e923fe2 431 GPIO_SetMode(LED_ICE_GRP, (1 << LED_ICE_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 432 GPIO_SetMode(LED_ISP_GRP, (1 << LED_ISP_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 433 GPIO_SetMode(LED_GRE_GRP, (1 << LED_GRE_BIT), GPIO_MODE_OUTPUT);
Pawel Zarembski 0:01f31e923fe2 434 LED_ICE_IO = 0;
Pawel Zarembski 0:01f31e923fe2 435 LED_ISP_IO = 1;
Pawel Zarembski 0:01f31e923fe2 436 LED_GRE_IO = 1;
Pawel Zarembski 0:01f31e923fe2 437 }
Pawel Zarembski 0:01f31e923fe2 438
Pawel Zarembski 0:01f31e923fe2 439 /** Reset Target Device with custom specific I/O pin or command sequence.
Pawel Zarembski 0:01f31e923fe2 440 This function allows the optional implementation of a device specific reset sequence.
Pawel Zarembski 0:01f31e923fe2 441 It is called when the command \ref DAP_ResetTarget and is for example required
Pawel Zarembski 0:01f31e923fe2 442 when a device needs a time-critical unlock sequence that enables the debug port.
Pawel Zarembski 0:01f31e923fe2 443 \return 0 = no device specific reset sequence is implemented.\n
Pawel Zarembski 0:01f31e923fe2 444 1 = a device specific reset sequence is implemented.
Pawel Zarembski 0:01f31e923fe2 445 */
Pawel Zarembski 0:01f31e923fe2 446 __STATIC_INLINE uint32_t RESET_TARGET(void)
Pawel Zarembski 0:01f31e923fe2 447 {
Pawel Zarembski 0:01f31e923fe2 448 return (0); // change to '1' when a device reset sequence is implemented
Pawel Zarembski 0:01f31e923fe2 449 }
Pawel Zarembski 0:01f31e923fe2 450
Pawel Zarembski 0:01f31e923fe2 451 ///@}
Pawel Zarembski 0:01f31e923fe2 452
Pawel Zarembski 0:01f31e923fe2 453
Pawel Zarembski 0:01f31e923fe2 454 #endif /* __DAP_CONFIG_H__ */