Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32625/uart_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ****************************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Permission is hereby granted, free of charge, to any person obtaining a
Pawel Zarembski 0:01f31e923fe2 5 * copy of this software and associated documentation files (the "Software"),
Pawel Zarembski 0:01f31e923fe2 6 * to deal in the Software without restriction, including without limitation
Pawel Zarembski 0:01f31e923fe2 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Pawel Zarembski 0:01f31e923fe2 8 * and/or sell copies of the Software, and to permit persons to whom the
Pawel Zarembski 0:01f31e923fe2 9 * Software is furnished to do so, subject to the following conditions:
Pawel Zarembski 0:01f31e923fe2 10 *
Pawel Zarembski 0:01f31e923fe2 11 * The above copyright notice and this permission notice shall be included
Pawel Zarembski 0:01f31e923fe2 12 * in all copies or substantial portions of the Software.
Pawel Zarembski 0:01f31e923fe2 13 *
Pawel Zarembski 0:01f31e923fe2 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Pawel Zarembski 0:01f31e923fe2 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Pawel Zarembski 0:01f31e923fe2 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Pawel Zarembski 0:01f31e923fe2 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Pawel Zarembski 0:01f31e923fe2 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Pawel Zarembski 0:01f31e923fe2 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Pawel Zarembski 0:01f31e923fe2 20 * OTHER DEALINGS IN THE SOFTWARE.
Pawel Zarembski 0:01f31e923fe2 21 *
Pawel Zarembski 0:01f31e923fe2 22 * Except as contained in this notice, the name of Maxim Integrated
Pawel Zarembski 0:01f31e923fe2 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Pawel Zarembski 0:01f31e923fe2 24 * Products, Inc. Branding Policy.
Pawel Zarembski 0:01f31e923fe2 25 *
Pawel Zarembski 0:01f31e923fe2 26 * The mere transfer of this software does not imply any licenses
Pawel Zarembski 0:01f31e923fe2 27 * of trade secrets, proprietary technology, copyrights, patents,
Pawel Zarembski 0:01f31e923fe2 28 * trademarks, maskwork rights, or any other form of intellectual
Pawel Zarembski 0:01f31e923fe2 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Pawel Zarembski 0:01f31e923fe2 30 * ownership rights.
Pawel Zarembski 0:01f31e923fe2 31 *
Pawel Zarembski 0:01f31e923fe2 32 *************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /* Define to prevent redundant inclusion */
Pawel Zarembski 0:01f31e923fe2 35 #ifndef _MXC_UART_REGS_H_
Pawel Zarembski 0:01f31e923fe2 36 #define _MXC_UART_REGS_H_
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 /* **** Includes **** */
Pawel Zarembski 0:01f31e923fe2 39 #include <stdint.h>
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 42 extern "C" {
Pawel Zarembski 0:01f31e923fe2 43 #endif
Pawel Zarembski 0:01f31e923fe2 44
Pawel Zarembski 0:01f31e923fe2 45 ///@cond
Pawel Zarembski 0:01f31e923fe2 46 /*
Pawel Zarembski 0:01f31e923fe2 47 If types are not defined elsewhere (CMSIS) define them here
Pawel Zarembski 0:01f31e923fe2 48 */
Pawel Zarembski 0:01f31e923fe2 49 #ifndef __IO
Pawel Zarembski 0:01f31e923fe2 50 #define __IO volatile
Pawel Zarembski 0:01f31e923fe2 51 #endif
Pawel Zarembski 0:01f31e923fe2 52 #ifndef __I
Pawel Zarembski 0:01f31e923fe2 53 #define __I volatile const
Pawel Zarembski 0:01f31e923fe2 54 #endif
Pawel Zarembski 0:01f31e923fe2 55 #ifndef __O
Pawel Zarembski 0:01f31e923fe2 56 #define __O volatile
Pawel Zarembski 0:01f31e923fe2 57 #endif
Pawel Zarembski 0:01f31e923fe2 58 #ifndef __R
Pawel Zarembski 0:01f31e923fe2 59 #define __R volatile const
Pawel Zarembski 0:01f31e923fe2 60 #endif
Pawel Zarembski 0:01f31e923fe2 61 ///@endcond
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 /**
Pawel Zarembski 0:01f31e923fe2 64 * @defgroup uart_registers UART Registers
Pawel Zarembski 0:01f31e923fe2 65 * @brief Registers, Bit Masks and Bit Positions
Pawel Zarembski 0:01f31e923fe2 66 * @ingroup uart_comm
Pawel Zarembski 0:01f31e923fe2 67 * @{
Pawel Zarembski 0:01f31e923fe2 68 */
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 /**
Pawel Zarembski 0:01f31e923fe2 71 * Structure type for the UART peripheral registers allowing direct 32-bit access to each register.
Pawel Zarembski 0:01f31e923fe2 72 */
Pawel Zarembski 0:01f31e923fe2 73 typedef struct {
Pawel Zarembski 0:01f31e923fe2 74 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART_CTRL Register - UART Control Register. */
Pawel Zarembski 0:01f31e923fe2 75 __IO uint32_t baud; /**< <tt>\b 0x0004:</tt> UART_BAUD Register - UART Baud Control Register. */
Pawel Zarembski 0:01f31e923fe2 76 __IO uint32_t tx_fifo_ctrl; /**< <tt>\b 0x0008:</tt> UART_TX_FIFO_CTRL Register - UART TX FIFO Control Register. */
Pawel Zarembski 0:01f31e923fe2 77 __IO uint32_t rx_fifo_ctrl; /**< <tt>\b 0x000C:</tt> UART_RX_FIFO_CTRL Register - UART RX FIFO Control Register. */
Pawel Zarembski 0:01f31e923fe2 78 __IO uint32_t md_ctrl; /**< <tt>\b 0x0010:</tt> UART_MD_CTRL Register - UART Multidrop Control Register. */
Pawel Zarembski 0:01f31e923fe2 79 __IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> UART_INTFL Register - UART Interrupt Flags. */
Pawel Zarembski 0:01f31e923fe2 80 __IO uint32_t inten; /**< <tt>\b 0x0018:</tt> UART_INTEN Register - UART Interrupt Enable/Disable Control. */
Pawel Zarembski 0:01f31e923fe2 81 #if (MXC_UART_REV > 0)
Pawel Zarembski 0:01f31e923fe2 82 __R uint32_t idle; /**< <tt>\b 0x001C:</tt> UART_IDLE Register - UART Idle Status */
Pawel Zarembski 0:01f31e923fe2 83 #endif
Pawel Zarembski 0:01f31e923fe2 84 } mxc_uart_regs_t;
Pawel Zarembski 0:01f31e923fe2 85 /**@} end of group uart_registers */
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 /**
Pawel Zarembski 0:01f31e923fe2 88 * @defgroup uart_fifos UART TX and RX FIFOs
Pawel Zarembski 0:01f31e923fe2 89 * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
Pawel Zarembski 0:01f31e923fe2 90 * @ingroup uart_registers
Pawel Zarembski 0:01f31e923fe2 91 * @{
Pawel Zarembski 0:01f31e923fe2 92 */
Pawel Zarembski 0:01f31e923fe2 93 /**
Pawel Zarembski 0:01f31e923fe2 94 * Structure type for accessing the UART Transmit and Receive FIFOs.
Pawel Zarembski 0:01f31e923fe2 95 */
Pawel Zarembski 0:01f31e923fe2 96 typedef struct {
Pawel Zarembski 0:01f31e923fe2 97 union {
Pawel Zarembski 0:01f31e923fe2 98 __IO uint8_t tx; /**< TX FIFO write point for data to transmit. */
Pawel Zarembski 0:01f31e923fe2 99 __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO. */
Pawel Zarembski 0:01f31e923fe2 100 __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO. */
Pawel Zarembski 0:01f31e923fe2 101 __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO. */
Pawel Zarembski 0:01f31e923fe2 102 };
Pawel Zarembski 0:01f31e923fe2 103 union {
Pawel Zarembski 0:01f31e923fe2 104 __IO uint8_t rx; /**< RX FIFO read point for received data. */
Pawel Zarembski 0:01f31e923fe2 105 __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO. */
Pawel Zarembski 0:01f31e923fe2 106 __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO. */
Pawel Zarembski 0:01f31e923fe2 107 __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO. */
Pawel Zarembski 0:01f31e923fe2 108 };
Pawel Zarembski 0:01f31e923fe2 109 } mxc_uart_fifo_regs_t;
Pawel Zarembski 0:01f31e923fe2 110 /**@} end of group uart_fifos */
Pawel Zarembski 0:01f31e923fe2 111
Pawel Zarembski 0:01f31e923fe2 112 /*
Pawel Zarembski 0:01f31e923fe2 113 Register offsets for module UART.
Pawel Zarembski 0:01f31e923fe2 114 */
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 #define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
Pawel Zarembski 0:01f31e923fe2 117 #define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
Pawel Zarembski 0:01f31e923fe2 118 #define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
Pawel Zarembski 0:01f31e923fe2 119 #define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
Pawel Zarembski 0:01f31e923fe2 120 #define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
Pawel Zarembski 0:01f31e923fe2 121 #define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
Pawel Zarembski 0:01f31e923fe2 122 #define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
Pawel Zarembski 0:01f31e923fe2 123 #define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
Pawel Zarembski 0:01f31e923fe2 124 #define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 /*
Pawel Zarembski 0:01f31e923fe2 128 Field positions and masks for module UART.
Pawel Zarembski 0:01f31e923fe2 129 */
Pawel Zarembski 0:01f31e923fe2 130
Pawel Zarembski 0:01f31e923fe2 131 #define MXC_F_UART_CTRL_UART_EN_POS 0
Pawel Zarembski 0:01f31e923fe2 132 #define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
Pawel Zarembski 0:01f31e923fe2 133 #define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
Pawel Zarembski 0:01f31e923fe2 134 #define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
Pawel Zarembski 0:01f31e923fe2 135 #define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
Pawel Zarembski 0:01f31e923fe2 136 #define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
Pawel Zarembski 0:01f31e923fe2 137 #define MXC_F_UART_CTRL_DATA_SIZE_POS 4
Pawel Zarembski 0:01f31e923fe2 138 #define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
Pawel Zarembski 0:01f31e923fe2 139 #define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
Pawel Zarembski 0:01f31e923fe2 140 #define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
Pawel Zarembski 0:01f31e923fe2 141 #define MXC_F_UART_CTRL_PARITY_POS 12
Pawel Zarembski 0:01f31e923fe2 142 #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
Pawel Zarembski 0:01f31e923fe2 143 #define MXC_F_UART_CTRL_CTS_EN_POS 16
Pawel Zarembski 0:01f31e923fe2 144 #define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
Pawel Zarembski 0:01f31e923fe2 145 #define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
Pawel Zarembski 0:01f31e923fe2 146 #define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
Pawel Zarembski 0:01f31e923fe2 147 #define MXC_F_UART_CTRL_RTS_EN_POS 18
Pawel Zarembski 0:01f31e923fe2 148 #define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
Pawel Zarembski 0:01f31e923fe2 149 #define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
Pawel Zarembski 0:01f31e923fe2 150 #define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
Pawel Zarembski 0:01f31e923fe2 151 #define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
Pawel Zarembski 0:01f31e923fe2 152 #define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
Pawel Zarembski 0:01f31e923fe2 153
Pawel Zarembski 0:01f31e923fe2 154 #define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
Pawel Zarembski 0:01f31e923fe2 155 #define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
Pawel Zarembski 0:01f31e923fe2 156 #define MXC_F_UART_BAUD_BAUD_MODE_POS 8
Pawel Zarembski 0:01f31e923fe2 157 #define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
Pawel Zarembski 0:01f31e923fe2 158
Pawel Zarembski 0:01f31e923fe2 159 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
Pawel Zarembski 0:01f31e923fe2 160 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
Pawel Zarembski 0:01f31e923fe2 161 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
Pawel Zarembski 0:01f31e923fe2 162 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
Pawel Zarembski 0:01f31e923fe2 163
Pawel Zarembski 0:01f31e923fe2 164 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
Pawel Zarembski 0:01f31e923fe2 165 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
Pawel Zarembski 0:01f31e923fe2 166 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
Pawel Zarembski 0:01f31e923fe2 167 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
Pawel Zarembski 0:01f31e923fe2 170 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
Pawel Zarembski 0:01f31e923fe2 171 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
Pawel Zarembski 0:01f31e923fe2 172 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
Pawel Zarembski 0:01f31e923fe2 173 #define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
Pawel Zarembski 0:01f31e923fe2 174 #define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
Pawel Zarembski 0:01f31e923fe2 175 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
Pawel Zarembski 0:01f31e923fe2 176 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
Pawel Zarembski 0:01f31e923fe2 177
Pawel Zarembski 0:01f31e923fe2 178 /**
Pawel Zarembski 0:01f31e923fe2 179 * @defgroup UART_INTFL_Register UART_INTFL
Pawel Zarembski 0:01f31e923fe2 180 * @ingroup uart_registers
Pawel Zarembski 0:01f31e923fe2 181 * @{
Pawel Zarembski 0:01f31e923fe2 182 */
Pawel Zarembski 0:01f31e923fe2 183 #define MXC_F_UART_INTFL_TX_DONE_POS 0
Pawel Zarembski 0:01f31e923fe2 184 #define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
Pawel Zarembski 0:01f31e923fe2 185 #define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
Pawel Zarembski 0:01f31e923fe2 186 #define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
Pawel Zarembski 0:01f31e923fe2 187 #define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
Pawel Zarembski 0:01f31e923fe2 188 #define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
Pawel Zarembski 0:01f31e923fe2 189 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
Pawel Zarembski 0:01f31e923fe2 190 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
Pawel Zarembski 0:01f31e923fe2 191 #define MXC_F_UART_INTFL_RX_STALLED_POS 4
Pawel Zarembski 0:01f31e923fe2 192 #define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
Pawel Zarembski 0:01f31e923fe2 193 #define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
Pawel Zarembski 0:01f31e923fe2 194 #define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
Pawel Zarembski 0:01f31e923fe2 195 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
Pawel Zarembski 0:01f31e923fe2 196 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
Pawel Zarembski 0:01f31e923fe2 197 #define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
Pawel Zarembski 0:01f31e923fe2 198 #define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
Pawel Zarembski 0:01f31e923fe2 199 #define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
Pawel Zarembski 0:01f31e923fe2 200 #define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
Pawel Zarembski 0:01f31e923fe2 201 /**@} end of group UART_INTFL_Register */
Pawel Zarembski 0:01f31e923fe2 202
Pawel Zarembski 0:01f31e923fe2 203 #define MXC_F_UART_INTEN_TX_DONE_POS 0
Pawel Zarembski 0:01f31e923fe2 204 #define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
Pawel Zarembski 0:01f31e923fe2 205 #define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
Pawel Zarembski 0:01f31e923fe2 206 #define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
Pawel Zarembski 0:01f31e923fe2 207 #define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
Pawel Zarembski 0:01f31e923fe2 208 #define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
Pawel Zarembski 0:01f31e923fe2 209 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
Pawel Zarembski 0:01f31e923fe2 210 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
Pawel Zarembski 0:01f31e923fe2 211 #define MXC_F_UART_INTEN_RX_STALLED_POS 4
Pawel Zarembski 0:01f31e923fe2 212 #define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
Pawel Zarembski 0:01f31e923fe2 213 #define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
Pawel Zarembski 0:01f31e923fe2 214 #define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
Pawel Zarembski 0:01f31e923fe2 215 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
Pawel Zarembski 0:01f31e923fe2 216 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
Pawel Zarembski 0:01f31e923fe2 217 #define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
Pawel Zarembski 0:01f31e923fe2 218 #define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
Pawel Zarembski 0:01f31e923fe2 219 #define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
Pawel Zarembski 0:01f31e923fe2 220 #define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
Pawel Zarembski 0:01f31e923fe2 221
Pawel Zarembski 0:01f31e923fe2 222 #if (MXC_UART_REV > 0)
Pawel Zarembski 0:01f31e923fe2 223 #define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
Pawel Zarembski 0:01f31e923fe2 224 #define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
Pawel Zarembski 0:01f31e923fe2 225 #define MXC_F_UART_IDLE_TX_IDLE_POS 1
Pawel Zarembski 0:01f31e923fe2 226 #define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
Pawel Zarembski 0:01f31e923fe2 227 #define MXC_F_UART_IDLE_RX_IDLE_POS 2
Pawel Zarembski 0:01f31e923fe2 228 #define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
Pawel Zarembski 0:01f31e923fe2 229 #endif
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 /*
Pawel Zarembski 0:01f31e923fe2 232 Field values and shifted values for module UART.
Pawel Zarembski 0:01f31e923fe2 233 */
Pawel Zarembski 0:01f31e923fe2 234
Pawel Zarembski 0:01f31e923fe2 235 #define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
Pawel Zarembski 0:01f31e923fe2 236 #define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
Pawel Zarembski 0:01f31e923fe2 237 #define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
Pawel Zarembski 0:01f31e923fe2 238 #define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
Pawel Zarembski 0:01f31e923fe2 239
Pawel Zarembski 0:01f31e923fe2 240 #define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
Pawel Zarembski 0:01f31e923fe2 241 #define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
Pawel Zarembski 0:01f31e923fe2 242 #define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
Pawel Zarembski 0:01f31e923fe2 243 #define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
Pawel Zarembski 0:01f31e923fe2 244
Pawel Zarembski 0:01f31e923fe2 245 #define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
Pawel Zarembski 0:01f31e923fe2 246 #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
Pawel Zarembski 0:01f31e923fe2 247 #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
Pawel Zarembski 0:01f31e923fe2 248 #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
Pawel Zarembski 0:01f31e923fe2 249
Pawel Zarembski 0:01f31e923fe2 250 #define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
Pawel Zarembski 0:01f31e923fe2 251 #define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
Pawel Zarembski 0:01f31e923fe2 252 #define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
Pawel Zarembski 0:01f31e923fe2 253 #define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 256 }
Pawel Zarembski 0:01f31e923fe2 257 #endif
Pawel Zarembski 0:01f31e923fe2 258
Pawel Zarembski 0:01f31e923fe2 259 #endif /* _MXC_UART_REGS_H_ */