Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32625/uart.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* CMSIS-DAP Interface Firmware
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2009-2013 ARM Limited
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Licensed under the Apache License, Version 2.0 (the "License");
Pawel Zarembski 0:01f31e923fe2 5 * you may not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 6 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 11 * distributed under the License is distributed on an "AS IS" BASIS,
Pawel Zarembski 0:01f31e923fe2 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 13 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 14 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 15 */
Pawel Zarembski 0:01f31e923fe2 16
Pawel Zarembski 0:01f31e923fe2 17 #include <string.h>
Pawel Zarembski 0:01f31e923fe2 18 #include "max32625.h"
Pawel Zarembski 0:01f31e923fe2 19 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 20 #include "clkman_regs.h"
Pawel Zarembski 0:01f31e923fe2 21 #include "ioman_regs.h"
Pawel Zarembski 0:01f31e923fe2 22 #include "gpio_regs.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "uart_regs.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "pwrman_regs.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "uart.h"
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 // Size must be 2^n
Pawel Zarembski 0:01f31e923fe2 28 #define BUFFER_SIZE (4096)
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
Pawel Zarembski 0:01f31e923fe2 31 MXC_F_UART_INTFL_RX_PARITY_ERR | \
Pawel Zarembski 0:01f31e923fe2 32 MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35 // Track bit rate to avoid calculation from bus clock, clock scaler and baud divisor values
Pawel Zarembski 0:01f31e923fe2 36 static uint32_t baudrate;
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 static mxc_uart_regs_t *CdcAcmUart = NULL;
Pawel Zarembski 0:01f31e923fe2 39 static mxc_uart_fifo_regs_t *CdcAcmUartFifo = NULL;
Pawel Zarembski 0:01f31e923fe2 40 static IRQn_Type CdcAcmUartIrqNumber = MXC_IRQ_EXT_COUNT;
Pawel Zarembski 0:01f31e923fe2 41
Pawel Zarembski 0:01f31e923fe2 42 static struct {
Pawel Zarembski 0:01f31e923fe2 43 uint8_t data[BUFFER_SIZE];
Pawel Zarembski 0:01f31e923fe2 44 volatile uint16_t idx_in;
Pawel Zarembski 0:01f31e923fe2 45 volatile uint16_t idx_out;
Pawel Zarembski 0:01f31e923fe2 46 volatile int16_t cnt_in;
Pawel Zarembski 0:01f31e923fe2 47 volatile int16_t cnt_out;
Pawel Zarembski 0:01f31e923fe2 48 } write_buffer, read_buffer;
Pawel Zarembski 0:01f31e923fe2 49
Pawel Zarembski 0:01f31e923fe2 50 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 51 static void set_bitrate(uint32_t bps)
Pawel Zarembski 0:01f31e923fe2 52 {
Pawel Zarembski 0:01f31e923fe2 53 uint32_t baud_divisor;
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 baud_divisor = SystemCoreClock / (1 << (MXC_CLKMAN->sys_clk_ctrl_8_uart - 1));
Pawel Zarembski 0:01f31e923fe2 56 baud_divisor /= (bps * 16);
Pawel Zarembski 0:01f31e923fe2 57 CdcAcmUart->baud = baud_divisor;
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 baudrate = bps;
Pawel Zarembski 0:01f31e923fe2 60 }
Pawel Zarembski 0:01f31e923fe2 61
Pawel Zarembski 0:01f31e923fe2 62 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 63 int32_t uart_set_instance(uint32_t inst)
Pawel Zarembski 0:01f31e923fe2 64 {
Pawel Zarembski 0:01f31e923fe2 65 if (inst == 0) {
Pawel Zarembski 0:01f31e923fe2 66 CdcAcmUart = MXC_UART0;
Pawel Zarembski 0:01f31e923fe2 67 CdcAcmUartFifo = MXC_UART0_FIFO;
Pawel Zarembski 0:01f31e923fe2 68 CdcAcmUartIrqNumber = UART0_IRQn;
Pawel Zarembski 0:01f31e923fe2 69 } else if (inst == 2) {
Pawel Zarembski 0:01f31e923fe2 70 CdcAcmUart = MXC_UART2;
Pawel Zarembski 0:01f31e923fe2 71 CdcAcmUartFifo = MXC_UART2_FIFO;
Pawel Zarembski 0:01f31e923fe2 72 CdcAcmUartIrqNumber = UART2_IRQn;
Pawel Zarembski 0:01f31e923fe2 73 } else {
Pawel Zarembski 0:01f31e923fe2 74 return 0;
Pawel Zarembski 0:01f31e923fe2 75 }
Pawel Zarembski 0:01f31e923fe2 76 return 1;
Pawel Zarembski 0:01f31e923fe2 77 }
Pawel Zarembski 0:01f31e923fe2 78
Pawel Zarembski 0:01f31e923fe2 79 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 80 int32_t uart_initialize(void)
Pawel Zarembski 0:01f31e923fe2 81 {
Pawel Zarembski 0:01f31e923fe2 82 int idx;
Pawel Zarembski 0:01f31e923fe2 83
Pawel Zarembski 0:01f31e923fe2 84 if (CdcAcmUart == MXC_UART0) {
Pawel Zarembski 0:01f31e923fe2 85 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER;
Pawel Zarembski 0:01f31e923fe2 86 if (MXC_CLKMAN->sys_clk_ctrl_8_uart != MXC_S_CLKMAN_CLK_SCALE_DIV_4) {
Pawel Zarembski 0:01f31e923fe2 87 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
Pawel Zarembski 0:01f31e923fe2 88 }
Pawel Zarembski 0:01f31e923fe2 89
Pawel Zarembski 0:01f31e923fe2 90 // Configure GPIO for UART
Pawel Zarembski 0:01f31e923fe2 91 MXC_IOMAN->uart0_req = ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ);
Pawel Zarembski 0:01f31e923fe2 92 while (MXC_IOMAN->uart0_ack != ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ));
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 } else if (CdcAcmUart == MXC_UART2) {
Pawel Zarembski 0:01f31e923fe2 95 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER;
Pawel Zarembski 0:01f31e923fe2 96 if (MXC_CLKMAN->sys_clk_ctrl_8_uart != MXC_S_CLKMAN_CLK_SCALE_DIV_4) {
Pawel Zarembski 0:01f31e923fe2 97 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
Pawel Zarembski 0:01f31e923fe2 98 }
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 // Configure GPIO for UART
Pawel Zarembski 0:01f31e923fe2 101 MXC_IOMAN->uart2_req = ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART2_REQ_IO_REQ);
Pawel Zarembski 0:01f31e923fe2 102 while (MXC_IOMAN->uart2_ack != ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART2_REQ_IO_REQ));
Pawel Zarembski 0:01f31e923fe2 103 } else {
Pawel Zarembski 0:01f31e923fe2 104 return 0;
Pawel Zarembski 0:01f31e923fe2 105 }
Pawel Zarembski 0:01f31e923fe2 106
Pawel Zarembski 0:01f31e923fe2 107 idx = MXC_UART_GET_IDX(CdcAcmUart);
Pawel Zarembski 0:01f31e923fe2 108 MXC_PWRMAN->peripheral_reset |= (MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx);
Pawel Zarembski 0:01f31e923fe2 109 MXC_PWRMAN->peripheral_reset &= ~((MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx));
Pawel Zarembski 0:01f31e923fe2 110
Pawel Zarembski 0:01f31e923fe2 111 // Flush RX and TX FIFOS
Pawel Zarembski 0:01f31e923fe2 112 CdcAcmUart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
Pawel Zarembski 0:01f31e923fe2 113
Pawel Zarembski 0:01f31e923fe2 114 // Disable interrupts
Pawel Zarembski 0:01f31e923fe2 115 CdcAcmUart->inten = 0;
Pawel Zarembski 0:01f31e923fe2 116 CdcAcmUart->intfl = CdcAcmUart->intfl;
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118 // Set the parity, size, stop and flow configuration
Pawel Zarembski 0:01f31e923fe2 119 CdcAcmUart->ctrl |= (MXC_S_UART_CTRL_DATA_SIZE_8_BITS | MXC_S_UART_CTRL_PARITY_DISABLE);
Pawel Zarembski 0:01f31e923fe2 120
Pawel Zarembski 0:01f31e923fe2 121 // Set receive fifo threshold to 0
Pawel Zarembski 0:01f31e923fe2 122 CdcAcmUart->rx_fifo_ctrl &= ~MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL;
Pawel Zarembski 0:01f31e923fe2 123 CdcAcmUart->rx_fifo_ctrl |= (0 << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
Pawel Zarembski 0:01f31e923fe2 124
Pawel Zarembski 0:01f31e923fe2 125 // Enable receive and transmit fifos
Pawel Zarembski 0:01f31e923fe2 126 CdcAcmUart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
Pawel Zarembski 0:01f31e923fe2 127
Pawel Zarembski 0:01f31e923fe2 128 NVIC_EnableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 // Set transmit almost empty level to three-quarters of the fifo size
Pawel Zarembski 0:01f31e923fe2 131 CdcAcmUart->tx_fifo_ctrl &= ~MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL;
Pawel Zarembski 0:01f31e923fe2 132 CdcAcmUart->tx_fifo_ctrl |= (MXC_UART_FIFO_DEPTH - (MXC_UART_FIFO_DEPTH >> 2)) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS;
Pawel Zarembski 0:01f31e923fe2 133
Pawel Zarembski 0:01f31e923fe2 134 // Enable RX and TX interrupts
Pawel Zarembski 0:01f31e923fe2 135 CdcAcmUart->inten = (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | MXC_F_UART_INTFL_RX_FIFO_OVERFLOW | MXC_F_UART_INTEN_TX_FIFO_AE);
Pawel Zarembski 0:01f31e923fe2 136
Pawel Zarembski 0:01f31e923fe2 137 // Enable UART
Pawel Zarembski 0:01f31e923fe2 138 CdcAcmUart->ctrl |= MXC_F_UART_CTRL_UART_EN;
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140 return 1;
Pawel Zarembski 0:01f31e923fe2 141 }
Pawel Zarembski 0:01f31e923fe2 142
Pawel Zarembski 0:01f31e923fe2 143 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 144 int32_t uart_uninitialize(void)
Pawel Zarembski 0:01f31e923fe2 145 {
Pawel Zarembski 0:01f31e923fe2 146 // Disable UART
Pawel Zarembski 0:01f31e923fe2 147 CdcAcmUart->ctrl &= ~MXC_F_UART_CTRL_UART_EN;
Pawel Zarembski 0:01f31e923fe2 148
Pawel Zarembski 0:01f31e923fe2 149 // Disable interrupts
Pawel Zarembski 0:01f31e923fe2 150 CdcAcmUart->inten = 0;
Pawel Zarembski 0:01f31e923fe2 151 NVIC_DisableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 152
Pawel Zarembski 0:01f31e923fe2 153 // Clear buffers
Pawel Zarembski 0:01f31e923fe2 154 memset(&write_buffer, 0, sizeof(write_buffer));
Pawel Zarembski 0:01f31e923fe2 155 memset(&read_buffer, 0, sizeof(read_buffer));
Pawel Zarembski 0:01f31e923fe2 156
Pawel Zarembski 0:01f31e923fe2 157 return 1;
Pawel Zarembski 0:01f31e923fe2 158 }
Pawel Zarembski 0:01f31e923fe2 159
Pawel Zarembski 0:01f31e923fe2 160 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 161 void uart_set_control_line_state(uint16_t ctrl_bmp)
Pawel Zarembski 0:01f31e923fe2 162 {
Pawel Zarembski 0:01f31e923fe2 163 }
Pawel Zarembski 0:01f31e923fe2 164
Pawel Zarembski 0:01f31e923fe2 165 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 166 int32_t uart_reset(void)
Pawel Zarembski 0:01f31e923fe2 167 {
Pawel Zarembski 0:01f31e923fe2 168 // Clear buffers
Pawel Zarembski 0:01f31e923fe2 169 memset(&write_buffer, 0, sizeof(write_buffer));
Pawel Zarembski 0:01f31e923fe2 170 memset(&read_buffer, 0, sizeof(read_buffer));
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 return 1;
Pawel Zarembski 0:01f31e923fe2 173 }
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 176 int32_t uart_set_configuration(UART_Configuration *config)
Pawel Zarembski 0:01f31e923fe2 177 {
Pawel Zarembski 0:01f31e923fe2 178 uint32_t ctrl;
Pawel Zarembski 0:01f31e923fe2 179
Pawel Zarembski 0:01f31e923fe2 180 // Get current configuration; clearing parameters that may be configured here
Pawel Zarembski 0:01f31e923fe2 181 ctrl = CdcAcmUart->ctrl & ~(MXC_F_UART_CTRL_PARITY |
Pawel Zarembski 0:01f31e923fe2 182 MXC_F_UART_CTRL_DATA_SIZE |
Pawel Zarembski 0:01f31e923fe2 183 MXC_F_UART_CTRL_EXTRA_STOP |
Pawel Zarembski 0:01f31e923fe2 184 MXC_F_UART_CTRL_CTS_EN |
Pawel Zarembski 0:01f31e923fe2 185 MXC_F_UART_CTRL_RTS_EN);
Pawel Zarembski 0:01f31e923fe2 186
Pawel Zarembski 0:01f31e923fe2 187 switch (config->Parity) {
Pawel Zarembski 0:01f31e923fe2 188 case UART_PARITY_NONE: break;
Pawel Zarembski 0:01f31e923fe2 189 case UART_PARITY_ODD: ctrl |= MXC_S_UART_CTRL_PARITY_ODD;
Pawel Zarembski 0:01f31e923fe2 190 case UART_PARITY_EVEN: ctrl |= MXC_S_UART_CTRL_PARITY_EVEN;
Pawel Zarembski 0:01f31e923fe2 191 case UART_PARITY_MARK: return 0;
Pawel Zarembski 0:01f31e923fe2 192 case UART_PARITY_SPACE: return 0;
Pawel Zarembski 0:01f31e923fe2 193 }
Pawel Zarembski 0:01f31e923fe2 194
Pawel Zarembski 0:01f31e923fe2 195 switch (config->DataBits) {
Pawel Zarembski 0:01f31e923fe2 196 case UART_DATA_BITS_5: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_5_BITS; break;
Pawel Zarembski 0:01f31e923fe2 197 case UART_DATA_BITS_6: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_6_BITS; break;
Pawel Zarembski 0:01f31e923fe2 198 case UART_DATA_BITS_7: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_7_BITS; break;
Pawel Zarembski 0:01f31e923fe2 199 case UART_DATA_BITS_8: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_8_BITS; break;
Pawel Zarembski 0:01f31e923fe2 200 case UART_DATA_BITS_16: return 0;
Pawel Zarembski 0:01f31e923fe2 201 }
Pawel Zarembski 0:01f31e923fe2 202
Pawel Zarembski 0:01f31e923fe2 203 switch (config->StopBits) {
Pawel Zarembski 0:01f31e923fe2 204 case UART_STOP_BITS_1: break;
Pawel Zarembski 0:01f31e923fe2 205 case UART_STOP_BITS_1_5:
Pawel Zarembski 0:01f31e923fe2 206 case UART_STOP_BITS_2: ctrl |= MXC_F_UART_CTRL_EXTRA_STOP; break;
Pawel Zarembski 0:01f31e923fe2 207 }
Pawel Zarembski 0:01f31e923fe2 208
Pawel Zarembski 0:01f31e923fe2 209 switch (config->FlowControl) {
Pawel Zarembski 0:01f31e923fe2 210 case UART_FLOW_CONTROL_NONE: break;
Pawel Zarembski 0:01f31e923fe2 211 case UART_FLOW_CONTROL_RTS_CTS: return 0;
Pawel Zarembski 0:01f31e923fe2 212 case UART_FLOW_CONTROL_XON_XOFF: return 0;
Pawel Zarembski 0:01f31e923fe2 213 }
Pawel Zarembski 0:01f31e923fe2 214
Pawel Zarembski 0:01f31e923fe2 215 set_bitrate(config->Baudrate);
Pawel Zarembski 0:01f31e923fe2 216
Pawel Zarembski 0:01f31e923fe2 217 // Set the new configuration
Pawel Zarembski 0:01f31e923fe2 218 CdcAcmUart->ctrl = ctrl;
Pawel Zarembski 0:01f31e923fe2 219
Pawel Zarembski 0:01f31e923fe2 220 return 1;
Pawel Zarembski 0:01f31e923fe2 221 }
Pawel Zarembski 0:01f31e923fe2 222
Pawel Zarembski 0:01f31e923fe2 223 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 224 int32_t uart_get_configuration(UART_Configuration *config)
Pawel Zarembski 0:01f31e923fe2 225 {
Pawel Zarembski 0:01f31e923fe2 226 uint32_t ctrl;
Pawel Zarembski 0:01f31e923fe2 227
Pawel Zarembski 0:01f31e923fe2 228 // Capture current configuration
Pawel Zarembski 0:01f31e923fe2 229 ctrl = CdcAcmUart->ctrl;
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 if (!(ctrl & MXC_S_UART_CTRL_PARITY_DISABLE)) {
Pawel Zarembski 0:01f31e923fe2 232 config->Parity = UART_PARITY_NONE;
Pawel Zarembski 0:01f31e923fe2 233 } else if (ctrl & MXC_S_UART_CTRL_PARITY_ODD) {
Pawel Zarembski 0:01f31e923fe2 234 config->Parity = UART_PARITY_ODD;
Pawel Zarembski 0:01f31e923fe2 235 } else {
Pawel Zarembski 0:01f31e923fe2 236 // Note both EVEN and MARK parity are captured here
Pawel Zarembski 0:01f31e923fe2 237 config->Parity = UART_PARITY_EVEN;
Pawel Zarembski 0:01f31e923fe2 238 }
Pawel Zarembski 0:01f31e923fe2 239
Pawel Zarembski 0:01f31e923fe2 240 switch (ctrl & MXC_F_UART_CTRL_DATA_SIZE) {
Pawel Zarembski 0:01f31e923fe2 241 case MXC_S_UART_CTRL_DATA_SIZE_5_BITS: config->DataBits = UART_DATA_BITS_5; break;
Pawel Zarembski 0:01f31e923fe2 242 case MXC_S_UART_CTRL_DATA_SIZE_6_BITS: config->DataBits = UART_DATA_BITS_6; break;
Pawel Zarembski 0:01f31e923fe2 243 case MXC_S_UART_CTRL_DATA_SIZE_7_BITS: config->DataBits = UART_DATA_BITS_7; break;
Pawel Zarembski 0:01f31e923fe2 244 case MXC_S_UART_CTRL_DATA_SIZE_8_BITS: config->DataBits = UART_DATA_BITS_8; break;
Pawel Zarembski 0:01f31e923fe2 245 }
Pawel Zarembski 0:01f31e923fe2 246
Pawel Zarembski 0:01f31e923fe2 247 if (!(ctrl & MXC_F_UART_CTRL_EXTRA_STOP)) {
Pawel Zarembski 0:01f31e923fe2 248 config->StopBits = UART_STOP_BITS_1;
Pawel Zarembski 0:01f31e923fe2 249 } else {
Pawel Zarembski 0:01f31e923fe2 250 config->StopBits = UART_STOP_BITS_2;
Pawel Zarembski 0:01f31e923fe2 251 }
Pawel Zarembski 0:01f31e923fe2 252
Pawel Zarembski 0:01f31e923fe2 253 if ((ctrl & (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) == (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) {
Pawel Zarembski 0:01f31e923fe2 254 config->FlowControl = UART_FLOW_CONTROL_RTS_CTS;
Pawel Zarembski 0:01f31e923fe2 255 } else {
Pawel Zarembski 0:01f31e923fe2 256 // Not true if only one of ...CST_EN and ...RTS_EN are asserted
Pawel Zarembski 0:01f31e923fe2 257 config->FlowControl = UART_FLOW_CONTROL_NONE;
Pawel Zarembski 0:01f31e923fe2 258 }
Pawel Zarembski 0:01f31e923fe2 259
Pawel Zarembski 0:01f31e923fe2 260 config->Baudrate = baudrate;
Pawel Zarembski 0:01f31e923fe2 261
Pawel Zarembski 0:01f31e923fe2 262 return 1;
Pawel Zarembski 0:01f31e923fe2 263 }
Pawel Zarembski 0:01f31e923fe2 264
Pawel Zarembski 0:01f31e923fe2 265 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 266 int32_t uart_write_free(void)
Pawel Zarembski 0:01f31e923fe2 267 {
Pawel Zarembski 0:01f31e923fe2 268 return BUFFER_SIZE - (write_buffer.cnt_in - write_buffer.cnt_out);
Pawel Zarembski 0:01f31e923fe2 269 }
Pawel Zarembski 0:01f31e923fe2 270
Pawel Zarembski 0:01f31e923fe2 271 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 272 int32_t uart_write_data(uint8_t *data, uint16_t size)
Pawel Zarembski 0:01f31e923fe2 273 {
Pawel Zarembski 0:01f31e923fe2 274 uint16_t xfer_count = size;
Pawel Zarembski 0:01f31e923fe2 275
Pawel Zarembski 0:01f31e923fe2 276 if (write_buffer.cnt_in == write_buffer.cnt_out) {
Pawel Zarembski 0:01f31e923fe2 277 while ((((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH) &&
Pawel Zarembski 0:01f31e923fe2 278 (xfer_count > 0)) {
Pawel Zarembski 0:01f31e923fe2 279
Pawel Zarembski 0:01f31e923fe2 280 NVIC_DisableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 281 CdcAcmUart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
Pawel Zarembski 0:01f31e923fe2 282 CdcAcmUartFifo->tx = *data++;
Pawel Zarembski 0:01f31e923fe2 283 xfer_count--;
Pawel Zarembski 0:01f31e923fe2 284 NVIC_EnableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 285
Pawel Zarembski 0:01f31e923fe2 286 }
Pawel Zarembski 0:01f31e923fe2 287 }
Pawel Zarembski 0:01f31e923fe2 288
Pawel Zarembski 0:01f31e923fe2 289 while (xfer_count > 0) {
Pawel Zarembski 0:01f31e923fe2 290 if ((write_buffer.cnt_in - write_buffer.cnt_out) < BUFFER_SIZE) {
Pawel Zarembski 0:01f31e923fe2 291
Pawel Zarembski 0:01f31e923fe2 292 NVIC_DisableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 293 write_buffer.data[write_buffer.idx_in++] = *data++;
Pawel Zarembski 0:01f31e923fe2 294 write_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 295 write_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 296 xfer_count--;
Pawel Zarembski 0:01f31e923fe2 297 NVIC_EnableIRQ(CdcAcmUartIrqNumber);
Pawel Zarembski 0:01f31e923fe2 298
Pawel Zarembski 0:01f31e923fe2 299 } else {
Pawel Zarembski 0:01f31e923fe2 300 break;
Pawel Zarembski 0:01f31e923fe2 301 }
Pawel Zarembski 0:01f31e923fe2 302 }
Pawel Zarembski 0:01f31e923fe2 303 return size - xfer_count;
Pawel Zarembski 0:01f31e923fe2 304 }
Pawel Zarembski 0:01f31e923fe2 305
Pawel Zarembski 0:01f31e923fe2 306 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 307 int32_t uart_read_data(uint8_t *data, uint16_t size)
Pawel Zarembski 0:01f31e923fe2 308 {
Pawel Zarembski 0:01f31e923fe2 309 int32_t cnt;
Pawel Zarembski 0:01f31e923fe2 310
Pawel Zarembski 0:01f31e923fe2 311 for (cnt = 0; (cnt < size) && (read_buffer.cnt_in != read_buffer.cnt_out); cnt++) {
Pawel Zarembski 0:01f31e923fe2 312 *data++ = read_buffer.data[read_buffer.idx_out++];
Pawel Zarembski 0:01f31e923fe2 313 read_buffer.idx_out &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 314 read_buffer.cnt_out++;
Pawel Zarembski 0:01f31e923fe2 315 }
Pawel Zarembski 0:01f31e923fe2 316
Pawel Zarembski 0:01f31e923fe2 317 return cnt;
Pawel Zarembski 0:01f31e923fe2 318 }
Pawel Zarembski 0:01f31e923fe2 319
Pawel Zarembski 0:01f31e923fe2 320 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 321 void UART_IRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 322 {
Pawel Zarembski 0:01f31e923fe2 323 // Capture interrupt flag state at entry
Pawel Zarembski 0:01f31e923fe2 324 uint32_t intfl = CdcAcmUart->intfl;
Pawel Zarembski 0:01f31e923fe2 325 // Clear interrupts that will be serviced
Pawel Zarembski 0:01f31e923fe2 326 CdcAcmUart->intfl = intfl;
Pawel Zarembski 0:01f31e923fe2 327
Pawel Zarembski 0:01f31e923fe2 328 if (intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
Pawel Zarembski 0:01f31e923fe2 329 read_buffer.data[read_buffer.idx_in++] = '*';
Pawel Zarembski 0:01f31e923fe2 330 read_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 331 read_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 332 }
Pawel Zarembski 0:01f31e923fe2 333
Pawel Zarembski 0:01f31e923fe2 334 if (intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
Pawel Zarembski 0:01f31e923fe2 335 while ((CdcAcmUart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) &&
Pawel Zarembski 0:01f31e923fe2 336 ((read_buffer.cnt_in - read_buffer.cnt_out) < BUFFER_SIZE)) {
Pawel Zarembski 0:01f31e923fe2 337 read_buffer.data[read_buffer.idx_in++] = CdcAcmUartFifo->rx;
Pawel Zarembski 0:01f31e923fe2 338 CdcAcmUart->intfl = MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY;
Pawel Zarembski 0:01f31e923fe2 339 read_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 340 read_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 341 }
Pawel Zarembski 0:01f31e923fe2 342 if (((read_buffer.cnt_in - read_buffer.cnt_out) >= BUFFER_SIZE)) {
Pawel Zarembski 0:01f31e923fe2 343 read_buffer.data[read_buffer.idx_in++] = '%';
Pawel Zarembski 0:01f31e923fe2 344 read_buffer.idx_in &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 345 read_buffer.cnt_in++;
Pawel Zarembski 0:01f31e923fe2 346 }
Pawel Zarembski 0:01f31e923fe2 347 }
Pawel Zarembski 0:01f31e923fe2 348
Pawel Zarembski 0:01f31e923fe2 349 if (intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
Pawel Zarembski 0:01f31e923fe2 350 /*
Pawel Zarembski 0:01f31e923fe2 351 Transfer data from write buffer to transmit FIFO if
Pawel Zarembski 0:01f31e923fe2 352 a) write buffer contains data and
Pawel Zarembski 0:01f31e923fe2 353 b) transmit FIFO is not full
Pawel Zarembski 0:01f31e923fe2 354 */
Pawel Zarembski 0:01f31e923fe2 355 while ((write_buffer.cnt_out != write_buffer.cnt_in) &&
Pawel Zarembski 0:01f31e923fe2 356 (((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH)) {
Pawel Zarembski 0:01f31e923fe2 357 CdcAcmUartFifo->tx = write_buffer.data[write_buffer.idx_out++];
Pawel Zarembski 0:01f31e923fe2 358 write_buffer.idx_out &= (BUFFER_SIZE - 1);
Pawel Zarembski 0:01f31e923fe2 359 write_buffer.cnt_out++;
Pawel Zarembski 0:01f31e923fe2 360 }
Pawel Zarembski 0:01f31e923fe2 361 }
Pawel Zarembski 0:01f31e923fe2 362 }
Pawel Zarembski 0:01f31e923fe2 363
Pawel Zarembski 0:01f31e923fe2 364 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 365 void UART0_IRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 366 {
Pawel Zarembski 0:01f31e923fe2 367 UART_IRQHandler();
Pawel Zarembski 0:01f31e923fe2 368 }
Pawel Zarembski 0:01f31e923fe2 369
Pawel Zarembski 0:01f31e923fe2 370 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 371 void UART1_IRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 372 {
Pawel Zarembski 0:01f31e923fe2 373 UART_IRQHandler();
Pawel Zarembski 0:01f31e923fe2 374 }
Pawel Zarembski 0:01f31e923fe2 375
Pawel Zarembski 0:01f31e923fe2 376 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 377 void UART2_IRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 378 {
Pawel Zarembski 0:01f31e923fe2 379 UART_IRQHandler();
Pawel Zarembski 0:01f31e923fe2 380 }