Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/tmr_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* ***************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | *************************************************************************** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /* Define to prevent redundant inclusion */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | #ifndef _MXC_TMR_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | #define _MXC_TMR_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | /* **** Includes **** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #include <stdint.h> |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #ifdef __cplusplus |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | extern "C" { |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | ///@cond |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | If types are not defined elsewhere (CMSIS) define them here |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | #ifndef __IO |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | #define __IO volatile |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | #ifndef __I |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | #define __I volatile const |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | #ifndef __O |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define __O volatile |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | #ifndef __R |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | #define __R volatile const |
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0:01f31e923fe2 | 60 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | ///@endcond |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | * @defgroup tmr_registers Timer Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | * @ingroup tmr |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | * @brief Hardware interface definitions for the Timer Peripheral. |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | * @details Definitions for the Hardware Access Layer of the Timer |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | * Peripherals. Includes: |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | * - Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | * - Fields |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | * - Positions |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | * - Values |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | * - Masks |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | /* **** Definitions **** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | * Structure type to access the Timer Registers, see #MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure. |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | __IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> - TMR_CTRL Register - Timer Control Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | __IO uint32_t count32; /**< <tt>\b 0x0004</tt> - TMR_COUNT32 Register - Timer [32 bit] Current Count Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | __IO uint32_t term_cnt32; /**< <tt>\b 0x0008</tt> - TMR_TERM_CNT32 Register - Timer [32 bit] Terminal Count Setting */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | __IO uint32_t pwm_cap32; /**< <tt>\b 0x000C</tt> - TMR_PWM_CAP32 Register - Timer [32 bit] PWM Compare Setting or Capture/Measure Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | __IO uint32_t count16_0; /**< <tt>\b 0x0010</tt> - TMR_COUNT16_0 Register - Timer [16 bit] Current Count Value, 16-bit Timer 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | __IO uint32_t term_cnt16_0; /**< <tt>\b 0x0014</tt> - TMR_TERM_CNT16_0 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | __IO uint32_t count16_1; /**< <tt>\b 0x0018</tt> - TMR_COUNT16_1 Register - Timer [16 bit] Current Count Value, 16-bit Timer 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | __IO uint32_t term_cnt16_1; /**< <tt>\b 0x001C</tt> - TMR_TERM_CNT16_1 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | __IO uint32_t intfl; /**< <tt>\b 0x0020</tt> - TMR_INTFL Register - Timer Interrupt Flags */ |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | __IO uint32_t inten; /**< <tt>\b 0x0024</tt> - TMR_INTEN Register - Timer Interrupt Enable/Disable Settings */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | } mxc_tmr_regs_t; |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | /**@} end of group tmr_registers. */ |
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0:01f31e923fe2 | 95 | |
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0:01f31e923fe2 | 96 | |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | Register offsets for module TMR. |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | * @defgroup TMR_Register_Offsets Register Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | * @ingroup tmr_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | * @brief Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_TMR_INSTANCES for the \MXIM_Device. Use #MXC_TMR_GET_BASE(i) to get the base address for a specific timer number. |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | #define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from TMR[n] Base Address: TMR_CTRL : <tt>\b 0x0x0000 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | #define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) /**< Offset from TMR[n] Base Address: TMR_COUNT32 : <tt>\b 0x0x0004 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | #define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT32 : <tt>\b 0x0x0008 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) /**< Offset from TMR[n] Base Address: TMR_PWM_CAP32 : <tt>\b 0x0x000C </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_0 : <tt>\b 0x0x0010 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_0 : <tt>\b 0x0x0014 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_1 : <tt>\b 0x0x0018 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_1 : <tt>\b 0x0x001C </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) /**< Offset from TMR[n] Base Address: TMR_INTFL : <tt>\b 0x0x0020 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) /**< Offset from TMR[n] Base Address: TMR_INTEN : <tt>\b 0x0x0024 </tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | /**@} end of group TMR_Register_Offsets */ |
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0:01f31e923fe2 | 117 | |
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0:01f31e923fe2 | 118 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | * @defgroup TMR_CTRL_Register TMR_CTRL Register |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | * @ingroup tmr_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | * @brief Field Positions and Bit Masks for the TMR_CTRL register |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define MXC_F_TMR_CTRL_MODE_POS 0 /**< MODE Field Position for 32-bit timer if TMR2X16 Field is 0 (Default) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | #define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) /**< MODE Field Shifted Position for 32-bit timer if TMR2X16 Field is 0 (Default) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | #define MXC_F_TMR_CTRL_TMR2X16_POS 3 /**< TMR2X16 Field Position */ |
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0:01f31e923fe2 | 127 | #define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) /**< TMR2X16 Field Shifted Position */ |
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0:01f31e923fe2 | 128 | #define MXC_F_TMR_CTRL_PRESCALE_POS 4 /**< PRESCALE Field Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | #define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< PRESCALE Field Shifted Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | #define MXC_F_TMR_CTRL_POLARITY_POS 8 /**< POLARITY Field Position */ |
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0:01f31e923fe2 | 131 | #define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) /**< POLARITY Field Shifted Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define MXC_F_TMR_CTRL_ENABLE0_POS 12 /**< ENABLE0 Field Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) /**< ENABLE0 Field Shifted Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define MXC_F_TMR_CTRL_ENABLE1_POS 13 /**< ENABLE1 Field Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | #define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) /**< ENABLE1 Field Shifted Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | /**@} end of group TMR_CTRL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | |
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0:01f31e923fe2 | 138 | /** |
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0:01f31e923fe2 | 139 | * @defgroup TMR_COUNT16_0_Register TMR_COUNT16_0 Register |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | * @ingroup tmr_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | * @brief Field Positions and Bit Masks for the TMR_COUNT16_0 register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance. |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define MXC_F_TMR_COUNT16_0_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | /**@} end of group TMR_COUNT16_0 */ |
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0:01f31e923fe2 | 147 | |
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0:01f31e923fe2 | 148 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | * @defgroup TMR_TERM_CNT16_0_Register TMR_TERM_CNT16_0 Register |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | * @ingroup tmr_registers |
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0:01f31e923fe2 | 151 | * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. This field indicates the termination count value for the <b> 16-bit Timer 0 </b> instance if the Timer is set to 2 16-bit Timers. |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | * @{ |
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0:01f31e923fe2 | 153 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | /**@} end of group TMR_TERM_CNT16_0 */ |
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0:01f31e923fe2 | 157 | |
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0:01f31e923fe2 | 158 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | * @defgroup TMR_COUNT16_1__Register _TMR_COUNT16_1_ Register |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | * @ingroup tmr_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | * @brief Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance. |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define MXC_F_TMR_COUNT16_1_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | /**@} end of group TMR_COUNT16_1 */ |
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0:01f31e923fe2 | 167 | |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | * @defgroup TMR_TERM_CNT16_1_Register TMR_TERM_CNT16_1 Register |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | * @ingroup tmr_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. This field indicates the termination count value for the <b> 16-bit Timer 1 </b> instance if the Timer is set to 2 16-bit Timers. |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | */ |
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0:01f31e923fe2 | 174 | #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
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0:01f31e923fe2 | 175 | #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */ |
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0:01f31e923fe2 | 176 | /**@} end of group TMR_TERM_CNT16_1 */ |
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0:01f31e923fe2 | 177 | |
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0:01f31e923fe2 | 178 | /** |
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0:01f31e923fe2 | 179 | * @defgroup TMR_INTFL_Register TMR_INTFL Register |
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0:01f31e923fe2 | 180 | * @ingroup tmr_registers |
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0:01f31e923fe2 | 181 | * @brief Field Positions and Bit Masks for the TMR_INTFL register. This register includes the interrupt flags for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>. |
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0:01f31e923fe2 | 182 | * @{ |
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0:01f31e923fe2 | 183 | */ |
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0:01f31e923fe2 | 184 | #define MXC_F_TMR_INTFL_TIMER0_POS 0 /**< TIMER0 Interrupt Flag Field Position */ |
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0:01f31e923fe2 | 185 | #define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) /**< TIMER0 Interrupt Flag Shifted Field */ |
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0:01f31e923fe2 | 186 | #define MXC_F_TMR_INTFL_TIMER1_POS 1 /**< TIMER1 Interrupt Flag Field Position */ |
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0:01f31e923fe2 | 187 | #define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) /**< TIMER1 Interrupt Flag Shifted Field */ |
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0:01f31e923fe2 | 188 | /**@} end of group TMR_INTFL */ |
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0:01f31e923fe2 | 189 | |
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0:01f31e923fe2 | 190 | /** |
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0:01f31e923fe2 | 191 | * @defgroup TMR_INTEN_Register TMR_INTEN Register |
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0:01f31e923fe2 | 192 | * @ingroup tmr_registers |
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0:01f31e923fe2 | 193 | * @brief Field Positions and Bit Masks for the TMR_INTEN register. This register includes the interrupt enable bits for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>. |
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0:01f31e923fe2 | 194 | * @{ |
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0:01f31e923fe2 | 195 | */ |
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0:01f31e923fe2 | 196 | #define MXC_F_TMR_INTEN_TIMER0_POS 0 /**< TIMER0 Interrupt Enable Field Position */ |
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0:01f31e923fe2 | 197 | #define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) /**< TIMER0 Interrupt Enable Shifted Field */ |
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0:01f31e923fe2 | 198 | #define MXC_F_TMR_INTEN_TIMER1_POS 1 /**< TIMER1 Interrupt Enable Field Position */ |
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0:01f31e923fe2 | 199 | #define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) /**< TIMER1 Interrupt Enable Shifted Field */ |
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0:01f31e923fe2 | 200 | /**@} end of group TMR_INTEN */ |
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0:01f31e923fe2 | 201 | |
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0:01f31e923fe2 | 202 | |
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0:01f31e923fe2 | 203 | |
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0:01f31e923fe2 | 204 | /* |
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0:01f31e923fe2 | 205 | Field values and shifted values for module TMR. |
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0:01f31e923fe2 | 206 | */ |
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0:01f31e923fe2 | 207 | /** |
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0:01f31e923fe2 | 208 | * @defgroup TMR_CTRL_field_values TMR_CTRL Field and Shifted Field Values |
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0:01f31e923fe2 | 209 | * @ingroup TMR_CTRL_Register |
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0:01f31e923fe2 | 210 | * @brief Field values and Shifted Field values for the TMR_CTRL register. Shifted field values are field values shifted to the loacation of the field in the register. |
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0:01f31e923fe2 | 211 | */ |
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0:01f31e923fe2 | 212 | /** |
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0:01f31e923fe2 | 213 | * @defgroup TMR_CTRL_MODE_Field Mode Field for 32-bit Timer Operation. |
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0:01f31e923fe2 | 214 | * @ingroup TMR_CTRL_field_values |
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0:01f31e923fe2 | 215 | * @brief This field is used to select the timer mode for a 32-bit timer. |
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0:01f31e923fe2 | 216 | * @details The mode field is used to set the 32-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc. |
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0:01f31e923fe2 | 217 | * @note If the 32-bit timer is set to operate as 2 16-bit timers, see @ref TMR_CTRL_MODE_16_Field. |
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0:01f31e923fe2 | 218 | * @{ |
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0:01f31e923fe2 | 219 | */ |
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0:01f31e923fe2 | 220 | #define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) /**< Field value to set a 32-bit Timer to 1-Shot Timer mode. */ |
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0:01f31e923fe2 | 221 | #define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) /**< Field value to set a 32-bit Timer to continuous mode. */ |
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0:01f31e923fe2 | 222 | #define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) /**< Field value to set a 32-bit Timer to counter mode. */ |
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0:01f31e923fe2 | 223 | #define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) /**< Field value to set a 32-bit Timer to pulse-width mode. */ |
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0:01f31e923fe2 | 224 | #define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) /**< Field value to set a 32-bit Timer to capture mode. */ |
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0:01f31e923fe2 | 225 | #define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) /**< Field value to set a 32-bit Timer to compare mode. */ |
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0:01f31e923fe2 | 226 | #define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) /**< Field value to set a 32-bit Timer to gated mode. */ |
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0:01f31e923fe2 | 227 | #define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) /**< Field value to set a 32-bit Timer to measurement mode. */ |
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0:01f31e923fe2 | 228 | |
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0:01f31e923fe2 | 229 | #define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to 1-Shot Timer mode. */ |
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0:01f31e923fe2 | 230 | #define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to continuous mode. */ |
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0:01f31e923fe2 | 231 | #define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to counter mode. */ |
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0:01f31e923fe2 | 232 | #define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to pulse-width mode. */ |
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0:01f31e923fe2 | 233 | #define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to capture mode. */ |
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0:01f31e923fe2 | 234 | #define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to compare mode. */ |
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0:01f31e923fe2 | 235 | #define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to gated mode. */ |
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0:01f31e923fe2 | 236 | #define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to measurement mode. */ |
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0:01f31e923fe2 | 237 | /**@} end of group TMR_CTRL_MODE_Field */ |
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0:01f31e923fe2 | 238 | /** |
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0:01f31e923fe2 | 239 | * @defgroup TMR_CTRL_MODE_16_Field 16-bit Timer Mode Field and Shifted Field Values. |
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0:01f31e923fe2 | 240 | * @ingroup TMR_CTRL_field_values |
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0:01f31e923fe2 | 241 | * @brief This field is used to select the timer mode when the timer is set to a dual 16-bit timer. The mode field is used to set the 16-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc. |
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0:01f31e923fe2 | 242 | * @{ |
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0:01f31e923fe2 | 243 | */ |
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0:01f31e923fe2 | 244 | #define MXC_F_TMR_CTRL_MODE_16_0_POS 0 |
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0:01f31e923fe2 | 245 | #define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS)) |
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0:01f31e923fe2 | 246 | |
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0:01f31e923fe2 | 247 | #define MXC_F_TMR_CTRL_MODE_16_1_POS 1 |
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0:01f31e923fe2 | 248 | #define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS)) |
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0:01f31e923fe2 | 249 | /**@} end of group TMR_CTRL_MODE_16_Field */ |
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0:01f31e923fe2 | 250 | |
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0:01f31e923fe2 | 251 | /** |
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0:01f31e923fe2 | 252 | * @defgroup TMR_CTRL_PRESCALE_Field Prescale Divide Selection Field and Shifted Field Values. |
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0:01f31e923fe2 | 253 | * @ingroup TMR_CTRL_field_values |
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0:01f31e923fe2 | 254 | * @brief Timer Clock Prescaler divide values and shifted values. The Prescale Divide field is used to scale the timer instance peripheral clock by the specified value. |
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0:01f31e923fe2 | 255 | * @{ |
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0:01f31e923fe2 | 256 | */ |
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0:01f31e923fe2 | 257 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */ |
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0:01f31e923fe2 | 258 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */ |
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0:01f31e923fe2 | 259 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */ |
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0:01f31e923fe2 | 260 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */ |
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0:01f31e923fe2 | 261 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16\f$ */ |
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0:01f31e923fe2 | 262 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */ |
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0:01f31e923fe2 | 263 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */ |
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0:01f31e923fe2 | 264 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */ |
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0:01f31e923fe2 | 265 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */ |
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0:01f31e923fe2 | 266 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */ |
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0:01f31e923fe2 | 267 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */ |
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0:01f31e923fe2 | 268 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */ |
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0:01f31e923fe2 | 269 | #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */ |
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0:01f31e923fe2 | 270 | |
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0:01f31e923fe2 | 271 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */ |
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0:01f31e923fe2 | 272 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */ |
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0:01f31e923fe2 | 273 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */ |
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0:01f31e923fe2 | 274 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */ |
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0:01f31e923fe2 | 275 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16 \f$ */ |
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0:01f31e923fe2 | 276 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */ |
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0:01f31e923fe2 | 277 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */ |
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0:01f31e923fe2 | 278 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */ |
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0:01f31e923fe2 | 279 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */ |
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0:01f31e923fe2 | 280 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */ |
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0:01f31e923fe2 | 281 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */ |
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0:01f31e923fe2 | 282 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */ |
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0:01f31e923fe2 | 283 | #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */ |
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0:01f31e923fe2 | 284 | /**@} end of group TMR_CTRL_PRESCALE_Field */ |
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0:01f31e923fe2 | 285 | |
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0:01f31e923fe2 | 286 | |
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0:01f31e923fe2 | 287 | /* |
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0:01f31e923fe2 | 288 | * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module |
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0:01f31e923fe2 | 289 | * is in dual 16-bit timer mode. |
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0:01f31e923fe2 | 290 | */ |
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0:01f31e923fe2 | 291 | |
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0:01f31e923fe2 | 292 | #ifdef __cplusplus |
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0:01f31e923fe2 | 293 | } |
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0:01f31e923fe2 | 294 | #endif |
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0:01f31e923fe2 | 295 | |
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0:01f31e923fe2 | 296 | #endif /* _MXC_TMR_REGS_H_ */ |