Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/rtc_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* **************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | **************************************************************************** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /* Define to prevent redundant inclusion */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | #ifndef _MXC_RTC_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | #define _MXC_RTC_REGS_H_ |
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0:01f31e923fe2 | 37 | |
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0:01f31e923fe2 | 38 | /* **** Includes **** */ |
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0:01f31e923fe2 | 39 | #include <stdint.h> |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #ifdef __cplusplus |
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0:01f31e923fe2 | 42 | extern "C" { |
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0:01f31e923fe2 | 43 | #endif |
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0:01f31e923fe2 | 44 | |
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0:01f31e923fe2 | 45 | /* |
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0:01f31e923fe2 | 46 | If types are not defined elsewhere (CMSIS) define them here |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | */ |
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0:01f31e923fe2 | 48 | /// @cond |
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0:01f31e923fe2 | 49 | #ifndef __IO |
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0:01f31e923fe2 | 50 | #define __IO volatile |
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0:01f31e923fe2 | 51 | #endif |
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0:01f31e923fe2 | 52 | #ifndef __I |
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0:01f31e923fe2 | 53 | #define __I volatile const |
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0:01f31e923fe2 | 54 | #endif |
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0:01f31e923fe2 | 55 | #ifndef __O |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define __O volatile |
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0:01f31e923fe2 | 57 | #endif |
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0:01f31e923fe2 | 58 | #ifndef __R |
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0:01f31e923fe2 | 59 | #define __R volatile const |
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0:01f31e923fe2 | 60 | #endif |
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0:01f31e923fe2 | 61 | /// @endcond |
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0:01f31e923fe2 | 62 | |
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0:01f31e923fe2 | 63 | /** |
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0:01f31e923fe2 | 64 | * @defgroup rtc_registers RTC Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | * @brief Registers, Bit Masks and Bit Positions |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | * @ingroup rtc |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | * @{ |
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0:01f31e923fe2 | 68 | */ |
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0:01f31e923fe2 | 69 | |
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0:01f31e923fe2 | 70 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | * Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register. |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | */ |
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0:01f31e923fe2 | 73 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | __IO uint32_t ctrl; /**< <tt>\b 0x0000: </tt> RTC_CTRL Register - RTC Timer Control */ |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | __IO uint32_t timer; /**< <tt>\b 0x0004: </tt> RTC_TIMER Register - RTC Timer Count Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | __IO uint32_t comp[2]; /**< <tt>\b 0x0008-0x000C: </tt> RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | __IO uint32_t flags; /**< <tt>\b 0x0010: </tt> RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */ |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | __IO uint32_t snz_val; /**< <tt>\b 0x0014: </tt> RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | __IO uint32_t inten; /**< <tt>\b 0x0018: </tt> RTC_INTEN Register - Interrupt Enable Controls */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | __IO uint32_t prescale; /**< <tt>\b 0x001C: </tt> RTC_PRESCALE Register - RTC Timer Prescale Setting */ |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | __R uint32_t rsv020; /**< <tt>\b 0x0020: </tt> RESERVED */ |
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0:01f31e923fe2 | 82 | __IO uint32_t prescale_mask; /**< <tt>\b 0x0024: </tt> RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | __IO uint32_t trim_ctrl; /**< <tt>\b 0x0028: </tt> RTC_TRIM_CTRL Register - RTC Timer Trim Controls */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | __IO uint32_t trim_value; /**< <tt>\b 0x002C: </tt> RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */ |
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0:01f31e923fe2 | 85 | } mxc_rtctmr_regs_t; |
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0:01f31e923fe2 | 86 | |
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0:01f31e923fe2 | 87 | |
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0:01f31e923fe2 | 88 | /** |
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0:01f31e923fe2 | 89 | * Structure type for access to the RTC CFG hardware. |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | */ |
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0:01f31e923fe2 | 91 | typedef struct { |
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0:01f31e923fe2 | 92 | __IO uint32_t nano_cntr; /**< <tt>\b 0x0000: </tt> - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> - RTCCFG_CLK_CTRL - RTC Clock Control Settings */ |
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0:01f31e923fe2 | 94 | __R uint32_t rsv008; /**< <tt>\b 0x0008: </tt> - RESERVED */ |
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0:01f31e923fe2 | 95 | __IO uint32_t osc_ctrl; /**< <tt>\b 0x000C: </tt> - RTCCFG_OSC_CTRL - RTC Oscillator Control */ |
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0:01f31e923fe2 | 96 | } mxc_rtccfg_regs_t; |
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0:01f31e923fe2 | 97 | /**@} end of group rtc_registers.*/ |
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0:01f31e923fe2 | 98 | |
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0:01f31e923fe2 | 99 | /* |
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0:01f31e923fe2 | 100 | Register offsets for module RTC. |
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0:01f31e923fe2 | 101 | */ |
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0:01f31e923fe2 | 102 | /** |
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0:01f31e923fe2 | 103 | * @defgroup RTC_Register_Offsets Register Offsets |
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0:01f31e923fe2 | 104 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 105 | * @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | * @{ |
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0:01f31e923fe2 | 107 | */ |
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0:01f31e923fe2 | 108 | #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0008</tt> */ |
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0:01f31e923fe2 | 111 | #define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0010</tt> */ |
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0:01f31e923fe2 | 113 | #define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0014</tt> */ |
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0:01f31e923fe2 | 114 | #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0018</tt> */ |
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0:01f31e923fe2 | 115 | #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x001C</tt> */ |
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0:01f31e923fe2 | 116 | #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0024</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0028</tt> */ |
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0:01f31e923fe2 | 118 | #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x002C</tt> */ |
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0:01f31e923fe2 | 119 | /**@} end of group RTC_Register_Offsets */ |
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0:01f31e923fe2 | 120 | /** |
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0:01f31e923fe2 | 121 | * @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 123 | * @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address. |
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0:01f31e923fe2 | 124 | * @{ |
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0:01f31e923fe2 | 125 | */ |
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0:01f31e923fe2 | 126 | #define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */ |
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0:01f31e923fe2 | 127 | #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */ |
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0:01f31e923fe2 | 128 | #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */ |
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0:01f31e923fe2 | 129 | /**@} end of group RTCCFG_Register_Offsets */ |
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0:01f31e923fe2 | 130 | |
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0:01f31e923fe2 | 131 | /* |
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0:01f31e923fe2 | 132 | Field positions and masks for module RTC. |
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0:01f31e923fe2 | 133 | */ |
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0:01f31e923fe2 | 134 | /** |
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0:01f31e923fe2 | 135 | * @defgroup RTC_CTRL_Register RTC_CTRL |
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0:01f31e923fe2 | 136 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 137 | * @{ |
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0:01f31e923fe2 | 138 | */ |
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0:01f31e923fe2 | 139 | #define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */ |
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0:01f31e923fe2 | 140 | #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */ |
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0:01f31e923fe2 | 141 | #define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */ |
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0:01f31e923fe2 | 142 | #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */ |
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0:01f31e923fe2 | 143 | #define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */ |
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0:01f31e923fe2 | 144 | #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */ |
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0:01f31e923fe2 | 145 | #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */ |
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0:01f31e923fe2 | 146 | #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */ |
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0:01f31e923fe2 | 147 | #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */ |
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0:01f31e923fe2 | 148 | #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */ |
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0:01f31e923fe2 | 149 | #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */ |
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0:01f31e923fe2 | 150 | #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */ |
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0:01f31e923fe2 | 151 | #define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */ |
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0:01f31e923fe2 | 152 | #define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */ |
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0:01f31e923fe2 | 153 | #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */ |
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0:01f31e923fe2 | 154 | #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */ |
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0:01f31e923fe2 | 155 | #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */ |
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0:01f31e923fe2 | 156 | #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */ |
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0:01f31e923fe2 | 157 | #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */ |
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0:01f31e923fe2 | 158 | #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */ |
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0:01f31e923fe2 | 159 | #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */ |
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0:01f31e923fe2 | 160 | #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */ |
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0:01f31e923fe2 | 161 | #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */ |
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0:01f31e923fe2 | 162 | #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */ |
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0:01f31e923fe2 | 163 | #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */ |
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0:01f31e923fe2 | 164 | #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */ |
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0:01f31e923fe2 | 165 | #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */ |
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0:01f31e923fe2 | 166 | #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */ |
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0:01f31e923fe2 | 167 | #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */ |
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0:01f31e923fe2 | 168 | #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */ |
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0:01f31e923fe2 | 169 | #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */ |
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0:01f31e923fe2 | 170 | #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */ |
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0:01f31e923fe2 | 171 | #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */ |
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0:01f31e923fe2 | 172 | #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */ |
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0:01f31e923fe2 | 173 | #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */ |
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0:01f31e923fe2 | 174 | #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */ |
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0:01f31e923fe2 | 175 | #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */ |
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0:01f31e923fe2 | 176 | #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */ |
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0:01f31e923fe2 | 177 | #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */ |
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0:01f31e923fe2 | 178 | #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */ |
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0:01f31e923fe2 | 179 | #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */ |
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0:01f31e923fe2 | 180 | #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */ |
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0:01f31e923fe2 | 181 | #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */ |
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0:01f31e923fe2 | 182 | #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */ |
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0:01f31e923fe2 | 183 | /**@} end of group RTC_CTRL*/ |
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0:01f31e923fe2 | 184 | /** |
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0:01f31e923fe2 | 185 | * @defgroup RTC_FLAGS_Register RTC_FLAGS |
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0:01f31e923fe2 | 186 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 187 | * @{ |
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0:01f31e923fe2 | 188 | */ |
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0:01f31e923fe2 | 189 | #define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */ |
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0:01f31e923fe2 | 190 | #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */ |
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0:01f31e923fe2 | 191 | #define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */ |
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0:01f31e923fe2 | 192 | #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */ |
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0:01f31e923fe2 | 193 | #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */ |
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0:01f31e923fe2 | 194 | #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */ |
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0:01f31e923fe2 | 195 | #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */ |
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0:01f31e923fe2 | 196 | #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */ |
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0:01f31e923fe2 | 197 | #define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */ |
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0:01f31e923fe2 | 198 | #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */ |
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0:01f31e923fe2 | 199 | #define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */ |
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0:01f31e923fe2 | 200 | #define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */ |
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0:01f31e923fe2 | 201 | #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */ |
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0:01f31e923fe2 | 202 | #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */ |
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0:01f31e923fe2 | 203 | #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */ |
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0:01f31e923fe2 | 204 | #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */ |
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0:01f31e923fe2 | 205 | #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */ |
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0:01f31e923fe2 | 206 | #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */ |
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0:01f31e923fe2 | 207 | #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */ |
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0:01f31e923fe2 | 208 | #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */ |
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0:01f31e923fe2 | 209 | #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */ |
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0:01f31e923fe2 | 210 | #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */ |
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0:01f31e923fe2 | 211 | #define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */ |
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0:01f31e923fe2 | 212 | #define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */ |
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0:01f31e923fe2 | 213 | #define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */ |
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0:01f31e923fe2 | 214 | #define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */ |
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0:01f31e923fe2 | 215 | #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */ |
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0:01f31e923fe2 | 216 | #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */ |
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0:01f31e923fe2 | 217 | /**@} end of group RTC_FLAGS_Register */ |
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0:01f31e923fe2 | 218 | /** |
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0:01f31e923fe2 | 219 | * @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL. |
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0:01f31e923fe2 | 220 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 221 | * @{ |
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0:01f31e923fe2 | 222 | */ |
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0:01f31e923fe2 | 223 | #define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */ |
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0:01f31e923fe2 | 224 | #define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */ |
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0:01f31e923fe2 | 225 | /**@} end of group RTC_SNZ_VAL_Register */ |
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0:01f31e923fe2 | 226 | /** |
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0:01f31e923fe2 | 227 | * @defgroup RTC_INTEN_Register RTC_INTEN. |
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0:01f31e923fe2 | 228 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 229 | * @{ |
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0:01f31e923fe2 | 230 | */ |
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0:01f31e923fe2 | 231 | #define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */ |
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0:01f31e923fe2 | 232 | #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */ |
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0:01f31e923fe2 | 233 | #define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */ |
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0:01f31e923fe2 | 234 | #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */ |
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0:01f31e923fe2 | 235 | #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */ |
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0:01f31e923fe2 | 236 | #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */ |
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0:01f31e923fe2 | 237 | #define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */ |
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0:01f31e923fe2 | 238 | #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */ |
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0:01f31e923fe2 | 239 | #define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */ |
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0:01f31e923fe2 | 240 | #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */ |
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0:01f31e923fe2 | 241 | /**@} end of group RTC_INTEN_Register */ |
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0:01f31e923fe2 | 242 | /** |
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0:01f31e923fe2 | 243 | * @defgroup RTC_PRESCALE_Register RTC_PRESCALE. |
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0:01f31e923fe2 | 244 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 245 | * @{ |
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0:01f31e923fe2 | 246 | */ |
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0:01f31e923fe2 | 247 | #define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */ |
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0:01f31e923fe2 | 248 | #define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */ |
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0:01f31e923fe2 | 249 | /**@} end of group RTC_INTEN_Register */ |
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0:01f31e923fe2 | 250 | /** |
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0:01f31e923fe2 | 251 | * @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK. |
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0:01f31e923fe2 | 252 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 253 | * @{ |
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0:01f31e923fe2 | 254 | */ |
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0:01f31e923fe2 | 255 | #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */ |
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0:01f31e923fe2 | 256 | #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */ |
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0:01f31e923fe2 | 257 | /**@} end of group RTC_PRESCALE_MASK_Register */ |
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0:01f31e923fe2 | 258 | /** |
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0:01f31e923fe2 | 259 | * @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL. |
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0:01f31e923fe2 | 260 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 261 | * @{ |
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0:01f31e923fe2 | 262 | */ |
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0:01f31e923fe2 | 263 | #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */ |
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0:01f31e923fe2 | 264 | #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */ |
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0:01f31e923fe2 | 265 | #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */ |
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0:01f31e923fe2 | 266 | #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */ |
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0:01f31e923fe2 | 267 | #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */ |
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0:01f31e923fe2 | 268 | #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */ |
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0:01f31e923fe2 | 269 | /**@} end of group RTC_TRIM_CTRL_Register */ |
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0:01f31e923fe2 | 270 | /** |
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0:01f31e923fe2 | 271 | * @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE. |
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0:01f31e923fe2 | 272 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 273 | * @{ |
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0:01f31e923fe2 | 274 | */ |
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0:01f31e923fe2 | 275 | #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */ |
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0:01f31e923fe2 | 276 | #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */ |
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0:01f31e923fe2 | 277 | #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */ |
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0:01f31e923fe2 | 278 | #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */ |
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0:01f31e923fe2 | 279 | /**@} end of group RTC_TRIM_VALUE_Register */ |
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0:01f31e923fe2 | 280 | /** |
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0:01f31e923fe2 | 281 | * @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR. |
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0:01f31e923fe2 | 282 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 283 | * @{ |
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0:01f31e923fe2 | 284 | */ |
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0:01f31e923fe2 | 285 | #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */ |
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0:01f31e923fe2 | 286 | #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */ |
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0:01f31e923fe2 | 287 | /**@} end of group RTC_NANO_CNTR_Register */ |
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0:01f31e923fe2 | 288 | /** |
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0:01f31e923fe2 | 289 | * @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL. |
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0:01f31e923fe2 | 290 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 291 | * @{ |
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0:01f31e923fe2 | 292 | */ |
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0:01f31e923fe2 | 293 | #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */ |
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0:01f31e923fe2 | 294 | #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */ |
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0:01f31e923fe2 | 295 | #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */ |
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0:01f31e923fe2 | 296 | #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */ |
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0:01f31e923fe2 | 297 | #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */ |
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0:01f31e923fe2 | 298 | #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */ |
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0:01f31e923fe2 | 299 | /**@} end of group RTC_CLK_CTRL_Register */ |
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0:01f31e923fe2 | 300 | /** |
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0:01f31e923fe2 | 301 | * @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL. |
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0:01f31e923fe2 | 302 | * @ingroup rtc_registers |
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0:01f31e923fe2 | 303 | * @{ |
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0:01f31e923fe2 | 304 | */ |
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0:01f31e923fe2 | 305 | #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */ |
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0:01f31e923fe2 | 306 | #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */ |
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0:01f31e923fe2 | 307 | #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */ |
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0:01f31e923fe2 | 308 | #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */ |
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0:01f31e923fe2 | 309 | #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */ |
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0:01f31e923fe2 | 310 | #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */ |
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0:01f31e923fe2 | 311 | #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */ |
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0:01f31e923fe2 | 312 | #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */ |
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0:01f31e923fe2 | 313 | #define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */ |
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0:01f31e923fe2 | 314 | #define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */ |
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0:01f31e923fe2 | 315 | /**@} end of group RTC_OSC_CTRL_Register */ |
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0:01f31e923fe2 | 316 | |
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0:01f31e923fe2 | 317 | /* |
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0:01f31e923fe2 | 318 | Field values |
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0:01f31e923fe2 | 319 | */ |
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0:01f31e923fe2 | 320 | /** |
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0:01f31e923fe2 | 321 | * @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values |
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0:01f31e923fe2 | 322 | * @ingroup RTC_CTRL_Register |
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0:01f31e923fe2 | 323 | * @{ |
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0:01f31e923fe2 | 324 | */ |
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0:01f31e923fe2 | 325 | #define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */ |
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0:01f31e923fe2 | 326 | #define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */ |
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0:01f31e923fe2 | 327 | #define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */ |
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0:01f31e923fe2 | 328 | /**@} end of group rtc_snz_mode_values */ |
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0:01f31e923fe2 | 329 | /** |
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0:01f31e923fe2 | 330 | * @defgroup rtc_prescale_values RTC Prescale Values |
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0:01f31e923fe2 | 331 | * @ingroup RTC_PRESCALE_Register |
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0:01f31e923fe2 | 332 | * @{ |
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0:01f31e923fe2 | 333 | */ |
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0:01f31e923fe2 | 334 | #define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/ |
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0:01f31e923fe2 | 335 | #define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/ |
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0:01f31e923fe2 | 336 | #define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/ |
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0:01f31e923fe2 | 337 | #define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/ |
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0:01f31e923fe2 | 338 | #define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/ |
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0:01f31e923fe2 | 339 | #define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/ |
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0:01f31e923fe2 | 340 | #define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/ |
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0:01f31e923fe2 | 341 | #define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/ |
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0:01f31e923fe2 | 342 | #define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/ |
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0:01f31e923fe2 | 343 | #define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/ |
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0:01f31e923fe2 | 344 | #define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/ |
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0:01f31e923fe2 | 345 | #define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/ |
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0:01f31e923fe2 | 346 | #define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/ |
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0:01f31e923fe2 | 347 | /**@} end of group rtc_prescale_values*/ |
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0:01f31e923fe2 | 348 | |
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0:01f31e923fe2 | 349 | #ifdef __cplusplus |
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0:01f31e923fe2 | 350 | } |
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0:01f31e923fe2 | 351 | #endif |
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0:01f31e923fe2 | 352 | |
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0:01f31e923fe2 | 353 | #endif /* _MXC_RTC_REGS_H_ */ |