Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/pwrseq_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /******************************************************************************* |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
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0:01f31e923fe2 | 32 | ******************************************************************************/ |
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0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | #ifndef _MXC_PWRSEQ_REGS_H_ |
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0:01f31e923fe2 | 35 | #define _MXC_PWRSEQ_REGS_H_ |
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0:01f31e923fe2 | 36 | |
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0:01f31e923fe2 | 37 | #ifdef __cplusplus |
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0:01f31e923fe2 | 38 | extern "C" { |
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0:01f31e923fe2 | 39 | #endif |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #include <stdint.h> |
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0:01f31e923fe2 | 42 | |
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0:01f31e923fe2 | 43 | /* |
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0:01f31e923fe2 | 44 | If types are not defined elsewhere (CMSIS) define them here |
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0:01f31e923fe2 | 45 | */ |
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0:01f31e923fe2 | 46 | #ifndef __IO |
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0:01f31e923fe2 | 47 | #define __IO volatile |
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0:01f31e923fe2 | 48 | #endif |
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0:01f31e923fe2 | 49 | #ifndef __I |
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0:01f31e923fe2 | 50 | #define __I volatile const |
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0:01f31e923fe2 | 51 | #endif |
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0:01f31e923fe2 | 52 | #ifndef __O |
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0:01f31e923fe2 | 53 | #define __O volatile |
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0:01f31e923fe2 | 54 | #endif |
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0:01f31e923fe2 | 55 | #ifndef __R |
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0:01f31e923fe2 | 56 | #define __R volatile const |
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0:01f31e923fe2 | 57 | #endif |
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0:01f31e923fe2 | 58 | |
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0:01f31e923fe2 | 59 | |
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0:01f31e923fe2 | 60 | /* |
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0:01f31e923fe2 | 61 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
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0:01f31e923fe2 | 62 | access to each register in module. |
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0:01f31e923fe2 | 63 | */ |
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0:01f31e923fe2 | 64 | |
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0:01f31e923fe2 | 65 | /* Offset Register Description |
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0:01f31e923fe2 | 66 | ============= ============================================================================ */ |
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0:01f31e923fe2 | 67 | typedef struct { |
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0:01f31e923fe2 | 68 | __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */ |
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0:01f31e923fe2 | 69 | __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */ |
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0:01f31e923fe2 | 70 | __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */ |
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0:01f31e923fe2 | 71 | __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */ |
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0:01f31e923fe2 | 72 | __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */ |
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0:01f31e923fe2 | 73 | __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */ |
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0:01f31e923fe2 | 74 | __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */ |
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0:01f31e923fe2 | 75 | __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */ |
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0:01f31e923fe2 | 76 | __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */ |
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0:01f31e923fe2 | 77 | __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */ |
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0:01f31e923fe2 | 78 | __R uint32_t rsv028; /* 0x0028 */ |
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0:01f31e923fe2 | 79 | __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */ |
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0:01f31e923fe2 | 80 | __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */ |
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0:01f31e923fe2 | 81 | __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */ |
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0:01f31e923fe2 | 82 | __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */ |
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0:01f31e923fe2 | 83 | __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */ |
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0:01f31e923fe2 | 84 | } mxc_pwrseq_regs_t; |
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0:01f31e923fe2 | 85 | |
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0:01f31e923fe2 | 86 | |
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0:01f31e923fe2 | 87 | /* |
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0:01f31e923fe2 | 88 | Register offsets for module PWRSEQ. |
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0:01f31e923fe2 | 89 | */ |
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0:01f31e923fe2 | 90 | |
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0:01f31e923fe2 | 91 | #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL) |
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0:01f31e923fe2 | 92 | #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL) |
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0:01f31e923fe2 | 93 | #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL) |
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0:01f31e923fe2 | 94 | #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL) |
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0:01f31e923fe2 | 95 | #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL) |
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0:01f31e923fe2 | 96 | #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL) |
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0:01f31e923fe2 | 97 | #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL) |
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0:01f31e923fe2 | 98 | #define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL) |
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0:01f31e923fe2 | 99 | #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL) |
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0:01f31e923fe2 | 100 | #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL) |
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0:01f31e923fe2 | 101 | #define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL) |
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0:01f31e923fe2 | 102 | #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL) |
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0:01f31e923fe2 | 103 | #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL) |
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0:01f31e923fe2 | 104 | #define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL) |
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0:01f31e923fe2 | 105 | #define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL) |
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0:01f31e923fe2 | 106 | |
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0:01f31e923fe2 | 107 | |
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0:01f31e923fe2 | 108 | /* |
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0:01f31e923fe2 | 109 | Field positions and masks for module PWRSEQ. |
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0:01f31e923fe2 | 110 | */ |
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0:01f31e923fe2 | 111 | |
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0:01f31e923fe2 | 112 | #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0 |
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0:01f31e923fe2 | 113 | #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS)) |
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0:01f31e923fe2 | 114 | #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1 |
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0:01f31e923fe2 | 115 | #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS)) |
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0:01f31e923fe2 | 116 | #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2 |
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0:01f31e923fe2 | 117 | #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS)) |
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0:01f31e923fe2 | 118 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3 |
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0:01f31e923fe2 | 119 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS)) |
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0:01f31e923fe2 | 120 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4 |
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0:01f31e923fe2 | 121 | #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS)) |
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0:01f31e923fe2 | 122 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5 |
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0:01f31e923fe2 | 123 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS)) |
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0:01f31e923fe2 | 124 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6 |
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0:01f31e923fe2 | 125 | #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS)) |
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0:01f31e923fe2 | 126 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7 |
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0:01f31e923fe2 | 127 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS)) |
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0:01f31e923fe2 | 128 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8 |
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0:01f31e923fe2 | 129 | #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS)) |
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0:01f31e923fe2 | 130 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9 |
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0:01f31e923fe2 | 131 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS)) |
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0:01f31e923fe2 | 132 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10 |
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0:01f31e923fe2 | 133 | #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS)) |
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0:01f31e923fe2 | 134 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11 |
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0:01f31e923fe2 | 135 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS)) |
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0:01f31e923fe2 | 136 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12 |
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0:01f31e923fe2 | 137 | #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS)) |
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0:01f31e923fe2 | 138 | #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13 |
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0:01f31e923fe2 | 139 | #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS)) |
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0:01f31e923fe2 | 140 | #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15 |
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0:01f31e923fe2 | 141 | #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS)) |
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0:01f31e923fe2 | 142 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17 |
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0:01f31e923fe2 | 143 | #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS)) |
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0:01f31e923fe2 | 144 | #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19 |
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0:01f31e923fe2 | 145 | #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS)) |
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0:01f31e923fe2 | 146 | #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21 |
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0:01f31e923fe2 | 147 | #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS)) |
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0:01f31e923fe2 | 148 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23 |
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0:01f31e923fe2 | 149 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS)) |
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0:01f31e923fe2 | 150 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24 |
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0:01f31e923fe2 | 151 | #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS)) |
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0:01f31e923fe2 | 152 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25 |
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0:01f31e923fe2 | 153 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS)) |
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0:01f31e923fe2 | 154 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26 |
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0:01f31e923fe2 | 155 | #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS)) |
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0:01f31e923fe2 | 156 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27 |
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0:01f31e923fe2 | 157 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS)) |
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0:01f31e923fe2 | 158 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28 |
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0:01f31e923fe2 | 159 | #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS)) |
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0:01f31e923fe2 | 160 | #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29 |
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0:01f31e923fe2 | 161 | #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS)) |
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0:01f31e923fe2 | 162 | #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30 |
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0:01f31e923fe2 | 163 | #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS)) |
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0:01f31e923fe2 | 164 | #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31 |
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0:01f31e923fe2 | 165 | #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS)) |
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0:01f31e923fe2 | 166 | |
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0:01f31e923fe2 | 167 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0 |
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0:01f31e923fe2 | 168 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS)) |
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0:01f31e923fe2 | 169 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1 |
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0:01f31e923fe2 | 170 | #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS)) |
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0:01f31e923fe2 | 171 | #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2 |
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0:01f31e923fe2 | 172 | #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS)) |
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0:01f31e923fe2 | 173 | #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3 |
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0:01f31e923fe2 | 174 | #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS)) |
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0:01f31e923fe2 | 175 | #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4 |
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0:01f31e923fe2 | 176 | #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS)) |
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0:01f31e923fe2 | 177 | #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5 |
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0:01f31e923fe2 | 178 | #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS)) |
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0:01f31e923fe2 | 179 | #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6 |
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0:01f31e923fe2 | 180 | #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS)) |
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0:01f31e923fe2 | 181 | #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8 |
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0:01f31e923fe2 | 182 | #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS)) |
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0:01f31e923fe2 | 183 | #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10 |
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0:01f31e923fe2 | 184 | #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS)) |
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0:01f31e923fe2 | 185 | #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12 |
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0:01f31e923fe2 | 186 | #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS)) |
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0:01f31e923fe2 | 187 | #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13 |
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0:01f31e923fe2 | 188 | #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS)) |
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0:01f31e923fe2 | 189 | #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14 |
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0:01f31e923fe2 | 190 | #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS)) |
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0:01f31e923fe2 | 191 | #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16 |
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0:01f31e923fe2 | 192 | #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS)) |
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0:01f31e923fe2 | 193 | #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17 |
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0:01f31e923fe2 | 194 | #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS)) |
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0:01f31e923fe2 | 195 | #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18 |
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0:01f31e923fe2 | 196 | #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS)) |
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0:01f31e923fe2 | 197 | #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19 |
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0:01f31e923fe2 | 198 | #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS)) |
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0:01f31e923fe2 | 199 | |
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0:01f31e923fe2 | 200 | #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0 |
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0:01f31e923fe2 | 201 | #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS)) |
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0:01f31e923fe2 | 202 | #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2 |
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0:01f31e923fe2 | 203 | #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS)) |
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0:01f31e923fe2 | 204 | #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4 |
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0:01f31e923fe2 | 205 | #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS)) |
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0:01f31e923fe2 | 206 | #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6 |
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0:01f31e923fe2 | 207 | #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS)) |
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0:01f31e923fe2 | 208 | #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8 |
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0:01f31e923fe2 | 209 | #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS)) |
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0:01f31e923fe2 | 210 | #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10 |
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0:01f31e923fe2 | 211 | #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS)) |
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0:01f31e923fe2 | 212 | #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12 |
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0:01f31e923fe2 | 213 | #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS)) |
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0:01f31e923fe2 | 214 | |
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0:01f31e923fe2 | 215 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0 |
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0:01f31e923fe2 | 216 | #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS)) |
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0:01f31e923fe2 | 217 | #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3 |
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0:01f31e923fe2 | 218 | #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS)) |
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0:01f31e923fe2 | 219 | #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6 |
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0:01f31e923fe2 | 220 | #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS)) |
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0:01f31e923fe2 | 221 | #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8 |
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0:01f31e923fe2 | 222 | #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS)) |
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0:01f31e923fe2 | 223 | #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10 |
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0:01f31e923fe2 | 224 | #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS)) |
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0:01f31e923fe2 | 225 | #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16 |
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0:01f31e923fe2 | 226 | #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)) |
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0:01f31e923fe2 | 227 | #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20 |
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0:01f31e923fe2 | 228 | #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)) |
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0:01f31e923fe2 | 229 | |
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0:01f31e923fe2 | 230 | #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0 |
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0:01f31e923fe2 | 231 | #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS)) |
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0:01f31e923fe2 | 232 | #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1 |
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0:01f31e923fe2 | 233 | #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS)) |
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0:01f31e923fe2 | 234 | #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3 |
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0:01f31e923fe2 | 235 | #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS)) |
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0:01f31e923fe2 | 236 | #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4 |
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0:01f31e923fe2 | 237 | #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS)) |
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0:01f31e923fe2 | 238 | #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5 |
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0:01f31e923fe2 | 239 | #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS)) |
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0:01f31e923fe2 | 240 | #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6 |
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0:01f31e923fe2 | 241 | #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS)) |
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0:01f31e923fe2 | 242 | #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7 |
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0:01f31e923fe2 | 243 | #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS)) |
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0:01f31e923fe2 | 244 | #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8 |
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0:01f31e923fe2 | 245 | #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS)) |
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0:01f31e923fe2 | 246 | #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9 |
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0:01f31e923fe2 | 247 | #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS)) |
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0:01f31e923fe2 | 248 | #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10 |
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0:01f31e923fe2 | 249 | #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS)) |
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0:01f31e923fe2 | 250 | |
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0:01f31e923fe2 | 251 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0 |
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0:01f31e923fe2 | 252 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS)) |
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0:01f31e923fe2 | 253 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9 |
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0:01f31e923fe2 | 254 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS)) |
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0:01f31e923fe2 | 255 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15 |
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0:01f31e923fe2 | 256 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS)) |
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0:01f31e923fe2 | 257 | #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21 |
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0:01f31e923fe2 | 258 | #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS)) |
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0:01f31e923fe2 | 259 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25 |
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0:01f31e923fe2 | 260 | #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS)) |
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0:01f31e923fe2 | 261 | |
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0:01f31e923fe2 | 262 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0 |
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0:01f31e923fe2 | 263 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS)) |
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0:01f31e923fe2 | 264 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3 |
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0:01f31e923fe2 | 265 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS)) |
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0:01f31e923fe2 | 266 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7 |
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0:01f31e923fe2 | 267 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS)) |
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0:01f31e923fe2 | 268 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11 |
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0:01f31e923fe2 | 269 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS)) |
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0:01f31e923fe2 | 270 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20 |
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0:01f31e923fe2 | 271 | #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS)) |
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0:01f31e923fe2 | 272 | |
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0:01f31e923fe2 | 273 | #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0 |
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0:01f31e923fe2 | 274 | #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS)) |
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0:01f31e923fe2 | 275 | #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16 |
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0:01f31e923fe2 | 276 | #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS)) |
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0:01f31e923fe2 | 277 | |
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0:01f31e923fe2 | 278 | #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0 |
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0:01f31e923fe2 | 279 | #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS)) |
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0:01f31e923fe2 | 280 | #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1 |
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0:01f31e923fe2 | 281 | #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS)) |
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0:01f31e923fe2 | 282 | #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2 |
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0:01f31e923fe2 | 283 | #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS)) |
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0:01f31e923fe2 | 284 | #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3 |
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0:01f31e923fe2 | 285 | #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS)) |
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0:01f31e923fe2 | 286 | #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4 |
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0:01f31e923fe2 | 287 | #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS)) |
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0:01f31e923fe2 | 288 | #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5 |
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0:01f31e923fe2 | 289 | #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS)) |
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0:01f31e923fe2 | 290 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6 |
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0:01f31e923fe2 | 291 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS)) |
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0:01f31e923fe2 | 292 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7 |
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0:01f31e923fe2 | 293 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS)) |
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0:01f31e923fe2 | 294 | #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8 |
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0:01f31e923fe2 | 295 | #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS)) |
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0:01f31e923fe2 | 296 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9 |
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0:01f31e923fe2 | 297 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS)) |
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0:01f31e923fe2 | 298 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10 |
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0:01f31e923fe2 | 299 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS)) |
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0:01f31e923fe2 | 300 | #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 |
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0:01f31e923fe2 | 301 | #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) |
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0:01f31e923fe2 | 302 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12 |
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0:01f31e923fe2 | 303 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS)) |
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0:01f31e923fe2 | 304 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13 |
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0:01f31e923fe2 | 305 | #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS)) |
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0:01f31e923fe2 | 306 | #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14 |
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0:01f31e923fe2 | 307 | #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS)) |
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0:01f31e923fe2 | 308 | #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15 |
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0:01f31e923fe2 | 309 | #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS)) |
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0:01f31e923fe2 | 310 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 |
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0:01f31e923fe2 | 311 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) |
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0:01f31e923fe2 | 312 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 |
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0:01f31e923fe2 | 313 | #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) |
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0:01f31e923fe2 | 314 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18 |
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0:01f31e923fe2 | 315 | #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS)) |
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0:01f31e923fe2 | 316 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19 |
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0:01f31e923fe2 | 317 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS)) |
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0:01f31e923fe2 | 318 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20 |
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0:01f31e923fe2 | 319 | #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS)) |
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0:01f31e923fe2 | 320 | #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21 |
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0:01f31e923fe2 | 321 | #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS)) |
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0:01f31e923fe2 | 322 | #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22 |
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0:01f31e923fe2 | 323 | #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS)) |
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0:01f31e923fe2 | 324 | #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23 |
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0:01f31e923fe2 | 325 | #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS)) |
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0:01f31e923fe2 | 326 | #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24 |
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0:01f31e923fe2 | 327 | #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS)) |
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0:01f31e923fe2 | 328 | |
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0:01f31e923fe2 | 329 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1 |
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0:01f31e923fe2 | 330 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS)) |
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0:01f31e923fe2 | 331 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2 |
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0:01f31e923fe2 | 332 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS)) |
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0:01f31e923fe2 | 333 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3 |
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0:01f31e923fe2 | 334 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS)) |
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0:01f31e923fe2 | 335 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4 |
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0:01f31e923fe2 | 336 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS)) |
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0:01f31e923fe2 | 337 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5 |
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0:01f31e923fe2 | 338 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS)) |
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0:01f31e923fe2 | 339 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6 |
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0:01f31e923fe2 | 340 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS)) |
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0:01f31e923fe2 | 341 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7 |
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0:01f31e923fe2 | 342 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS)) |
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0:01f31e923fe2 | 343 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8 |
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0:01f31e923fe2 | 344 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS)) |
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0:01f31e923fe2 | 345 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9 |
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0:01f31e923fe2 | 346 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS)) |
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0:01f31e923fe2 | 347 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10 |
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0:01f31e923fe2 | 348 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS)) |
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0:01f31e923fe2 | 349 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11 |
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0:01f31e923fe2 | 350 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS)) |
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0:01f31e923fe2 | 351 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12 |
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0:01f31e923fe2 | 352 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS)) |
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0:01f31e923fe2 | 353 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13 |
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0:01f31e923fe2 | 354 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS)) |
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0:01f31e923fe2 | 355 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14 |
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0:01f31e923fe2 | 356 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS)) |
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0:01f31e923fe2 | 357 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15 |
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0:01f31e923fe2 | 358 | #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS)) |
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0:01f31e923fe2 | 359 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16 |
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0:01f31e923fe2 | 360 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS)) |
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0:01f31e923fe2 | 361 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17 |
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0:01f31e923fe2 | 362 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS)) |
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0:01f31e923fe2 | 363 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18 |
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0:01f31e923fe2 | 364 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS)) |
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0:01f31e923fe2 | 365 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19 |
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0:01f31e923fe2 | 366 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS)) |
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0:01f31e923fe2 | 367 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20 |
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0:01f31e923fe2 | 368 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS)) |
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0:01f31e923fe2 | 369 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21 |
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0:01f31e923fe2 | 370 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS)) |
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0:01f31e923fe2 | 371 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22 |
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0:01f31e923fe2 | 372 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS)) |
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0:01f31e923fe2 | 373 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23 |
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0:01f31e923fe2 | 374 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS)) |
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0:01f31e923fe2 | 375 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24 |
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0:01f31e923fe2 | 376 | #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS)) |
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0:01f31e923fe2 | 377 | |
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0:01f31e923fe2 | 378 | #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0 |
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0:01f31e923fe2 | 379 | #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS)) |
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0:01f31e923fe2 | 380 | #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8 |
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0:01f31e923fe2 | 381 | #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS)) |
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0:01f31e923fe2 | 382 | #define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28 |
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0:01f31e923fe2 | 383 | #define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS)) |
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0:01f31e923fe2 | 384 | #define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29 |
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0:01f31e923fe2 | 385 | #define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS)) |
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0:01f31e923fe2 | 386 | #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30 |
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0:01f31e923fe2 | 387 | #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS)) |
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0:01f31e923fe2 | 388 | #define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31 |
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0:01f31e923fe2 | 389 | #define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS)) |
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0:01f31e923fe2 | 390 | |
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0:01f31e923fe2 | 391 | #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0 |
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0:01f31e923fe2 | 392 | #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS)) |
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0:01f31e923fe2 | 393 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1 |
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0:01f31e923fe2 | 394 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS)) |
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0:01f31e923fe2 | 395 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2 |
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0:01f31e923fe2 | 396 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS)) |
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0:01f31e923fe2 | 397 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3 |
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0:01f31e923fe2 | 398 | #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS)) |
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0:01f31e923fe2 | 399 | #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4 |
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0:01f31e923fe2 | 400 | #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS)) |
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0:01f31e923fe2 | 401 | |
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0:01f31e923fe2 | 402 | #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0 |
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0:01f31e923fe2 | 403 | #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS)) |
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0:01f31e923fe2 | 404 | #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4 |
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0:01f31e923fe2 | 405 | #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS)) |
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0:01f31e923fe2 | 406 | |
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0:01f31e923fe2 | 407 | #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0 |
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0:01f31e923fe2 | 408 | #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS)) |
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0:01f31e923fe2 | 409 | |
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0:01f31e923fe2 | 410 | #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0 |
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0:01f31e923fe2 | 411 | #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS)) |
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0:01f31e923fe2 | 412 | #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1 |
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0:01f31e923fe2 | 413 | #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS)) |
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0:01f31e923fe2 | 414 | #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2 |
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0:01f31e923fe2 | 415 | #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS)) |
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0:01f31e923fe2 | 416 | #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3 |
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0:01f31e923fe2 | 417 | #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS)) |
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0:01f31e923fe2 | 418 | #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24 |
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0:01f31e923fe2 | 419 | #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS)) |
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0:01f31e923fe2 | 420 | |
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0:01f31e923fe2 | 421 | #ifdef __cplusplus |
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0:01f31e923fe2 | 422 | } |
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0:01f31e923fe2 | 423 | #endif |
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0:01f31e923fe2 | 424 | |
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0:01f31e923fe2 | 425 | #endif /* _MXC_PWRSEQ_REGS_H_ */ |