Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32625/owm_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ****************************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Permission is hereby granted, free of charge, to any person obtaining a
Pawel Zarembski 0:01f31e923fe2 5 * copy of this software and associated documentation files (the "Software"),
Pawel Zarembski 0:01f31e923fe2 6 * to deal in the Software without restriction, including without limitation
Pawel Zarembski 0:01f31e923fe2 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Pawel Zarembski 0:01f31e923fe2 8 * and/or sell copies of the Software, and to permit persons to whom the
Pawel Zarembski 0:01f31e923fe2 9 * Software is furnished to do so, subject to the following conditions:
Pawel Zarembski 0:01f31e923fe2 10 *
Pawel Zarembski 0:01f31e923fe2 11 * The above copyright notice and this permission notice shall be included
Pawel Zarembski 0:01f31e923fe2 12 * in all copies or substantial portions of the Software.
Pawel Zarembski 0:01f31e923fe2 13 *
Pawel Zarembski 0:01f31e923fe2 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Pawel Zarembski 0:01f31e923fe2 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Pawel Zarembski 0:01f31e923fe2 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Pawel Zarembski 0:01f31e923fe2 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Pawel Zarembski 0:01f31e923fe2 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Pawel Zarembski 0:01f31e923fe2 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Pawel Zarembski 0:01f31e923fe2 20 * OTHER DEALINGS IN THE SOFTWARE.
Pawel Zarembski 0:01f31e923fe2 21 *
Pawel Zarembski 0:01f31e923fe2 22 * Except as contained in this notice, the name of Maxim Integrated
Pawel Zarembski 0:01f31e923fe2 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Pawel Zarembski 0:01f31e923fe2 24 * Products, Inc. Branding Policy.
Pawel Zarembski 0:01f31e923fe2 25 *
Pawel Zarembski 0:01f31e923fe2 26 * The mere transfer of this software does not imply any licenses
Pawel Zarembski 0:01f31e923fe2 27 * of trade secrets, proprietary technology, copyrights, patents,
Pawel Zarembski 0:01f31e923fe2 28 * trademarks, maskwork rights, or any other form of intellectual
Pawel Zarembski 0:01f31e923fe2 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Pawel Zarembski 0:01f31e923fe2 30 * ownership rights.
Pawel Zarembski 0:01f31e923fe2 31 *
Pawel Zarembski 0:01f31e923fe2 32 **************************************************************************** */
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /* Define to prevent redundant inclusion */
Pawel Zarembski 0:01f31e923fe2 35 #ifndef _MXC_OWM_REGS_H_
Pawel Zarembski 0:01f31e923fe2 36 #define _MXC_OWM_REGS_H_
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 #include <stdint.h>
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 41 extern "C" {
Pawel Zarembski 0:01f31e923fe2 42 #endif
Pawel Zarembski 0:01f31e923fe2 43
Pawel Zarembski 0:01f31e923fe2 44 /*
Pawel Zarembski 0:01f31e923fe2 45 If types are not defined elsewhere (CMSIS) define them here
Pawel Zarembski 0:01f31e923fe2 46 */
Pawel Zarembski 0:01f31e923fe2 47 ///@cond
Pawel Zarembski 0:01f31e923fe2 48 #ifndef __IO
Pawel Zarembski 0:01f31e923fe2 49 #define __IO volatile
Pawel Zarembski 0:01f31e923fe2 50 #endif
Pawel Zarembski 0:01f31e923fe2 51 #ifndef __I
Pawel Zarembski 0:01f31e923fe2 52 #define __I volatile const
Pawel Zarembski 0:01f31e923fe2 53 #endif
Pawel Zarembski 0:01f31e923fe2 54 #ifndef __O
Pawel Zarembski 0:01f31e923fe2 55 #define __O volatile
Pawel Zarembski 0:01f31e923fe2 56 #endif
Pawel Zarembski 0:01f31e923fe2 57 #ifndef __R
Pawel Zarembski 0:01f31e923fe2 58 #define __R volatile const
Pawel Zarembski 0:01f31e923fe2 59 #endif
Pawel Zarembski 0:01f31e923fe2 60 ///@endcond
Pawel Zarembski 0:01f31e923fe2 61
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 /**
Pawel Zarembski 0:01f31e923fe2 64 * @defgroup owm_registers Registers
Pawel Zarembski 0:01f31e923fe2 65 * @brief Registers, Bit Masks and Bit Positions
Pawel Zarembski 0:01f31e923fe2 66 * @ingroup owm
Pawel Zarembski 0:01f31e923fe2 67 * @{
Pawel Zarembski 0:01f31e923fe2 68 */
Pawel Zarembski 0:01f31e923fe2 69 /**
Pawel Zarembski 0:01f31e923fe2 70 * Structure type for the 1-Wire Master module registers allowing direct 32-bit access to each register.
Pawel Zarembski 0:01f31e923fe2 71 */
Pawel Zarembski 0:01f31e923fe2 72 typedef struct {
Pawel Zarembski 0:01f31e923fe2 73 __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM_CFG Register - 1-Wire Master Configuration */
Pawel Zarembski 0:01f31e923fe2 74 __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM_CLK_DIV_1US Register - 1-Wire Master Clock Divisor */
Pawel Zarembski 0:01f31e923fe2 75 __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM_CTRL_STAT Register - 1-Wire Master Control/Status */
Pawel Zarembski 0:01f31e923fe2 76 __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM_DATA Register - 1-Wire Master Data Buffer */
Pawel Zarembski 0:01f31e923fe2 77 __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM_INTFL Register - 1-Wire Master Interrupt Flags */
Pawel Zarembski 0:01f31e923fe2 78 __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM_INTEN Register - 1-Wire Master Interrupt Enables */
Pawel Zarembski 0:01f31e923fe2 79 } mxc_owm_regs_t;
Pawel Zarembski 0:01f31e923fe2 80 /**@} end of group owm_registers */
Pawel Zarembski 0:01f31e923fe2 81
Pawel Zarembski 0:01f31e923fe2 82 /**
Pawel Zarembski 0:01f31e923fe2 83 * @defgroup OWM_Register_Offsets Register Offsets
Pawel Zarembski 0:01f31e923fe2 84 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 85 * @brief 1-Wire Master register offsets from the 1-Wire Master Base Peripheral Address.
Pawel Zarembski 0:01f31e923fe2 86 * @{
Pawel Zarembski 0:01f31e923fe2 87 */
Pawel Zarembski 0:01f31e923fe2 88 #define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0000:</tt>*/
Pawel Zarembski 0:01f31e923fe2 89 #define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0004:</tt>*/
Pawel Zarembski 0:01f31e923fe2 90 #define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0008:</tt>*/
Pawel Zarembski 0:01f31e923fe2 91 #define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x000C:</tt>*/
Pawel Zarembski 0:01f31e923fe2 92 #define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0010:</tt>*/
Pawel Zarembski 0:01f31e923fe2 93 #define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0014:</tt>*/
Pawel Zarembski 0:01f31e923fe2 94 /**@} end of group OWM_Register_Offsets */
Pawel Zarembski 0:01f31e923fe2 95
Pawel Zarembski 0:01f31e923fe2 96 /*
Pawel Zarembski 0:01f31e923fe2 97 Field positions and masks for module OWM.
Pawel Zarembski 0:01f31e923fe2 98 */
Pawel Zarembski 0:01f31e923fe2 99 /**
Pawel Zarembski 0:01f31e923fe2 100 * @defgroup owm_cfg OWM_CFG
Pawel Zarembski 0:01f31e923fe2 101 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 102 * @brief Field Positions and Masks
Pawel Zarembski 0:01f31e923fe2 103 */
Pawel Zarembski 0:01f31e923fe2 104 #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< LONG_LINE_MODE Position */
Pawel Zarembski 0:01f31e923fe2 105 #define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< LONG_LINE_MODE Mask */
Pawel Zarembski 0:01f31e923fe2 106 #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< FORCE_PRES_DET Position */
Pawel Zarembski 0:01f31e923fe2 107 #define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< FORCE_PRES_DET Mask */
Pawel Zarembski 0:01f31e923fe2 108 #define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< BIT_BANG_EN Position */
Pawel Zarembski 0:01f31e923fe2 109 #define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< BIT_BANG_EN Mask */
Pawel Zarembski 0:01f31e923fe2 110 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< EXT_PULLUP_MODE Position */
Pawel Zarembski 0:01f31e923fe2 111 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< EXT_PULLUP_MODE Mask */
Pawel Zarembski 0:01f31e923fe2 112 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< EXT_PULLUP_ENABLE Position */
Pawel Zarembski 0:01f31e923fe2 113 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< EXT_PULLUP_ENABLE Mask */
Pawel Zarembski 0:01f31e923fe2 114 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< SINGLE_BIT_MODE Position */
Pawel Zarembski 0:01f31e923fe2 115 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< SINGLE_BIT_MODE Mask */
Pawel Zarembski 0:01f31e923fe2 116 #define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< OVERDRIVE Position */
Pawel Zarembski 0:01f31e923fe2 117 #define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< OVERDRIVE Mask */
Pawel Zarembski 0:01f31e923fe2 118 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< INT_PULLUP_ENABLE Position */
Pawel Zarembski 0:01f31e923fe2 119 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< INT_PULLUP_ENABLE Mask */
Pawel Zarembski 0:01f31e923fe2 120 /**@} end of group owm_cfg*/
Pawel Zarembski 0:01f31e923fe2 121 /**
Pawel Zarembski 0:01f31e923fe2 122 * @defgroup owm_clk_div OWM_CLK_DIV
Pawel Zarembski 0:01f31e923fe2 123 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 124 * @brief Field Positions and Masks
Pawel Zarembski 0:01f31e923fe2 125 */
Pawel Zarembski 0:01f31e923fe2 126 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< 1US_DIVISOR Position */
Pawel Zarembski 0:01f31e923fe2 127 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< 1US_DIVISOR Mask */
Pawel Zarembski 0:01f31e923fe2 128 /**@} end of group owm_clk_cfg*/
Pawel Zarembski 0:01f31e923fe2 129 /**
Pawel Zarembski 0:01f31e923fe2 130 * @defgroup owm_ctrl_stat OWM_CTRL_STAT
Pawel Zarembski 0:01f31e923fe2 131 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 132 * @brief Field Positions and Masks
Pawel Zarembski 0:01f31e923fe2 133 */
Pawel Zarembski 0:01f31e923fe2 134 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< START_OW_RESET Position */
Pawel Zarembski 0:01f31e923fe2 135 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< START_OW_RESET Mask */
Pawel Zarembski 0:01f31e923fe2 136 #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< SRA_MODE Position */
Pawel Zarembski 0:01f31e923fe2 137 #define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< SRA_MODE Mask */
Pawel Zarembski 0:01f31e923fe2 138 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< BIT_BANG_OE Position */
Pawel Zarembski 0:01f31e923fe2 139 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< BIT_BANG_OE Mask */
Pawel Zarembski 0:01f31e923fe2 140 #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< OW_INPUT Position */
Pawel Zarembski 0:01f31e923fe2 141 #define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< OW_INPUT Mask */
Pawel Zarembski 0:01f31e923fe2 142 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< OD_SPEC_MODE Position */
Pawel Zarembski 0:01f31e923fe2 143 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< OD_SPEC_MODE Mask */
Pawel Zarembski 0:01f31e923fe2 144 #define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS 5 /**< EXT_PULLUP_POL Position */
Pawel Zarembski 0:01f31e923fe2 145 #define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS)) /**< EXT_PULLUP_POL Mask */
Pawel Zarembski 0:01f31e923fe2 146 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< PRESENCE_DETECT Position */
Pawel Zarembski 0:01f31e923fe2 147 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< PRESENCE_DETECT Mask */
Pawel Zarembski 0:01f31e923fe2 148 /**@} end of group owm_ctrl*/
Pawel Zarembski 0:01f31e923fe2 149 /**
Pawel Zarembski 0:01f31e923fe2 150 * @defgroup owm_data OWM_DATA
Pawel Zarembski 0:01f31e923fe2 151 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 152 * @brief Field Positions and Masks
Pawel Zarembski 0:01f31e923fe2 153 */
Pawel Zarembski 0:01f31e923fe2 154 #define MXC_F_OWM_DATA_TX_RX_POS 0 /**< TX_RX Position */
Pawel Zarembski 0:01f31e923fe2 155 #define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< TX_RX Mask */
Pawel Zarembski 0:01f31e923fe2 156 /**@} end of group owm_data*/
Pawel Zarembski 0:01f31e923fe2 157 /**
Pawel Zarembski 0:01f31e923fe2 158 * @defgroup owm_intfl OWM_INTFL
Pawel Zarembski 0:01f31e923fe2 159 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 160 * @brief Field Positions and Masks
Pawel Zarembski 0:01f31e923fe2 161 */
Pawel Zarembski 0:01f31e923fe2 162 #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
Pawel Zarembski 0:01f31e923fe2 163 #define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
Pawel Zarembski 0:01f31e923fe2 164 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
Pawel Zarembski 0:01f31e923fe2 165 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
Pawel Zarembski 0:01f31e923fe2 166 #define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
Pawel Zarembski 0:01f31e923fe2 167 #define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
Pawel Zarembski 0:01f31e923fe2 168 #define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
Pawel Zarembski 0:01f31e923fe2 169 #define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
Pawel Zarembski 0:01f31e923fe2 170 #define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< LINE_LOW Position */
Pawel Zarembski 0:01f31e923fe2 171 #define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< LINE_LOW Mask */
Pawel Zarembski 0:01f31e923fe2 172 /**@} end of group owm_intfl*/
Pawel Zarembski 0:01f31e923fe2 173 /**
Pawel Zarembski 0:01f31e923fe2 174 * @defgroup owm_inten OWM_INTEN
Pawel Zarembski 0:01f31e923fe2 175 * @ingroup owm_registers
Pawel Zarembski 0:01f31e923fe2 176 * @brief Field Positions and Masks
Pawel Zarembski 0:01f31e923fe2 177 */
Pawel Zarembski 0:01f31e923fe2 178 #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
Pawel Zarembski 0:01f31e923fe2 179 #define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
Pawel Zarembski 0:01f31e923fe2 180 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
Pawel Zarembski 0:01f31e923fe2 181 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
Pawel Zarembski 0:01f31e923fe2 182 #define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
Pawel Zarembski 0:01f31e923fe2 183 #define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
Pawel Zarembski 0:01f31e923fe2 184 #define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
Pawel Zarembski 0:01f31e923fe2 185 #define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
Pawel Zarembski 0:01f31e923fe2 186 #define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< LINE_LOW Position */
Pawel Zarembski 0:01f31e923fe2 187 #define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< LINE_LOW Mask */
Pawel Zarembski 0:01f31e923fe2 188 /**@} end of group owm_inten*/
Pawel Zarembski 0:01f31e923fe2 189 /**
Pawel Zarembski 0:01f31e923fe2 190 * @ingroup owm_cfg
Pawel Zarembski 0:01f31e923fe2 191 * @{
Pawel Zarembski 0:01f31e923fe2 192 */
Pawel Zarembski 0:01f31e923fe2 193 #define MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED ((uint32_t)(0x00000000UL)) /**< External Pullup Mode Value: Unused */
Pawel Zarembski 0:01f31e923fe2 194 #define MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED ((uint32_t)(0x00000001UL)) /**< External Pullup Mode Value: Used */
Pawel Zarembski 0:01f31e923fe2 195 /**@}*/
Pawel Zarembski 0:01f31e923fe2 196 /**
Pawel Zarembski 0:01f31e923fe2 197 * @ingroup owm_ctrl_stat
Pawel Zarembski 0:01f31e923fe2 198 * @{
Pawel Zarembski 0:01f31e923fe2 199 */
Pawel Zarembski 0:01f31e923fe2 200 #define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US ((uint32_t)(0x00000000UL)) /**< Overdrive speed setting 12us. */
Pawel Zarembski 0:01f31e923fe2 201 #define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US ((uint32_t)(0x00000001UL)) /**< Overdrive speed setting 10us. */
Pawel Zarembski 0:01f31e923fe2 202
Pawel Zarembski 0:01f31e923fe2 203 #define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH ((uint32_t)(0x00000000UL)) /**< External Pullup Pin Polarity Active High */
Pawel Zarembski 0:01f31e923fe2 204 #define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW ((uint32_t)(0x00000001UL)) /**< External Pullup Pin Polarity Active Low */
Pawel Zarembski 0:01f31e923fe2 205 /**@}*/
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 208 }
Pawel Zarembski 0:01f31e923fe2 209 #endif
Pawel Zarembski 0:01f31e923fe2 210
Pawel Zarembski 0:01f31e923fe2 211 #endif /* _MXC_OWM_REGS_H_ */