Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/max32625.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /******************************************************************************* |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | ******************************************************************************/ |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | #ifndef _MAX32625_H_ |
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0:01f31e923fe2 | 35 | #define _MAX32625_H_ |
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0:01f31e923fe2 | 36 | |
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0:01f31e923fe2 | 37 | #include <stdint.h> |
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0:01f31e923fe2 | 38 | |
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0:01f31e923fe2 | 39 | #ifndef FALSE |
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0:01f31e923fe2 | 40 | #define FALSE (0) |
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0:01f31e923fe2 | 41 | #endif |
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0:01f31e923fe2 | 42 | |
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0:01f31e923fe2 | 43 | #ifndef TRUE |
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0:01f31e923fe2 | 44 | #define TRUE (1) |
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0:01f31e923fe2 | 45 | #endif |
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0:01f31e923fe2 | 46 | |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ |
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0:01f31e923fe2 | 48 | #if defined ( __GNUC__ ) |
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0:01f31e923fe2 | 49 | #define __weak __attribute__((weak)) |
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0:01f31e923fe2 | 50 | |
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0:01f31e923fe2 | 51 | #elif defined ( __CC_ARM) |
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0:01f31e923fe2 | 52 | |
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0:01f31e923fe2 | 53 | #define inline __inline |
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0:01f31e923fe2 | 54 | #pragma anon_unions |
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0:01f31e923fe2 | 55 | |
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0:01f31e923fe2 | 56 | #endif |
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0:01f31e923fe2 | 57 | |
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0:01f31e923fe2 | 58 | typedef enum { |
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0:01f31e923fe2 | 59 | NonMaskableInt_IRQn = -14, |
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0:01f31e923fe2 | 60 | HardFault_IRQn = -13, |
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0:01f31e923fe2 | 61 | MemoryManagement_IRQn = -12, |
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0:01f31e923fe2 | 62 | BusFault_IRQn = -11, |
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0:01f31e923fe2 | 63 | UsageFault_IRQn = -10, |
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0:01f31e923fe2 | 64 | SVCall_IRQn = -5, |
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0:01f31e923fe2 | 65 | DebugMonitor_IRQn = -4, |
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0:01f31e923fe2 | 66 | PendSV_IRQn = -2, |
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0:01f31e923fe2 | 67 | SysTick_IRQn = -1, |
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0:01f31e923fe2 | 68 | |
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0:01f31e923fe2 | 69 | /* Device-specific interrupt sources (external to ARM core) */ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | /* table entry number */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | /* |||| */ |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | /* |||| table offset address */ |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | /* vvvv vvvvvv */ |
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0:01f31e923fe2 | 74 | |
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0:01f31e923fe2 | 75 | CLKMAN_IRQn = 0, /* 0x10 0x0040,CLKMAN */ |
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0:01f31e923fe2 | 76 | PWRMAN_IRQn = 1, /* 0x11 0x0044 PWRMAN */ |
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0:01f31e923fe2 | 77 | FLC_IRQn = 2, /* 0x12 0x0048 Flash Controller */ |
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0:01f31e923fe2 | 78 | RTC0_IRQn = 3, /* 0x13 0x004C RTC Counter match with Compare 0 */ |
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0:01f31e923fe2 | 79 | RTC1_IRQn = 4, /* 0x14 0x0050 RTC Counter match with Compare 1 */ |
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0:01f31e923fe2 | 80 | RTC2_IRQn = 5, /* 0x15 0x0054 RTC Prescaler interval compare match */ |
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0:01f31e923fe2 | 81 | RTC3_IRQn = 6, /* 0x16 0x0058 RTC Overflow */ |
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0:01f31e923fe2 | 82 | PMU_IRQn = 7, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */ |
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0:01f31e923fe2 | 83 | USB_IRQn = 8, /* 0x18 0x0060 USB */ |
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0:01f31e923fe2 | 84 | AES_IRQn = 9, /* 0x19 0x0064 AES */ |
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0:01f31e923fe2 | 85 | MAA_IRQn = 10, /* 0x1A 0x0068 MAA */ |
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0:01f31e923fe2 | 86 | WDT0_IRQn = 11, /* 0x1B 0x006C Watchdog 0 timeout */ |
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0:01f31e923fe2 | 87 | WDT0_P_IRQn = 12, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */ |
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0:01f31e923fe2 | 88 | WDT1_IRQn = 13, /* 0x1D 0x0074 Watchdog 1 timeout */ |
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0:01f31e923fe2 | 89 | WDT1_P_IRQn = 14, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */ |
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0:01f31e923fe2 | 90 | GPIO_P0_IRQn = 15, /* 0x1F 0x007C GPIO Port 0 */ |
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0:01f31e923fe2 | 91 | GPIO_P1_IRQn = 16, /* 0x20 0x0080 GPIO Port 1 */ |
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0:01f31e923fe2 | 92 | GPIO_P2_IRQn = 17, /* 0x21 0x0084 GPIO Port 2 */ |
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0:01f31e923fe2 | 93 | GPIO_P3_IRQn = 18, /* 0x22 0x0088 GPIO Port 3 */ |
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0:01f31e923fe2 | 94 | GPIO_P4_IRQn = 19, /* 0x23 0x008C GPIO Port 4 */ |
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0:01f31e923fe2 | 95 | // Reserved = 20, /* 0x24 0x0090 Reserved */ |
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0:01f31e923fe2 | 96 | // Reserved = 21, /* 0x25 0x0094 Reserved */ |
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0:01f31e923fe2 | 97 | TMR0_0_IRQn = 22, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */ |
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0:01f31e923fe2 | 98 | TMR0_1_IRQn = 23, /* 0x27 0x009C Timer 0 (16-bit #1) */ |
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0:01f31e923fe2 | 99 | TMR1_0_IRQn = 24, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */ |
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0:01f31e923fe2 | 100 | TMR1_1_IRQn = 25, /* 0x29 0x00A4 Timer 1 (16-bit #1) */ |
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0:01f31e923fe2 | 101 | TMR2_0_IRQn = 26, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */ |
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0:01f31e923fe2 | 102 | TMR2_1_IRQn = 27, /* 0x2B 0x00AC Timer 2 (16-bit #1) */ |
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0:01f31e923fe2 | 103 | TMR3_0_IRQn = 28, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */ |
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0:01f31e923fe2 | 104 | TMR3_1_IRQn = 29, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */ |
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0:01f31e923fe2 | 105 | TMR4_0_IRQn = 30, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */ |
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0:01f31e923fe2 | 106 | TMR4_1_IRQn = 31, /* 0x2F 0x00BC Timer 4 (16-bit #1) */ |
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0:01f31e923fe2 | 107 | TMR5_0_IRQn = 32, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */ |
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0:01f31e923fe2 | 108 | TMR5_1_IRQn = 33, /* 0x31 0x00C4 Timer 5 (16-bit #1) */ |
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0:01f31e923fe2 | 109 | UART0_IRQn = 34, /* 0x32 0x00C8 UART 0 */ |
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0:01f31e923fe2 | 110 | UART1_IRQn = 35, /* 0x33 0x00CC UART 1 */ |
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0:01f31e923fe2 | 111 | UART2_IRQn = 36, /* 0x34 0x00D0 UART 2 */ |
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0:01f31e923fe2 | 112 | UART3_IRQn = 37, /* 0x35 0x00D4 UART 3 (Unused) */ |
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0:01f31e923fe2 | 113 | PT_IRQn = 38, /* 0x36 0x00D8 Pulse Trains */ |
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0:01f31e923fe2 | 114 | I2CM0_IRQn = 39, /* 0x37 0x00DC I2C Master 0 */ |
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0:01f31e923fe2 | 115 | I2CM1_IRQn = 40, /* 0x38 0x00E0 I2C Master 1 */ |
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0:01f31e923fe2 | 116 | I2CM2_IRQn = 41, /* 0x39 0x00E4 I2C Master 2 (Unused) */ |
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0:01f31e923fe2 | 117 | I2CS_IRQn = 42, /* 0x3A 0x00E8 I2C Slave */ |
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0:01f31e923fe2 | 118 | SPIM0_IRQn = 43, /* 0x3B 0x00EC SPI Master 0 */ |
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0:01f31e923fe2 | 119 | SPIM1_IRQn = 44, /* 0x3C 0x00F0 SPI Master 1 */ |
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0:01f31e923fe2 | 120 | SPIM2_IRQn = 45, /* 0x3D 0x00F4 SPI Master 2 */ |
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0:01f31e923fe2 | 121 | SPIB_IRQn = 46, /* 0x3E 0x00F8 SPI Bridge (Unused) */ |
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0:01f31e923fe2 | 122 | OWM_IRQn = 47, /* 0x3F 0x00FC 1-Wire Master */ |
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0:01f31e923fe2 | 123 | AFE_IRQn = 48, /* 0x40 0x0100 Analog Front End, ADC */ |
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0:01f31e923fe2 | 124 | SPIS_IRQn = 49, /* 0x41 0x0104 SPI Slave */ |
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0:01f31e923fe2 | 125 | MXC_IRQ_EXT_COUNT, |
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0:01f31e923fe2 | 126 | } IRQn_Type; |
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0:01f31e923fe2 | 127 | |
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0:01f31e923fe2 | 128 | #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) |
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0:01f31e923fe2 | 129 | |
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0:01f31e923fe2 | 130 | |
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0:01f31e923fe2 | 131 | /* ================================================================================ */ |
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0:01f31e923fe2 | 132 | /* ================ Processor and Core Peripheral Section ================ */ |
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0:01f31e923fe2 | 133 | /* ================================================================================ */ |
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0:01f31e923fe2 | 134 | |
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0:01f31e923fe2 | 135 | /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ |
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0:01f31e923fe2 | 136 | #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ |
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0:01f31e923fe2 | 137 | #define __MPU_PRESENT 1 /*!< MPU present or not */ |
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0:01f31e923fe2 | 138 | #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ |
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0:01f31e923fe2 | 139 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
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0:01f31e923fe2 | 140 | #define __FPU_PRESENT 1 /*!< FPU present or not */ |
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0:01f31e923fe2 | 141 | |
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0:01f31e923fe2 | 142 | #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ |
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0:01f31e923fe2 | 143 | #include "system_max32625.h" /*!< System Header */ |
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0:01f31e923fe2 | 144 | |
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0:01f31e923fe2 | 145 | |
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0:01f31e923fe2 | 146 | /* ================================================================================ */ |
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0:01f31e923fe2 | 147 | /* ================== Device Specific Memory Section ================== */ |
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0:01f31e923fe2 | 148 | /* ================================================================================ */ |
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0:01f31e923fe2 | 149 | |
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0:01f31e923fe2 | 150 | #define MXC_FLASH_MEM_BASE 0x00000000UL |
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0:01f31e923fe2 | 151 | #define MXC_FLASH_PAGE_SIZE 0x00002000UL |
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0:01f31e923fe2 | 152 | #define MXC_FLASH_FULL_MEM_SIZE 0x00080000UL |
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0:01f31e923fe2 | 153 | #define MXC_SYS_MEM_BASE 0x20000000UL |
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0:01f31e923fe2 | 154 | #define MXC_SRAM_FULL_MEM_SIZE 0x00028000UL |
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0:01f31e923fe2 | 155 | #define MXC_EXT_FLASH_MEM_BASE 0x10000000UL |
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0:01f31e923fe2 | 156 | |
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0:01f31e923fe2 | 157 | /* ================================================================================ */ |
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0:01f31e923fe2 | 158 | /* ================ Device Specific Peripheral Section ================ */ |
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0:01f31e923fe2 | 159 | /* ================================================================================ */ |
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0:01f31e923fe2 | 160 | |
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0:01f31e923fe2 | 161 | |
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0:01f31e923fe2 | 162 | /* |
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0:01f31e923fe2 | 163 | Base addresses and configuration settings for all MAX32625 peripheral modules. |
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0:01f31e923fe2 | 164 | */ |
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0:01f31e923fe2 | 165 | |
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0:01f31e923fe2 | 166 | |
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0:01f31e923fe2 | 167 | /*******************************************************************************/ |
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0:01f31e923fe2 | 168 | /* System Manager Settings */ |
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0:01f31e923fe2 | 169 | |
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0:01f31e923fe2 | 170 | #define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL) |
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0:01f31e923fe2 | 171 | #define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN) |
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0:01f31e923fe2 | 172 | |
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0:01f31e923fe2 | 173 | |
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0:01f31e923fe2 | 174 | |
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0:01f31e923fe2 | 175 | /*******************************************************************************/ |
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0:01f31e923fe2 | 176 | /* System Clock Manager */ |
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0:01f31e923fe2 | 177 | |
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0:01f31e923fe2 | 178 | #define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL) |
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0:01f31e923fe2 | 179 | #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) |
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0:01f31e923fe2 | 180 | |
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0:01f31e923fe2 | 181 | |
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0:01f31e923fe2 | 182 | |
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0:01f31e923fe2 | 183 | /*******************************************************************************/ |
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0:01f31e923fe2 | 184 | /* System Power Manager */ |
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0:01f31e923fe2 | 185 | |
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0:01f31e923fe2 | 186 | #define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL) |
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0:01f31e923fe2 | 187 | #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) |
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0:01f31e923fe2 | 188 | |
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0:01f31e923fe2 | 189 | |
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0:01f31e923fe2 | 190 | |
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0:01f31e923fe2 | 191 | /*******************************************************************************/ |
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0:01f31e923fe2 | 192 | /* Real Time Clock */ |
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0:01f31e923fe2 | 193 | |
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0:01f31e923fe2 | 194 | #define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL) |
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0:01f31e923fe2 | 195 | #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) |
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0:01f31e923fe2 | 196 | #define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL) |
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0:01f31e923fe2 | 197 | #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) |
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0:01f31e923fe2 | 198 | |
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0:01f31e923fe2 | 199 | #define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? RTC0_IRQn : \ |
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0:01f31e923fe2 | 200 | (i) == 1 ? RTC1_IRQn : \ |
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0:01f31e923fe2 | 201 | (i) == 2 ? RTC2_IRQn : \ |
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0:01f31e923fe2 | 202 | (i) == 3 ? RTC3_IRQn : 0) |
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0:01f31e923fe2 | 203 | |
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0:01f31e923fe2 | 204 | |
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0:01f31e923fe2 | 205 | |
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0:01f31e923fe2 | 206 | /*******************************************************************************/ |
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0:01f31e923fe2 | 207 | /* Power Sequencer */ |
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0:01f31e923fe2 | 208 | |
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0:01f31e923fe2 | 209 | #define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL) |
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0:01f31e923fe2 | 210 | #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) |
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0:01f31e923fe2 | 211 | |
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0:01f31e923fe2 | 212 | |
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0:01f31e923fe2 | 213 | |
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0:01f31e923fe2 | 214 | /*******************************************************************************/ |
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0:01f31e923fe2 | 215 | /* System I/O Manager */ |
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0:01f31e923fe2 | 216 | |
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0:01f31e923fe2 | 217 | #define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) |
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0:01f31e923fe2 | 218 | #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) |
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0:01f31e923fe2 | 219 | |
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0:01f31e923fe2 | 220 | |
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0:01f31e923fe2 | 221 | |
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0:01f31e923fe2 | 222 | /*******************************************************************************/ |
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0:01f31e923fe2 | 223 | /* Shadow Trim Registers */ |
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0:01f31e923fe2 | 224 | |
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0:01f31e923fe2 | 225 | #define MXC_BASE_TRIM ((uint32_t)0x40001000UL) |
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0:01f31e923fe2 | 226 | #define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM) |
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0:01f31e923fe2 | 227 | |
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0:01f31e923fe2 | 228 | |
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0:01f31e923fe2 | 229 | |
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0:01f31e923fe2 | 230 | /*******************************************************************************/ |
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0:01f31e923fe2 | 231 | /* Flash Controller */ |
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0:01f31e923fe2 | 232 | |
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0:01f31e923fe2 | 233 | #define MXC_BASE_FLC ((uint32_t)0x40002000UL) |
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0:01f31e923fe2 | 234 | #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) |
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0:01f31e923fe2 | 235 | |
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0:01f31e923fe2 | 236 | #define MXC_FLC_PAGE_SIZE_SHIFT (13) |
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0:01f31e923fe2 | 237 | #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) |
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0:01f31e923fe2 | 238 | #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT |
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0:01f31e923fe2 | 239 | |
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0:01f31e923fe2 | 240 | |
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0:01f31e923fe2 | 241 | |
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0:01f31e923fe2 | 242 | /*******************************************************************************/ |
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0:01f31e923fe2 | 243 | /* Instruction Cache */ |
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0:01f31e923fe2 | 244 | |
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0:01f31e923fe2 | 245 | #define MXC_BASE_ICC ((uint32_t)0x40003000UL) |
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0:01f31e923fe2 | 246 | #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) |
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0:01f31e923fe2 | 247 | |
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0:01f31e923fe2 | 248 | |
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0:01f31e923fe2 | 249 | |
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0:01f31e923fe2 | 250 | /*******************************************************************************/ |
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0:01f31e923fe2 | 251 | /* SPI XIP Interface */ |
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0:01f31e923fe2 | 252 | |
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0:01f31e923fe2 | 253 | #define MXC_BASE_SPIX ((uint32_t)0x40004000UL) |
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0:01f31e923fe2 | 254 | #define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX) |
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0:01f31e923fe2 | 255 | |
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0:01f31e923fe2 | 256 | |
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0:01f31e923fe2 | 257 | |
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0:01f31e923fe2 | 258 | /*******************************************************************************/ |
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0:01f31e923fe2 | 259 | /* Peripheral Management Unit */ |
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0:01f31e923fe2 | 260 | |
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0:01f31e923fe2 | 261 | #define MXC_CFG_PMU_CHANNELS (6) |
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0:01f31e923fe2 | 262 | |
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0:01f31e923fe2 | 263 | #define MXC_BASE_PMU0 ((uint32_t)0x40005000UL) |
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0:01f31e923fe2 | 264 | #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) |
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0:01f31e923fe2 | 265 | #define MXC_BASE_PMU1 ((uint32_t)0x40005020UL) |
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0:01f31e923fe2 | 266 | #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) |
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0:01f31e923fe2 | 267 | #define MXC_BASE_PMU2 ((uint32_t)0x40005040UL) |
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0:01f31e923fe2 | 268 | #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) |
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0:01f31e923fe2 | 269 | #define MXC_BASE_PMU3 ((uint32_t)0x40005060UL) |
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0:01f31e923fe2 | 270 | #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) |
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0:01f31e923fe2 | 271 | #define MXC_BASE_PMU4 ((uint32_t)0x40005080UL) |
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0:01f31e923fe2 | 272 | #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) |
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0:01f31e923fe2 | 273 | #define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL) |
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0:01f31e923fe2 | 274 | #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) |
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0:01f31e923fe2 | 275 | |
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0:01f31e923fe2 | 276 | #define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \ |
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0:01f31e923fe2 | 277 | (i) == 1 ? MXC_BASE_PMU1 : \ |
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0:01f31e923fe2 | 278 | (i) == 2 ? MXC_BASE_PMU2 : \ |
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0:01f31e923fe2 | 279 | (i) == 3 ? MXC_BASE_PMU3 : \ |
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0:01f31e923fe2 | 280 | (i) == 4 ? MXC_BASE_PMU4 : \ |
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0:01f31e923fe2 | 281 | (i) == 5 ? MXC_BASE_PMU5 : 0) |
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0:01f31e923fe2 | 282 | |
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0:01f31e923fe2 | 283 | #define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \ |
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0:01f31e923fe2 | 284 | (i) == 1 ? MXC_PMU1 : \ |
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0:01f31e923fe2 | 285 | (i) == 2 ? MXC_PMU2 : \ |
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0:01f31e923fe2 | 286 | (i) == 3 ? MXC_PMU3 : \ |
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0:01f31e923fe2 | 287 | (i) == 4 ? MXC_PMU4 : \ |
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0:01f31e923fe2 | 288 | (i) == 5 ? MXC_PMU5 : 0) |
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0:01f31e923fe2 | 289 | |
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0:01f31e923fe2 | 290 | #define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \ |
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0:01f31e923fe2 | 291 | (p) == MXC_PMU1 ? 1 : \ |
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0:01f31e923fe2 | 292 | (p) == MXC_PMU2 ? 2 : \ |
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0:01f31e923fe2 | 293 | (p) == MXC_PMU3 ? 3 : \ |
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0:01f31e923fe2 | 294 | (p) == MXC_PMU4 ? 4 : \ |
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0:01f31e923fe2 | 295 | (p) == MXC_PMU5 ? 5 : -1) |
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0:01f31e923fe2 | 296 | |
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0:01f31e923fe2 | 297 | /*******************************************************************************/ |
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0:01f31e923fe2 | 298 | /* USB Device Controller */ |
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0:01f31e923fe2 | 299 | |
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0:01f31e923fe2 | 300 | #define MXC_BASE_USB ((uint32_t)0x40100000UL) |
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0:01f31e923fe2 | 301 | #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) |
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0:01f31e923fe2 | 302 | |
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0:01f31e923fe2 | 303 | #define MXC_USB_MAX_PACKET (64) |
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0:01f31e923fe2 | 304 | #define MXC_USB_NUM_EP (8) |
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0:01f31e923fe2 | 305 | |
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0:01f31e923fe2 | 306 | |
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0:01f31e923fe2 | 307 | |
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0:01f31e923fe2 | 308 | /*******************************************************************************/ |
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0:01f31e923fe2 | 309 | /* CRC-16/CRC-32 Engine */ |
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0:01f31e923fe2 | 310 | |
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0:01f31e923fe2 | 311 | #define MXC_BASE_CRC ((uint32_t)0x40006000UL) |
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0:01f31e923fe2 | 312 | #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) |
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0:01f31e923fe2 | 313 | #define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL) |
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0:01f31e923fe2 | 314 | #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) |
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0:01f31e923fe2 | 315 | |
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0:01f31e923fe2 | 316 | /*******************************************************************************/ |
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0:01f31e923fe2 | 317 | /* Pseudo-random number generator (PRNG) */ |
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0:01f31e923fe2 | 318 | |
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0:01f31e923fe2 | 319 | #define MXC_BASE_PRNG ((uint32_t)0x40007000UL) |
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0:01f31e923fe2 | 320 | #define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG) |
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0:01f31e923fe2 | 321 | |
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0:01f31e923fe2 | 322 | /*******************************************************************************/ |
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0:01f31e923fe2 | 323 | /* AES Cryptographic Engine */ |
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0:01f31e923fe2 | 324 | |
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0:01f31e923fe2 | 325 | #define MXC_BASE_AES ((uint32_t)0x40007400UL) |
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0:01f31e923fe2 | 326 | #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) |
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0:01f31e923fe2 | 327 | #define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL) |
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0:01f31e923fe2 | 328 | #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) |
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0:01f31e923fe2 | 329 | |
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0:01f31e923fe2 | 330 | /*******************************************************************************/ |
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0:01f31e923fe2 | 331 | /* MAA Cryptographic Engine */ |
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0:01f31e923fe2 | 332 | |
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0:01f31e923fe2 | 333 | #define MXC_BASE_MAA ((uint32_t)0x40007800UL) |
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0:01f31e923fe2 | 334 | #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) |
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0:01f31e923fe2 | 335 | #define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL) |
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0:01f31e923fe2 | 336 | #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) |
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0:01f31e923fe2 | 337 | |
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0:01f31e923fe2 | 338 | /*******************************************************************************/ |
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0:01f31e923fe2 | 339 | /* Trust Protection Unit (TPU) */ |
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0:01f31e923fe2 | 340 | |
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0:01f31e923fe2 | 341 | #define MXC_BASE_TPU ((uint32_t)0x40007000UL) |
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0:01f31e923fe2 | 342 | #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) |
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0:01f31e923fe2 | 343 | #define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL) |
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0:01f31e923fe2 | 344 | #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) |
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0:01f31e923fe2 | 345 | |
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0:01f31e923fe2 | 346 | /*******************************************************************************/ |
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0:01f31e923fe2 | 347 | /* Watchdog Timers */ |
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0:01f31e923fe2 | 348 | |
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0:01f31e923fe2 | 349 | #define MXC_CFG_WDT_INSTANCES (2) |
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0:01f31e923fe2 | 350 | |
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0:01f31e923fe2 | 351 | #define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) |
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0:01f31e923fe2 | 352 | #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) |
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0:01f31e923fe2 | 353 | #define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) |
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0:01f31e923fe2 | 354 | #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) |
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0:01f31e923fe2 | 355 | |
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0:01f31e923fe2 | 356 | #define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \ |
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0:01f31e923fe2 | 357 | (i) == 1 ? WDT1_IRQn : 0) |
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0:01f31e923fe2 | 358 | |
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0:01f31e923fe2 | 359 | #define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \ |
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0:01f31e923fe2 | 360 | (i) == 1 ? WDT1_P_IRQn : 0) |
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0:01f31e923fe2 | 361 | |
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0:01f31e923fe2 | 362 | #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ |
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0:01f31e923fe2 | 363 | (i) == 1 ? MXC_BASE_WDT1 : 0) |
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0:01f31e923fe2 | 364 | |
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0:01f31e923fe2 | 365 | #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ |
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0:01f31e923fe2 | 366 | (i) == 1 ? MXC_WDT1 : 0) |
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0:01f31e923fe2 | 367 | |
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0:01f31e923fe2 | 368 | #define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \ |
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0:01f31e923fe2 | 369 | (i) == MXC_WDT1 ? 1: -1) |
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0:01f31e923fe2 | 370 | |
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0:01f31e923fe2 | 371 | |
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0:01f31e923fe2 | 372 | /*******************************************************************************/ |
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0:01f31e923fe2 | 373 | /* Low-Level Watchdog Timer */ |
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0:01f31e923fe2 | 374 | |
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0:01f31e923fe2 | 375 | #define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL) |
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0:01f31e923fe2 | 376 | #define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2) |
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0:01f31e923fe2 | 377 | |
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0:01f31e923fe2 | 378 | |
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0:01f31e923fe2 | 379 | |
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0:01f31e923fe2 | 380 | /*******************************************************************************/ |
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0:01f31e923fe2 | 381 | /* General Purpose I/O Ports (GPIO) */ |
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0:01f31e923fe2 | 382 | |
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0:01f31e923fe2 | 383 | #define MXC_GPIO_NUM_PORTS (5) |
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0:01f31e923fe2 | 384 | #define MXC_GPIO_MAX_PINS_PER_PORT (8) |
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0:01f31e923fe2 | 385 | |
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0:01f31e923fe2 | 386 | #define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) |
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0:01f31e923fe2 | 387 | #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) |
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0:01f31e923fe2 | 388 | |
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0:01f31e923fe2 | 389 | #define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \ |
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0:01f31e923fe2 | 390 | (i) == 1 ? GPIO_P1_IRQn : \ |
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0:01f31e923fe2 | 391 | (i) == 2 ? GPIO_P2_IRQn : \ |
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0:01f31e923fe2 | 392 | (i) == 3 ? GPIO_P3_IRQn : \ |
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0:01f31e923fe2 | 393 | (i) == 4 ? GPIO_P4_IRQn : 0) |
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0:01f31e923fe2 | 394 | |
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0:01f31e923fe2 | 395 | |
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0:01f31e923fe2 | 396 | |
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0:01f31e923fe2 | 397 | /*******************************************************************************/ |
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0:01f31e923fe2 | 398 | /* 16/32 bit Timer/Counters */ |
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0:01f31e923fe2 | 399 | |
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0:01f31e923fe2 | 400 | #define MXC_CFG_TMR_INSTANCES (6) |
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0:01f31e923fe2 | 401 | |
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0:01f31e923fe2 | 402 | #define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) |
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0:01f31e923fe2 | 403 | #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) |
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0:01f31e923fe2 | 404 | #define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) |
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0:01f31e923fe2 | 405 | #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) |
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0:01f31e923fe2 | 406 | #define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) |
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0:01f31e923fe2 | 407 | #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) |
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0:01f31e923fe2 | 408 | #define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) |
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0:01f31e923fe2 | 409 | #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) |
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0:01f31e923fe2 | 410 | #define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) |
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0:01f31e923fe2 | 411 | #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) |
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0:01f31e923fe2 | 412 | #define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) |
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0:01f31e923fe2 | 413 | #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) |
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0:01f31e923fe2 | 414 | |
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0:01f31e923fe2 | 415 | #define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \ |
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0:01f31e923fe2 | 416 | (i) == 1 ? TMR1_0_IRQn : \ |
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0:01f31e923fe2 | 417 | (i) == 2 ? TMR2_0_IRQn : \ |
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0:01f31e923fe2 | 418 | (i) == 3 ? TMR3_0_IRQn : \ |
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0:01f31e923fe2 | 419 | (i) == 4 ? TMR4_0_IRQn : \ |
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0:01f31e923fe2 | 420 | (i) == 5 ? TMR5_0_IRQn : 0) |
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0:01f31e923fe2 | 421 | |
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0:01f31e923fe2 | 422 | #define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \ |
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0:01f31e923fe2 | 423 | (i) == 1 ? TMR1_0_IRQn : \ |
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0:01f31e923fe2 | 424 | (i) == 2 ? TMR2_0_IRQn : \ |
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0:01f31e923fe2 | 425 | (i) == 3 ? TMR3_0_IRQn : \ |
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0:01f31e923fe2 | 426 | (i) == 4 ? TMR4_0_IRQn : \ |
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0:01f31e923fe2 | 427 | (i) == 5 ? TMR5_0_IRQn : \ |
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0:01f31e923fe2 | 428 | (i) == 6 ? TMR0_1_IRQn : \ |
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0:01f31e923fe2 | 429 | (i) == 7 ? TMR1_1_IRQn : \ |
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0:01f31e923fe2 | 430 | (i) == 8 ? TMR2_1_IRQn : \ |
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0:01f31e923fe2 | 431 | (i) == 9 ? TMR3_1_IRQn : \ |
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0:01f31e923fe2 | 432 | (i) == 10 ? TMR4_1_IRQn : \ |
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0:01f31e923fe2 | 433 | (i) == 11 ? TMR5_1_IRQn : 0) |
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0:01f31e923fe2 | 434 | |
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0:01f31e923fe2 | 435 | #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ |
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0:01f31e923fe2 | 436 | (i) == 1 ? MXC_BASE_TMR1 : \ |
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0:01f31e923fe2 | 437 | (i) == 2 ? MXC_BASE_TMR2 : \ |
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0:01f31e923fe2 | 438 | (i) == 3 ? MXC_BASE_TMR3 : \ |
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0:01f31e923fe2 | 439 | (i) == 4 ? MXC_BASE_TMR4 : \ |
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0:01f31e923fe2 | 440 | (i) == 5 ? MXC_BASE_TMR5 : 0) |
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0:01f31e923fe2 | 441 | |
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0:01f31e923fe2 | 442 | #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ |
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0:01f31e923fe2 | 443 | (i) == 1 ? MXC_TMR1 : \ |
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0:01f31e923fe2 | 444 | (i) == 2 ? MXC_TMR2 : \ |
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0:01f31e923fe2 | 445 | (i) == 3 ? MXC_TMR3 : \ |
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0:01f31e923fe2 | 446 | (i) == 4 ? MXC_TMR4 : \ |
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0:01f31e923fe2 | 447 | (i) == 5 ? MXC_TMR5 : 0) |
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0:01f31e923fe2 | 448 | |
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0:01f31e923fe2 | 449 | #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ |
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0:01f31e923fe2 | 450 | (p) == MXC_TMR1 ? 1 : \ |
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0:01f31e923fe2 | 451 | (p) == MXC_TMR2 ? 2 : \ |
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0:01f31e923fe2 | 452 | (p) == MXC_TMR3 ? 3 : \ |
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0:01f31e923fe2 | 453 | (p) == MXC_TMR4 ? 4 : \ |
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0:01f31e923fe2 | 454 | (p) == MXC_TMR5 ? 5 : -1) |
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0:01f31e923fe2 | 455 | |
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0:01f31e923fe2 | 456 | |
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0:01f31e923fe2 | 457 | |
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0:01f31e923fe2 | 458 | |
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0:01f31e923fe2 | 459 | /*******************************************************************************/ |
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0:01f31e923fe2 | 460 | /* Pulse Train Generation */ |
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0:01f31e923fe2 | 461 | |
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0:01f31e923fe2 | 462 | #define MXC_CFG_PT_INSTANCES (16) |
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0:01f31e923fe2 | 463 | |
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0:01f31e923fe2 | 464 | #define MXC_BASE_PTG ((uint32_t)0x40011000UL) |
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0:01f31e923fe2 | 465 | #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) |
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0:01f31e923fe2 | 466 | #define MXC_BASE_PT0 ((uint32_t)0x40011020UL) |
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0:01f31e923fe2 | 467 | #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) |
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0:01f31e923fe2 | 468 | #define MXC_BASE_PT1 ((uint32_t)0x40011040UL) |
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0:01f31e923fe2 | 469 | #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) |
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0:01f31e923fe2 | 470 | #define MXC_BASE_PT2 ((uint32_t)0x40011060UL) |
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0:01f31e923fe2 | 471 | #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) |
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0:01f31e923fe2 | 472 | #define MXC_BASE_PT3 ((uint32_t)0x40011080UL) |
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0:01f31e923fe2 | 473 | #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) |
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0:01f31e923fe2 | 474 | #define MXC_BASE_PT4 ((uint32_t)0x400110A0UL) |
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0:01f31e923fe2 | 475 | #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) |
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0:01f31e923fe2 | 476 | #define MXC_BASE_PT5 ((uint32_t)0x400110C0UL) |
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0:01f31e923fe2 | 477 | #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) |
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0:01f31e923fe2 | 478 | #define MXC_BASE_PT6 ((uint32_t)0x400110E0UL) |
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0:01f31e923fe2 | 479 | #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) |
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0:01f31e923fe2 | 480 | #define MXC_BASE_PT7 ((uint32_t)0x40011100UL) |
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0:01f31e923fe2 | 481 | #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) |
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0:01f31e923fe2 | 482 | #define MXC_BASE_PT8 ((uint32_t)0x40011120UL) |
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0:01f31e923fe2 | 483 | #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8) |
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0:01f31e923fe2 | 484 | #define MXC_BASE_PT9 ((uint32_t)0x40011140UL) |
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0:01f31e923fe2 | 485 | #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9) |
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0:01f31e923fe2 | 486 | #define MXC_BASE_PT10 ((uint32_t)0x40011160UL) |
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0:01f31e923fe2 | 487 | #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10) |
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0:01f31e923fe2 | 488 | #define MXC_BASE_PT11 ((uint32_t)0x40011180UL) |
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0:01f31e923fe2 | 489 | #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11) |
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0:01f31e923fe2 | 490 | #define MXC_BASE_PT12 ((uint32_t)0x400111A0UL) |
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0:01f31e923fe2 | 491 | #define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12) |
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0:01f31e923fe2 | 492 | #define MXC_BASE_PT13 ((uint32_t)0x400111C0UL) |
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0:01f31e923fe2 | 493 | #define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13) |
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0:01f31e923fe2 | 494 | #define MXC_BASE_PT14 ((uint32_t)0x400111E0UL) |
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0:01f31e923fe2 | 495 | #define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14) |
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0:01f31e923fe2 | 496 | #define MXC_BASE_PT15 ((uint32_t)0x40011200UL) |
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0:01f31e923fe2 | 497 | #define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15) |
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0:01f31e923fe2 | 498 | |
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0:01f31e923fe2 | 499 | #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \ |
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0:01f31e923fe2 | 500 | (i) == 1 ? MXC_BASE_PT1 : \ |
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0:01f31e923fe2 | 501 | (i) == 2 ? MXC_BASE_PT2 : \ |
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0:01f31e923fe2 | 502 | (i) == 3 ? MXC_BASE_PT3 : \ |
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0:01f31e923fe2 | 503 | (i) == 4 ? MXC_BASE_PT4 : \ |
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0:01f31e923fe2 | 504 | (i) == 5 ? MXC_BASE_PT5 : \ |
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0:01f31e923fe2 | 505 | (i) == 6 ? MXC_BASE_PT6 : \ |
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0:01f31e923fe2 | 506 | (i) == 7 ? MXC_BASE_PT7 : \ |
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0:01f31e923fe2 | 507 | (i) == 8 ? MXC_BASE_PT8 : \ |
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0:01f31e923fe2 | 508 | (i) == 9 ? MXC_BASE_PT9 : \ |
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0:01f31e923fe2 | 509 | (i) == 10 ? MXC_BASE_PT10 : \ |
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0:01f31e923fe2 | 510 | (i) == 11 ? MXC_BASE_PT11 : \ |
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0:01f31e923fe2 | 511 | (i) == 12 ? MXC_BASE_PT12 : \ |
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0:01f31e923fe2 | 512 | (i) == 13 ? MXC_BASE_PT13 : \ |
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0:01f31e923fe2 | 513 | (i) == 14 ? MXC_BASE_PT14 : \ |
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0:01f31e923fe2 | 514 | (i) == 15 ? MXC_BASE_PT15 : 0) |
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0:01f31e923fe2 | 515 | |
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0:01f31e923fe2 | 516 | #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \ |
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0:01f31e923fe2 | 517 | (i) == 1 ? MXC_PT1 : \ |
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0:01f31e923fe2 | 518 | (i) == 2 ? MXC_PT2 : \ |
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0:01f31e923fe2 | 519 | (i) == 3 ? MXC_PT3 : \ |
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0:01f31e923fe2 | 520 | (i) == 4 ? MXC_PT4 : \ |
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0:01f31e923fe2 | 521 | (i) == 5 ? MXC_PT5 : \ |
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0:01f31e923fe2 | 522 | (i) == 6 ? MXC_PT6 : \ |
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0:01f31e923fe2 | 523 | (i) == 7 ? MXC_PT7 : \ |
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0:01f31e923fe2 | 524 | (i) == 8 ? MXC_PT8 : \ |
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0:01f31e923fe2 | 525 | (i) == 9 ? MXC_PT9 : \ |
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0:01f31e923fe2 | 526 | (i) == 10 ? MXC_PT10 : \ |
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0:01f31e923fe2 | 527 | (i) == 11 ? MXC_PT11 : \ |
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0:01f31e923fe2 | 528 | (i) == 12 ? MXC_PT12 : \ |
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0:01f31e923fe2 | 529 | (i) == 13 ? MXC_PT13 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 530 | (i) == 14 ? MXC_PT14 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 531 | (i) == 15 ? MXC_PT15 : 0) |
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0:01f31e923fe2 | 532 | |
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0:01f31e923fe2 | 533 | #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \ |
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0:01f31e923fe2 | 534 | (p) == MXC_PT1 ? 1 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 535 | (p) == MXC_PT2 ? 2 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 536 | (p) == MXC_PT3 ? 3 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 537 | (p) == MXC_PT4 ? 4 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 538 | (p) == MXC_PT5 ? 5 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 539 | (p) == MXC_PT6 ? 6 : \ |
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0:01f31e923fe2 | 540 | (p) == MXC_PT7 ? 7 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 541 | (p) == MXC_PT8 ? 8 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 542 | (p) == MXC_PT9 ? 9 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 543 | (p) == MXC_PT10 ? 10 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 544 | (p) == MXC_PT11 ? 11 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 545 | (p) == MXC_PT12 ? 12 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 546 | (p) == MXC_PT13 ? 13 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 547 | (p) == MXC_PT14 ? 14 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 548 | (p) == MXC_PT15 ? 15 : -1) |
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0:01f31e923fe2 | 549 | |
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0:01f31e923fe2 | 550 | |
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0:01f31e923fe2 | 551 | |
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0:01f31e923fe2 | 552 | /*******************************************************************************/ |
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0:01f31e923fe2 | 553 | /* UART / Serial Port Interface */ |
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0:01f31e923fe2 | 554 | |
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0:01f31e923fe2 | 555 | #define MXC_CFG_UART_INSTANCES (3) |
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0:01f31e923fe2 | 556 | #define MXC_UART_FIFO_DEPTH (32) |
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0:01f31e923fe2 | 557 | |
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0:01f31e923fe2 | 558 | #define MXC_BASE_UART0 ((uint32_t)0x40012000UL) |
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0:01f31e923fe2 | 559 | #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) |
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0:01f31e923fe2 | 560 | #define MXC_BASE_UART1 ((uint32_t)0x40013000UL) |
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0:01f31e923fe2 | 561 | #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) |
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0:01f31e923fe2 | 562 | #define MXC_BASE_UART2 ((uint32_t)0x40014000UL) |
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0:01f31e923fe2 | 563 | #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) |
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0:01f31e923fe2 | 564 | #define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL) |
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0:01f31e923fe2 | 565 | #define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO) |
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0:01f31e923fe2 | 566 | #define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL) |
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0:01f31e923fe2 | 567 | #define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO) |
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0:01f31e923fe2 | 568 | #define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL) |
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0:01f31e923fe2 | 569 | #define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO) |
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0:01f31e923fe2 | 570 | |
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0:01f31e923fe2 | 571 | #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 572 | (i) == 1 ? UART1_IRQn : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 573 | (i) == 2 ? UART2_IRQn : 0) |
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0:01f31e923fe2 | 574 | |
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0:01f31e923fe2 | 575 | #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 576 | (i) == 1 ? MXC_BASE_UART1 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 577 | (i) == 2 ? MXC_BASE_UART2 : 0) |
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0:01f31e923fe2 | 578 | |
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0:01f31e923fe2 | 579 | #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 580 | (i) == 1 ? MXC_UART1 : \ |
| Pawel Zarembski |
0:01f31e923fe2 | 581 | (i) == 2 ? MXC_UART2 : 0) |
| Pawel Zarembski |
0:01f31e923fe2 | 582 | |
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0:01f31e923fe2 | 583 | #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ |
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0:01f31e923fe2 | 584 | (p) == MXC_UART1 ? 1 : \ |
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0:01f31e923fe2 | 585 | (p) == MXC_UART2 ? 2 : -1) |
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0:01f31e923fe2 | 586 | |
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0:01f31e923fe2 | 587 | #define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \ |
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0:01f31e923fe2 | 588 | (i) == 1 ? MXC_BASE_UART1_FIFO : \ |
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0:01f31e923fe2 | 589 | (i) == 2 ? MXC_BASE_UART2_FIFO : 0) |
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0:01f31e923fe2 | 590 | |
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0:01f31e923fe2 | 591 | #define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \ |
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0:01f31e923fe2 | 592 | (i) == 1 ? MXC_UART1_FIFO : \ |
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0:01f31e923fe2 | 593 | (i) == 2 ? MXC_UART2_FIFO : 0) |
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0:01f31e923fe2 | 594 | |
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0:01f31e923fe2 | 595 | |
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0:01f31e923fe2 | 596 | |
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0:01f31e923fe2 | 597 | /*******************************************************************************/ |
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0:01f31e923fe2 | 598 | /* I2C Master Interface */ |
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0:01f31e923fe2 | 599 | |
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0:01f31e923fe2 | 600 | #define MXC_CFG_I2CM_INSTANCES (2) |
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0:01f31e923fe2 | 601 | #define MXC_I2CM_FIFO_DEPTH (8) |
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0:01f31e923fe2 | 602 | |
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0:01f31e923fe2 | 603 | #define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL) |
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0:01f31e923fe2 | 604 | #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) |
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0:01f31e923fe2 | 605 | #define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL) |
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0:01f31e923fe2 | 606 | #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) |
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0:01f31e923fe2 | 607 | #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL) |
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0:01f31e923fe2 | 608 | #define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO) |
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0:01f31e923fe2 | 609 | #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL) |
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0:01f31e923fe2 | 610 | #define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO) |
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0:01f31e923fe2 | 611 | |
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0:01f31e923fe2 | 612 | #define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \ |
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0:01f31e923fe2 | 613 | (i) == 1 ? I2CM1_IRQn : 0) |
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0:01f31e923fe2 | 614 | |
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0:01f31e923fe2 | 615 | #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ |
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0:01f31e923fe2 | 616 | (i) == 1 ? MXC_BASE_I2CM1 : 0) |
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0:01f31e923fe2 | 617 | |
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0:01f31e923fe2 | 618 | #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ |
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0:01f31e923fe2 | 619 | (i) == 1 ? MXC_I2CM1 : 0) |
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0:01f31e923fe2 | 620 | |
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0:01f31e923fe2 | 621 | #define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \ |
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0:01f31e923fe2 | 622 | (p) == MXC_I2CM1 ? 1 : -1) |
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0:01f31e923fe2 | 623 | |
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0:01f31e923fe2 | 624 | #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \ |
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0:01f31e923fe2 | 625 | (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0) |
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0:01f31e923fe2 | 626 | |
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0:01f31e923fe2 | 627 | #define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \ |
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0:01f31e923fe2 | 628 | (i) == 1 ? MXC_I2CM1_FIFO : 0) |
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0:01f31e923fe2 | 629 | |
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0:01f31e923fe2 | 630 | |
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0:01f31e923fe2 | 631 | |
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0:01f31e923fe2 | 632 | /*******************************************************************************/ |
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0:01f31e923fe2 | 633 | /* I2C Slave Interface (Mailbox type) */ |
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0:01f31e923fe2 | 634 | |
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0:01f31e923fe2 | 635 | #define MXC_CFG_I2CS_INSTANCES (1) |
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0:01f31e923fe2 | 636 | #define MXC_CFG_I2CS_BUFFER_SIZE (32) |
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0:01f31e923fe2 | 637 | |
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0:01f31e923fe2 | 638 | #define MXC_BASE_I2CS ((uint32_t)0x40019000UL) |
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0:01f31e923fe2 | 639 | #define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS) |
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0:01f31e923fe2 | 640 | |
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0:01f31e923fe2 | 641 | #define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0) |
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0:01f31e923fe2 | 642 | |
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0:01f31e923fe2 | 643 | #define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0) |
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0:01f31e923fe2 | 644 | |
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0:01f31e923fe2 | 645 | #define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0) |
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0:01f31e923fe2 | 646 | |
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0:01f31e923fe2 | 647 | #define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1) |
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0:01f31e923fe2 | 648 | |
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0:01f31e923fe2 | 649 | /*******************************************************************************/ |
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0:01f31e923fe2 | 650 | /* SPI Master Interface */ |
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0:01f31e923fe2 | 651 | |
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0:01f31e923fe2 | 652 | #define MXC_CFG_SPIM_INSTANCES (3) |
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0:01f31e923fe2 | 653 | #define MXC_CFG_SPIM_FIFO_DEPTH (16) |
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0:01f31e923fe2 | 654 | |
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0:01f31e923fe2 | 655 | #define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL) |
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0:01f31e923fe2 | 656 | #define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0) |
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0:01f31e923fe2 | 657 | #define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL) |
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0:01f31e923fe2 | 658 | #define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1) |
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0:01f31e923fe2 | 659 | #define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL) |
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0:01f31e923fe2 | 660 | #define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2) |
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0:01f31e923fe2 | 661 | #define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL) |
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0:01f31e923fe2 | 662 | #define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO) |
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0:01f31e923fe2 | 663 | #define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL) |
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0:01f31e923fe2 | 664 | #define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO) |
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0:01f31e923fe2 | 665 | #define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL) |
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0:01f31e923fe2 | 666 | #define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO) |
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0:01f31e923fe2 | 667 | |
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0:01f31e923fe2 | 668 | #define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \ |
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0:01f31e923fe2 | 669 | (i) == 1 ? SPIM1_IRQn : \ |
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0:01f31e923fe2 | 670 | (i) == 2 ? SPIM2_IRQn : 0) |
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0:01f31e923fe2 | 671 | |
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0:01f31e923fe2 | 672 | #define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \ |
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0:01f31e923fe2 | 673 | (i) == 1 ? MXC_BASE_SPIM1 : \ |
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0:01f31e923fe2 | 674 | (i) == 2 ? MXC_BASE_SPIM2 : 0) |
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0:01f31e923fe2 | 675 | |
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0:01f31e923fe2 | 676 | #define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \ |
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0:01f31e923fe2 | 677 | (i) == 1 ? MXC_SPIM1 : \ |
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0:01f31e923fe2 | 678 | (i) == 2 ? MXC_SPIM2 : 0) |
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0:01f31e923fe2 | 679 | |
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0:01f31e923fe2 | 680 | #define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \ |
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0:01f31e923fe2 | 681 | (p) == MXC_SPIM1 ? 1 : \ |
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0:01f31e923fe2 | 682 | (p) == MXC_SPIM2 ? 2 : -1) |
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0:01f31e923fe2 | 683 | |
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0:01f31e923fe2 | 684 | #define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \ |
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0:01f31e923fe2 | 685 | (i) == 1 ? MXC_BASE_SPIM1_FIFO : \ |
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0:01f31e923fe2 | 686 | (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0) |
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0:01f31e923fe2 | 687 | |
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0:01f31e923fe2 | 688 | #define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \ |
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0:01f31e923fe2 | 689 | (i) == 1 ? MXC_SPIM1_FIFO : \ |
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0:01f31e923fe2 | 690 | (i) == 2 ? MXC_SPIM2_FIFO : 0) |
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0:01f31e923fe2 | 691 | |
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0:01f31e923fe2 | 692 | |
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0:01f31e923fe2 | 693 | |
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0:01f31e923fe2 | 694 | /*******************************************************************************/ |
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0:01f31e923fe2 | 695 | /* 1-Wire Master Interface */ |
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0:01f31e923fe2 | 696 | |
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0:01f31e923fe2 | 697 | #define MXC_CFG_OWM_INSTANCES (1) |
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0:01f31e923fe2 | 698 | |
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0:01f31e923fe2 | 699 | #define MXC_BASE_OWM ((uint32_t)0x4001E000UL) |
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0:01f31e923fe2 | 700 | #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) |
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0:01f31e923fe2 | 701 | |
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0:01f31e923fe2 | 702 | #define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0) |
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0:01f31e923fe2 | 703 | |
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0:01f31e923fe2 | 704 | #define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0) |
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0:01f31e923fe2 | 705 | |
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0:01f31e923fe2 | 706 | #define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0) |
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0:01f31e923fe2 | 707 | |
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0:01f31e923fe2 | 708 | #define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1) |
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0:01f31e923fe2 | 709 | |
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0:01f31e923fe2 | 710 | /*******************************************************************************/ |
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0:01f31e923fe2 | 711 | /* ADC / AFE */ |
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0:01f31e923fe2 | 712 | |
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0:01f31e923fe2 | 713 | #define MXC_CFG_ADC_FIFO_DEPTH (32) |
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0:01f31e923fe2 | 714 | |
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0:01f31e923fe2 | 715 | #define MXC_BASE_ADC ((uint32_t)0x4001F000UL) |
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0:01f31e923fe2 | 716 | #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) |
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0:01f31e923fe2 | 717 | |
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0:01f31e923fe2 | 718 | |
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0:01f31e923fe2 | 719 | |
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0:01f31e923fe2 | 720 | /*******************************************************************************/ |
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0:01f31e923fe2 | 721 | /* SPI Slave Interface */ |
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0:01f31e923fe2 | 722 | #define MXC_CFG_SPIS_INSTANCES (1) |
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0:01f31e923fe2 | 723 | #define MXC_CFG_SPIS_FIFO_DEPTH (32) |
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0:01f31e923fe2 | 724 | |
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0:01f31e923fe2 | 725 | #define MXC_BASE_SPIS ((uint32_t)0x40020000UL) |
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0:01f31e923fe2 | 726 | #define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS) |
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0:01f31e923fe2 | 727 | #define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL) |
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0:01f31e923fe2 | 728 | #define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO) |
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0:01f31e923fe2 | 729 | |
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0:01f31e923fe2 | 730 | #define MXC_SPIS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0) |
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0:01f31e923fe2 | 731 | |
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0:01f31e923fe2 | 732 | #define MXC_SPIS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIS : 0) |
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0:01f31e923fe2 | 733 | |
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0:01f31e923fe2 | 734 | #define MXC_SPIS_GET_SPIS(i) ((i) == 0 ? MXC_SPIS : 0) |
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0:01f31e923fe2 | 735 | |
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0:01f31e923fe2 | 736 | #define MXC_SPIS_GET_IDX(p) ((p) == MXC_SPIS ? 0 : -1) |
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0:01f31e923fe2 | 737 | |
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0:01f31e923fe2 | 738 | #define MXC_SPIS_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0) |
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0:01f31e923fe2 | 739 | |
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0:01f31e923fe2 | 740 | #define MXC_SPIS_GET_SPIS_FIFO(i) ((i) == 0 ? MXC_SPIS_FIFO :0) |
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0:01f31e923fe2 | 741 | |
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0:01f31e923fe2 | 742 | /*******************************************************************************/ |
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0:01f31e923fe2 | 743 | /* Bit Shifting */ |
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0:01f31e923fe2 | 744 | |
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0:01f31e923fe2 | 745 | #define MXC_F_BIT_0 (1 << 0) |
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0:01f31e923fe2 | 746 | #define MXC_F_BIT_1 (1 << 1) |
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0:01f31e923fe2 | 747 | #define MXC_F_BIT_2 (1 << 2) |
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0:01f31e923fe2 | 748 | #define MXC_F_BIT_3 (1 << 3) |
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0:01f31e923fe2 | 749 | #define MXC_F_BIT_4 (1 << 4) |
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0:01f31e923fe2 | 750 | #define MXC_F_BIT_5 (1 << 5) |
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0:01f31e923fe2 | 751 | #define MXC_F_BIT_6 (1 << 6) |
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0:01f31e923fe2 | 752 | #define MXC_F_BIT_7 (1 << 7) |
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0:01f31e923fe2 | 753 | #define MXC_F_BIT_8 (1 << 8) |
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0:01f31e923fe2 | 754 | #define MXC_F_BIT_9 (1 << 9) |
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0:01f31e923fe2 | 755 | #define MXC_F_BIT_10 (1 << 10) |
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0:01f31e923fe2 | 756 | #define MXC_F_BIT_11 (1 << 11) |
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0:01f31e923fe2 | 757 | #define MXC_F_BIT_12 (1 << 12) |
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0:01f31e923fe2 | 758 | #define MXC_F_BIT_13 (1 << 13) |
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0:01f31e923fe2 | 759 | #define MXC_F_BIT_14 (1 << 14) |
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0:01f31e923fe2 | 760 | #define MXC_F_BIT_15 (1 << 15) |
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0:01f31e923fe2 | 761 | #define MXC_F_BIT_16 (1 << 16) |
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0:01f31e923fe2 | 762 | #define MXC_F_BIT_17 (1 << 17) |
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0:01f31e923fe2 | 763 | #define MXC_F_BIT_18 (1 << 18) |
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0:01f31e923fe2 | 764 | #define MXC_F_BIT_19 (1 << 19) |
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0:01f31e923fe2 | 765 | #define MXC_F_BIT_20 (1 << 20) |
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0:01f31e923fe2 | 766 | #define MXC_F_BIT_21 (1 << 21) |
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0:01f31e923fe2 | 767 | #define MXC_F_BIT_22 (1 << 22) |
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0:01f31e923fe2 | 768 | #define MXC_F_BIT_23 (1 << 23) |
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0:01f31e923fe2 | 769 | #define MXC_F_BIT_24 (1 << 24) |
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0:01f31e923fe2 | 770 | #define MXC_F_BIT_25 (1 << 25) |
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0:01f31e923fe2 | 771 | #define MXC_F_BIT_26 (1 << 26) |
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0:01f31e923fe2 | 772 | #define MXC_F_BIT_27 (1 << 27) |
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0:01f31e923fe2 | 773 | #define MXC_F_BIT_28 (1 << 28) |
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0:01f31e923fe2 | 774 | #define MXC_F_BIT_29 (1 << 29) |
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0:01f31e923fe2 | 775 | #define MXC_F_BIT_30 (1 << 30) |
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0:01f31e923fe2 | 776 | #define MXC_F_BIT_31 (1 << 31) |
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0:01f31e923fe2 | 777 | |
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0:01f31e923fe2 | 778 | |
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0:01f31e923fe2 | 779 | /*******************************************************************************/ |
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0:01f31e923fe2 | 780 | |
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0:01f31e923fe2 | 781 | #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) |
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0:01f31e923fe2 | 782 | #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) |
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0:01f31e923fe2 | 783 | #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) |
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0:01f31e923fe2 | 784 | #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) |
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0:01f31e923fe2 | 785 | |
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0:01f31e923fe2 | 786 | |
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0:01f31e923fe2 | 787 | /*******************************************************************************/ |
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0:01f31e923fe2 | 788 | |
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0:01f31e923fe2 | 789 | /* SCB CPACR Register Definitions */ |
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0:01f31e923fe2 | 790 | /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ |
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0:01f31e923fe2 | 791 | #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ |
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0:01f31e923fe2 | 792 | #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ |
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0:01f31e923fe2 | 793 | #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ |
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0:01f31e923fe2 | 794 | #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ |
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0:01f31e923fe2 | 795 | |
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0:01f31e923fe2 | 796 | #endif /* _MAX32625_H_ */ |