Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/gpio_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* **************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 32 | *************************************************************************** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 33 | |
| Pawel Zarembski |
0:01f31e923fe2 | 34 | /* Define to prevent redundant inclusion */ |
| Pawel Zarembski |
0:01f31e923fe2 | 35 | #ifndef _MXC_GPIO_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 36 | #define _MXC_GPIO_REGS_H_ |
| Pawel Zarembski |
0:01f31e923fe2 | 37 | |
| Pawel Zarembski |
0:01f31e923fe2 | 38 | /* **** Includes **** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 39 | #include <stdint.h> |
| Pawel Zarembski |
0:01f31e923fe2 | 40 | |
| Pawel Zarembski |
0:01f31e923fe2 | 41 | #ifdef __cplusplus |
| Pawel Zarembski |
0:01f31e923fe2 | 42 | extern "C" { |
| Pawel Zarembski |
0:01f31e923fe2 | 43 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 44 | |
| Pawel Zarembski |
0:01f31e923fe2 | 45 | ///@cond |
| Pawel Zarembski |
0:01f31e923fe2 | 46 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 47 | If types are not defined elsewhere (CMSIS) define them here |
| Pawel Zarembski |
0:01f31e923fe2 | 48 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 49 | #ifndef __IO |
| Pawel Zarembski |
0:01f31e923fe2 | 50 | #define __IO volatile |
| Pawel Zarembski |
0:01f31e923fe2 | 51 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 52 | #ifndef __I |
| Pawel Zarembski |
0:01f31e923fe2 | 53 | #define __I volatile const |
| Pawel Zarembski |
0:01f31e923fe2 | 54 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 55 | #ifndef __O |
| Pawel Zarembski |
0:01f31e923fe2 | 56 | #define __O volatile |
| Pawel Zarembski |
0:01f31e923fe2 | 57 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 58 | #ifndef __R |
| Pawel Zarembski |
0:01f31e923fe2 | 59 | #define __R volatile const |
| Pawel Zarembski |
0:01f31e923fe2 | 60 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 61 | ///@endcond |
| Pawel Zarembski |
0:01f31e923fe2 | 62 | |
| Pawel Zarembski |
0:01f31e923fe2 | 63 | /* **** Definitions **** */ |
| Pawel Zarembski |
0:01f31e923fe2 | 64 | |
| Pawel Zarembski |
0:01f31e923fe2 | 65 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 66 | * @defgroup gpio_registers Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 67 | * @ingroup gpio |
| Pawel Zarembski |
0:01f31e923fe2 | 68 | * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. |
| Pawel Zarembski |
0:01f31e923fe2 | 69 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 70 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 71 | |
| Pawel Zarembski |
0:01f31e923fe2 | 72 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 73 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Pawel Zarembski |
0:01f31e923fe2 | 74 | access to each register in module. |
| Pawel Zarembski |
0:01f31e923fe2 | 75 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 76 | |
| Pawel Zarembski |
0:01f31e923fe2 | 77 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 78 | * Structure type to access the GPIO Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 79 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 80 | typedef struct { |
| Pawel Zarembski |
0:01f31e923fe2 | 81 | __IO uint32_t rst_mode[16]; /**< <tt>\b 0x0000-0x003C</tt> GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 82 | __IO uint32_t free[16]; /**< <tt>\b 0x0040-0x007C</tt> GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */ |
| Pawel Zarembski |
0:01f31e923fe2 | 83 | __IO uint32_t out_mode[16]; /**< <tt>\b 0x0080-0x00BC</tt> GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 84 | __IO uint32_t out_val[16]; /**< <tt>\b 0x00C0-0x00FC</tt> GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 85 | __IO uint32_t func_sel[16]; /**< <tt>\b 0x0100-0x013C</tt> GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */ |
| Pawel Zarembski |
0:01f31e923fe2 | 86 | __IO uint32_t in_mode[16]; /**< <tt>\b 0x0140-0x017C</tt> GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 87 | __IO uint32_t in_val[16]; /**< <tt>\b 0x0180-0x01BC</tt> GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */ |
| Pawel Zarembski |
0:01f31e923fe2 | 88 | __IO uint32_t int_mode[16]; /**< <tt>\b 0x01C0-0x01FC</tt> GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 89 | __IO uint32_t intfl[16]; /**< <tt>\b 0x0200-0x023C</tt> GPIO_INTFL_P[0..15] Registers - Interrupt Flags */ |
| Pawel Zarembski |
0:01f31e923fe2 | 90 | __IO uint32_t inten[16]; /**< <tt>\b 0x0240-0x027C</tt> GPIO_INTEN_P[0..15] Registers - Interrupt Enables */ |
| Pawel Zarembski |
0:01f31e923fe2 | 91 | } mxc_gpio_regs_t; |
| Pawel Zarembski |
0:01f31e923fe2 | 92 | /**@} end of gpio_registers group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 93 | |
| Pawel Zarembski |
0:01f31e923fe2 | 94 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 95 | Register offsets for module GPIO. |
| Pawel Zarembski |
0:01f31e923fe2 | 96 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 97 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 98 | * @defgroup GPIO_Register_Offsets Register Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 99 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 100 | * @brief GPIO Register Offsets from the GPIO Base Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 101 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 102 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 103 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 104 | * @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 105 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 106 | * @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 107 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 108 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 109 | #define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>\b 0x0000</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 110 | #define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>\b 0x0004</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 111 | #define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>\b 0x0008</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 112 | #define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>\b 0x000C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 113 | #define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>\b 0x0010</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 114 | #define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>\b 0x0014</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 115 | #define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>\b 0x0018</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 116 | #define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>\b 0x001C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 117 | #define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>\b 0x0020</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 118 | #define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>\b 0x0024</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 119 | #define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>\b 0x0028</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 120 | #define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>\b 0x002C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 121 | #define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt>\b 0x0030</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 122 | #define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>\b 0x0034</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 123 | #define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>\b 0x0038</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 124 | #define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>\b 0x003C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 125 | /**@} end of gpio_rst_mode group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 126 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 127 | * @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 128 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 129 | * @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 130 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 131 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 132 | #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>\b 0x0040</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 133 | #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: <tt>\b 0x0044</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 134 | #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>\b 0x0048</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 135 | #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>\b 0x004C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 136 | #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>\b 0x0050</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 137 | #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>\b 0x0054</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 138 | #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: <tt>\b 0x0058</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 139 | #define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>\b 0x005C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 140 | #define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>\b 0x0060</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 141 | #define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>\b 0x0064</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 142 | #define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>\b 0x0068</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 143 | #define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>\b 0x006C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 144 | #define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>\b 0x0070</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 145 | #define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>\b 0x0074</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 146 | #define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>\b 0x0078</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 147 | #define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>\b 0x007C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 148 | /**@} end of gpio_free group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 149 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 150 | * @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 151 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 152 | * @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 153 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 154 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 155 | #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt>\b 0x0080</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 156 | #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt>\b 0x0084</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 157 | #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt>\b 0x0088</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 158 | #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: <tt>\b 0x008C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 159 | #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: <tt>\b 0x0090</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 160 | #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: <tt>\b 0x0094</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 161 | #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: <tt>\b 0x0098</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 162 | #define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: <tt>\b 0x009C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 163 | #define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 164 | #define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 165 | #define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 166 | #define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x00AC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 167 | #define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 168 | #define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 169 | #define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 170 | #define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00BC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 171 | /**@} end of gpio_out_mode group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 172 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 173 | * @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 174 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 175 | * @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 176 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 177 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 178 | #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 179 | #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 180 | #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 181 | #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00CC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 182 | #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 183 | #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 184 | #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 185 | #define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00DC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 186 | #define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 187 | #define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 188 | #define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 189 | #define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x00EC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 190 | #define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 191 | #define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 192 | #define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 193 | #define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00FC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 194 | /**@} end of gpio_out_val group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 195 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 196 | * @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 197 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 198 | * @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 199 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 200 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 201 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: <tt>\b 0x0100</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 202 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: <tt>\b 0x0104</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 203 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: <tt>\b 0x0108</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 204 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: <tt>\b 0x010C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 205 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: <tt>\b 0x0110</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 206 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: <tt>\b 0x0114</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 207 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: <tt>\b 0x0118</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 208 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: <tt>\b 0x011C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 209 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: <tt>\b 0x0120</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 210 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: <tt>\b 0x0124</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 211 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: <tt>\b 0x0128</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 212 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: <tt>\b 0x012C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 213 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: <tt>\b 0x0130</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 214 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: <tt>\b 0x0134</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 215 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: <tt>\b 0x0138</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 216 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: <tt>\b 0x013C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 217 | /**@} end of gpio_func_sel */ |
| Pawel Zarembski |
0:01f31e923fe2 | 218 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 219 | * @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 220 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 221 | * @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 222 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 223 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 224 | #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: <tt>\b 0x0140</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 225 | #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: <tt>\b 0x0144</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 226 | #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: <tt>\b 0x0148</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 227 | #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: <tt>\b 0x014C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 228 | #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: <tt>\b 0x0150</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 229 | #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: <tt>\b 0x0154</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 230 | #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: <tt>\b 0x0158</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 231 | #define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: <tt>\b 0x015C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 232 | #define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: <tt>\b 0x0160</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 233 | #define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: <tt>\b 0x0164</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 234 | #define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: <tt>\b 0x0168</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 235 | #define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: <tt>\b 0x016C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 236 | #define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: <tt>\b 0x0170</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 237 | #define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: <tt>\b 0x0174</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 238 | #define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: <tt>\b 0x0178</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 239 | #define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: <tt>\b 0x017C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 240 | /**@} end of gpio_in_mode group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 241 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 242 | * @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 243 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 244 | * @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 245 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 246 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 247 | #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: <tt>\b 0x0180</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 248 | #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: <tt>\b 0x0184</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 249 | #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: <tt>\b 0x0188</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 250 | #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: <tt>\b 0x018C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 251 | #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: <tt>\b 0x0190</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 252 | #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: <tt>\b 0x0194</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 253 | #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: <tt>\b 0x0198</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 254 | #define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: <tt>\b 0x019C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 255 | #define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 256 | #define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 257 | #define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 258 | #define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x01AC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 259 | #define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 260 | #define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 261 | #define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 262 | #define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01BC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 263 | /**@} end of gpio_in_val group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 264 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 265 | * @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 266 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 267 | * @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 268 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 269 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 270 | #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 271 | #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 272 | #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 273 | #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01CC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 274 | #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 275 | #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 276 | #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 277 | #define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01DC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 278 | #define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 279 | #define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 280 | #define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 281 | #define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x01EC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 282 | #define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F0</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 283 | #define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F4</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 284 | #define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F8</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 285 | #define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01FC</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 286 | /**@} end of gpio_int_mode group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 287 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 288 | * @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 289 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 290 | * @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 291 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 292 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 293 | #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: <tt>\b 0x0200</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 294 | #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: <tt>\b 0x0204</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 295 | #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: <tt>\b 0x0208</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 296 | #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: <tt>\b 0x020C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 297 | #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: <tt>\b 0x0210</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 298 | #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: <tt>\b 0x0214</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 299 | #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: <tt>\b 0x0218</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 300 | #define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: <tt>\b 0x021C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 301 | #define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: <tt>\b 0x0220</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 302 | #define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: <tt>\b 0x0224</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 303 | #define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: <tt>\b 0x0228</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 304 | #define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: <tt>\b 0x022C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 305 | #define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: <tt>\b 0x0230</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 306 | #define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: <tt>\b 0x0234</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 307 | #define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: <tt>\b 0x0238</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 308 | #define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: <tt>\b 0x023C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 309 | /**@} end of gpio_int_flag group */ |
| Pawel Zarembski |
0:01f31e923fe2 | 310 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 311 | * @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers |
| Pawel Zarembski |
0:01f31e923fe2 | 312 | * @ingroup GPIO_Register_Offsets |
| Pawel Zarembski |
0:01f31e923fe2 | 313 | * @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address. |
| Pawel Zarembski |
0:01f31e923fe2 | 314 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 315 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 316 | #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: <tt>\b 0x0240</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 317 | #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: <tt>\b 0x0244</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 318 | #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: <tt>\b 0x0248</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 319 | #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: <tt>\b 0x024C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 320 | #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: <tt>\b 0x0250</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 321 | #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: <tt>\b 0x0254</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 322 | #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: <tt>\b 0x0258</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 323 | #define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: <tt>\b 0x025C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 324 | #define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: <tt>\b 0x0260</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 325 | #define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: <tt>\b 0x0264</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 326 | #define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: <tt>\b 0x0268</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 327 | #define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: <tt>\b 0x026C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 328 | #define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: <tt>\b 0x0270</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 329 | #define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: <tt>\b 0x0274</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 330 | #define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: <tt>\b 0x0278</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 331 | #define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: <tt>\b 0x027C</tt> */ |
| Pawel Zarembski |
0:01f31e923fe2 | 332 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 333 | /**@} end of GPIO_Register_Offsets */ |
| Pawel Zarembski |
0:01f31e923fe2 | 334 | |
| Pawel Zarembski |
0:01f31e923fe2 | 335 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 336 | Field positions and masks for module GPIO. |
| Pawel Zarembski |
0:01f31e923fe2 | 337 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 338 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 339 | * @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE |
| Pawel Zarembski |
0:01f31e923fe2 | 340 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 341 | * @brief Field Positions and Bit Masks for the GPIO_RST_MODE register. |
| Pawel Zarembski |
0:01f31e923fe2 | 342 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 343 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 344 | #define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 345 | #define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 346 | #define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 347 | #define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 348 | #define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 349 | #define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 350 | #define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 351 | #define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 352 | #define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 353 | #define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 354 | #define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 355 | #define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 356 | #define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 357 | #define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 358 | #define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 359 | #define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 360 | /**@} end of group GPIO_FREE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 361 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 362 | * @defgroup GPIO_FREE_Register GPIO_FREE |
| Pawel Zarembski |
0:01f31e923fe2 | 363 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 364 | * @brief Field Positions and Bit Masks for the GPIO_FREE register. |
| Pawel Zarembski |
0:01f31e923fe2 | 365 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 366 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 367 | #define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 368 | #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 369 | #define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 370 | #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 371 | #define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 372 | #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 373 | #define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 374 | #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 375 | #define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 376 | #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 377 | #define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 378 | #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 379 | #define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 380 | #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 381 | #define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 382 | #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 383 | /**@} end of group GPIO_FREE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 384 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 385 | * @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE |
| Pawel Zarembski |
0:01f31e923fe2 | 386 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 387 | * @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register. |
| Pawel Zarembski |
0:01f31e923fe2 | 388 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 389 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 390 | #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 391 | #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 392 | #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 393 | #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 394 | #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 395 | #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 396 | #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 397 | #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 398 | #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 399 | #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 400 | #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 401 | #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 402 | #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 403 | #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 404 | #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 405 | #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 406 | /**@} end of group GPIO_OUT_MODE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 407 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 408 | * @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL |
| Pawel Zarembski |
0:01f31e923fe2 | 409 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 410 | * @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register. |
| Pawel Zarembski |
0:01f31e923fe2 | 411 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 412 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 413 | #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 414 | #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 415 | #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 416 | #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 417 | #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 418 | #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 419 | #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 420 | #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 421 | #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 422 | #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 423 | #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 424 | #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 425 | #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 426 | #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 427 | #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 428 | #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 429 | /**@} end of group GPIO_OUT_VAL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 430 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 431 | * @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL |
| Pawel Zarembski |
0:01f31e923fe2 | 432 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 433 | * @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register. |
| Pawel Zarembski |
0:01f31e923fe2 | 434 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 435 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 436 | #define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 437 | #define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 438 | #define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 439 | #define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 440 | #define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 441 | #define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 442 | #define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 443 | #define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 444 | #define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 445 | #define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 446 | #define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 447 | #define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 448 | #define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 449 | #define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 450 | #define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 451 | #define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 452 | /**@} end of group GPIO_FUNC_SEL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 453 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 454 | * @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE |
| Pawel Zarembski |
0:01f31e923fe2 | 455 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 456 | * @brief Field Positions and Bit Masks for the GPIO_IN_MODE register. |
| Pawel Zarembski |
0:01f31e923fe2 | 457 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 458 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 459 | #define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 460 | #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 461 | #define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 462 | #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 463 | #define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 464 | #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 465 | #define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 466 | #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 467 | #define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 468 | #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 469 | #define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 470 | #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 471 | #define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 472 | #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 473 | #define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 474 | #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 475 | /**@} end of group GPIO_IN_MODE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 476 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 477 | * @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL |
| Pawel Zarembski |
0:01f31e923fe2 | 478 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 479 | * @brief Field Positions and Bit Masks for the GPIO_IN_VAL register. |
| Pawel Zarembski |
0:01f31e923fe2 | 480 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 481 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 482 | #define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 483 | #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 484 | #define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 485 | #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 486 | #define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 487 | #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 488 | #define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 489 | #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 490 | #define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 491 | #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 492 | #define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 493 | #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 494 | #define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 495 | #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 496 | #define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 497 | #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 498 | /**@} end of group GPIO_IN_VAL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 499 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 500 | * @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE |
| Pawel Zarembski |
0:01f31e923fe2 | 501 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 502 | * @brief Field Positions and Bit Masks for the GPIO_INT_MODE register. |
| Pawel Zarembski |
0:01f31e923fe2 | 503 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 504 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 505 | #define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 506 | #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 507 | #define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 508 | #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 509 | #define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 510 | #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 511 | #define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 512 | #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 513 | #define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 514 | #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 515 | #define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 516 | #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 517 | #define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 518 | #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 519 | #define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 520 | #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 521 | /**@} end of group GPIO_INT_MODE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 522 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 523 | * @defgroup GPIO_INTFL_Register GPIO_INTFL |
| Pawel Zarembski |
0:01f31e923fe2 | 524 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 525 | * @brief Field Positions and Bit Masks for the GPIO_INTFL register. |
| Pawel Zarembski |
0:01f31e923fe2 | 526 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 527 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 528 | #define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 529 | #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 530 | #define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 531 | #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 532 | #define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 533 | #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 534 | #define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 535 | #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 536 | #define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 537 | #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 538 | #define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 539 | #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 540 | #define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 541 | #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 542 | #define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 543 | #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 544 | /**@} end of group GPIO_INTFL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 545 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 546 | * @defgroup GPIO_INTEN_Register GPIO_INTEN |
| Pawel Zarembski |
0:01f31e923fe2 | 547 | * @ingroup gpio_registers |
| Pawel Zarembski |
0:01f31e923fe2 | 548 | * @brief Field Positions and Bit Masks for the GPIO_INTEN register. |
| Pawel Zarembski |
0:01f31e923fe2 | 549 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 550 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 551 | #define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 552 | #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 553 | #define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 554 | #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 555 | #define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 556 | #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 557 | #define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 558 | #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 559 | #define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 560 | #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 561 | #define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 562 | #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 563 | #define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 564 | #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 565 | #define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */ |
| Pawel Zarembski |
0:01f31e923fe2 | 566 | #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */ |
| Pawel Zarembski |
0:01f31e923fe2 | 567 | /**@} end group GPIO_INTEN_Register */ |
| Pawel Zarembski |
0:01f31e923fe2 | 568 | |
| Pawel Zarembski |
0:01f31e923fe2 | 569 | |
| Pawel Zarembski |
0:01f31e923fe2 | 570 | /* |
| Pawel Zarembski |
0:01f31e923fe2 | 571 | Field values and shifted values for module GPIO. |
| Pawel Zarembski |
0:01f31e923fe2 | 572 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 573 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 574 | * @defgroup GPIO_RST_MODE_Values Reset Mode Values |
| Pawel Zarembski |
0:01f31e923fe2 | 575 | * @ingroup GPIO_RST_MODE_Register |
| Pawel Zarembski |
0:01f31e923fe2 | 576 | * @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes |
| Pawel Zarembski |
0:01f31e923fe2 | 577 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 578 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 579 | #define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 580 | #define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */ |
| Pawel Zarembski |
0:01f31e923fe2 | 581 | #define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */ |
| Pawel Zarembski |
0:01f31e923fe2 | 582 | #define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 583 | #define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */ |
| Pawel Zarembski |
0:01f31e923fe2 | 584 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 585 | |
| Pawel Zarembski |
0:01f31e923fe2 | 586 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 587 | * @defgroup GPIO_FREE_Values Reset Mode Values |
| Pawel Zarembski |
0:01f31e923fe2 | 588 | * @ingroup GPIO_FREE_Register |
| Pawel Zarembski |
0:01f31e923fe2 | 589 | * @brief Mode Values for setting the GPIO_FREE to Available or Unavailable |
| Pawel Zarembski |
0:01f31e923fe2 | 590 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 591 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 592 | #define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */ |
| Pawel Zarembski |
0:01f31e923fe2 | 593 | #define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */ |
| Pawel Zarembski |
0:01f31e923fe2 | 594 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 595 | |
| Pawel Zarembski |
0:01f31e923fe2 | 596 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 597 | * @defgroup GPIO_OUT_MODE_Values Output Mode Values |
| Pawel Zarembski |
0:01f31e923fe2 | 598 | * @ingroup GPIO_FREE_Register |
| Pawel Zarembski |
0:01f31e923fe2 | 599 | * @brief GPIO_OUT_MODE values for setting the different port pin output modes |
| Pawel Zarembski |
0:01f31e923fe2 | 600 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 601 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 602 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */ |
| Pawel Zarembski |
0:01f31e923fe2 | 603 | #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */ |
| Pawel Zarembski |
0:01f31e923fe2 | 604 | #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */ |
| Pawel Zarembski |
0:01f31e923fe2 | 605 | #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */ |
| Pawel Zarembski |
0:01f31e923fe2 | 606 | #define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */ |
| Pawel Zarembski |
0:01f31e923fe2 | 607 | #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */ |
| Pawel Zarembski |
0:01f31e923fe2 | 608 | #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 609 | #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */ |
| Pawel Zarembski |
0:01f31e923fe2 | 610 | #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 611 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */ |
| Pawel Zarembski |
0:01f31e923fe2 | 612 | #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */ |
| Pawel Zarembski |
0:01f31e923fe2 | 613 | #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */ |
| Pawel Zarembski |
0:01f31e923fe2 | 614 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */ |
| Pawel Zarembski |
0:01f31e923fe2 | 615 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 616 | |
| Pawel Zarembski |
0:01f31e923fe2 | 617 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 618 | * @defgroup GPIO_FUNC_SEL_Values Function type selection values |
| Pawel Zarembski |
0:01f31e923fe2 | 619 | * @ingroup GPIO_FUNC_SEL_Register |
| Pawel Zarembski |
0:01f31e923fe2 | 620 | * @brief Function selection values for the GPIO_FUNC_SEL Register. |
| Pawel Zarembski |
0:01f31e923fe2 | 621 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 622 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 623 | #define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 624 | #define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 625 | #define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 626 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 627 | |
| Pawel Zarembski |
0:01f31e923fe2 | 628 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 629 | * @defgroup GPIO_IN_MODE_Values Input mode selection values |
| Pawel Zarembski |
0:01f31e923fe2 | 630 | * @ingroup GPIO_IN_MODE_Register |
| Pawel Zarembski |
0:01f31e923fe2 | 631 | * @brief Input mode values for selecting the GPIO input mode. |
| Pawel Zarembski |
0:01f31e923fe2 | 632 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 633 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 634 | #define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 635 | #define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */ |
| Pawel Zarembski |
0:01f31e923fe2 | 636 | #define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 637 | #define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */ |
| Pawel Zarembski |
0:01f31e923fe2 | 638 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 639 | |
| Pawel Zarembski |
0:01f31e923fe2 | 640 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 641 | * @defgroup GPIO_INT_MODE_Values Interrupt mode selection values |
| Pawel Zarembski |
0:01f31e923fe2 | 642 | * @ingroup GPIO_INT_MODE_Register |
| Pawel Zarembski |
0:01f31e923fe2 | 643 | * @brief Values for setting the interrupt mode of a GPIO input pin. |
| Pawel Zarembski |
0:01f31e923fe2 | 644 | * @{ |
| Pawel Zarembski |
0:01f31e923fe2 | 645 | */ |
| Pawel Zarembski |
0:01f31e923fe2 | 646 | #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */ |
| Pawel Zarembski |
0:01f31e923fe2 | 647 | #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 648 | #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 649 | #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */ |
| Pawel Zarembski |
0:01f31e923fe2 | 650 | #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */ |
| Pawel Zarembski |
0:01f31e923fe2 | 651 | #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */ |
| Pawel Zarembski |
0:01f31e923fe2 | 652 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 653 | |
| Pawel Zarembski |
0:01f31e923fe2 | 654 | /**@}*/ |
| Pawel Zarembski |
0:01f31e923fe2 | 655 | #ifdef __cplusplus |
| Pawel Zarembski |
0:01f31e923fe2 | 656 | } |
| Pawel Zarembski |
0:01f31e923fe2 | 657 | #endif |
| Pawel Zarembski |
0:01f31e923fe2 | 658 | |
| Pawel Zarembski |
0:01f31e923fe2 | 659 | #endif /* _MXC_GPIO_REGS_H_ */ |