Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32625/gpio.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* CMSIS-DAP Interface Firmware
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2009-2013 ARM Limited
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Licensed under the Apache License, Version 2.0 (the "License");
Pawel Zarembski 0:01f31e923fe2 5 * you may not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 6 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 11 * distributed under the License is distributed on an "AS IS" BASIS,
Pawel Zarembski 0:01f31e923fe2 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 13 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 14 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 15 */
Pawel Zarembski 0:01f31e923fe2 16
Pawel Zarembski 0:01f31e923fe2 17 #include "max32625.h"
Pawel Zarembski 0:01f31e923fe2 18 #include "clkman_regs.h"
Pawel Zarembski 0:01f31e923fe2 19 #include "gpio_regs.h"
Pawel Zarembski 0:01f31e923fe2 20 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 21 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 22 #include "adc_regs.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "pwrman_regs.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "ioman_regs.h"
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 // For channels 4 and 5; the target VIO inputs
Pawel Zarembski 0:01f31e923fe2 27 // 1.6V is the lowest VIO can operate at,
Pawel Zarembski 0:01f31e923fe2 28 // so set this as minimum acceptable voltage.
Pawel Zarembski 0:01f31e923fe2 29 // round(AIN/(5 * 1.2)*(2^10-1))
Pawel Zarembski 0:01f31e923fe2 30 #define VIO_ADC_MIN 273
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32 // Bitband pointers
Pawel Zarembski 0:01f31e923fe2 33 volatile uint32_t *tck_in;
Pawel Zarembski 0:01f31e923fe2 34 volatile uint32_t *tck_out;
Pawel Zarembski 0:01f31e923fe2 35 volatile uint32_t *tms_in;
Pawel Zarembski 0:01f31e923fe2 36 volatile uint32_t *tms_out;
Pawel Zarembski 0:01f31e923fe2 37 volatile uint32_t *rst_in;
Pawel Zarembski 0:01f31e923fe2 38 volatile uint32_t *rst_out;
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40 uint32_t swdio_port;
Pawel Zarembski 0:01f31e923fe2 41 uint32_t swdio_pin;
Pawel Zarembski 0:01f31e923fe2 42 uint32_t swclk_port;
Pawel Zarembski 0:01f31e923fe2 43 uint32_t swclk_pin;
Pawel Zarembski 0:01f31e923fe2 44 uint32_t nreset_port;
Pawel Zarembski 0:01f31e923fe2 45 uint32_t nreset_pin;
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 int32_t uart_set_instance(uint32_t inst);
Pawel Zarembski 0:01f31e923fe2 48
Pawel Zarembski 0:01f31e923fe2 49 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 50 static inline void use_vddioh(int port, int pin)
Pawel Zarembski 0:01f31e923fe2 51 {
Pawel Zarembski 0:01f31e923fe2 52 if (port > 3) {
Pawel Zarembski 0:01f31e923fe2 53 MXC_IOMAN->use_vddioh_1 |= 1U << (((port - 4) * 8) + pin);
Pawel Zarembski 0:01f31e923fe2 54 } else {
Pawel Zarembski 0:01f31e923fe2 55 MXC_IOMAN->use_vddioh_0 |= 1U << ((port * 8) + pin);
Pawel Zarembski 0:01f31e923fe2 56 }
Pawel Zarembski 0:01f31e923fe2 57 }
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 60 static uint16_t readADC(uint8_t ch)
Pawel Zarembski 0:01f31e923fe2 61 {
Pawel Zarembski 0:01f31e923fe2 62 uint32_t ctrl_tmp;
Pawel Zarembski 0:01f31e923fe2 63
Pawel Zarembski 0:01f31e923fe2 64 // Select channel
Pawel Zarembski 0:01f31e923fe2 65 ctrl_tmp = MXC_ADC->ctrl;
Pawel Zarembski 0:01f31e923fe2 66 ctrl_tmp &= ~MXC_F_ADC_CTRL_ADC_CHSEL;
Pawel Zarembski 0:01f31e923fe2 67 ctrl_tmp |= ((ch << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL);
Pawel Zarembski 0:01f31e923fe2 68
Pawel Zarembski 0:01f31e923fe2 69 // Clear channel configuration
Pawel Zarembski 0:01f31e923fe2 70 ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_REFSCL | MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_BUF_BYPASS);
Pawel Zarembski 0:01f31e923fe2 71
Pawel Zarembski 0:01f31e923fe2 72 // ADC reference scaling
Pawel Zarembski 0:01f31e923fe2 73 ctrl_tmp |= MXC_F_ADC_CTRL_ADC_REFSCL;
Pawel Zarembski 0:01f31e923fe2 74
Pawel Zarembski 0:01f31e923fe2 75 if ((ch == SWD_VIO_CH) || (ch == HDR_VIO_CH)) {
Pawel Zarembski 0:01f31e923fe2 76 ctrl_tmp |= MXC_F_ADC_CTRL_ADC_SCALE;
Pawel Zarembski 0:01f31e923fe2 77 }
Pawel Zarembski 0:01f31e923fe2 78
Pawel Zarembski 0:01f31e923fe2 79 // Do not bypass buffer, except when measuring near ground.
Pawel Zarembski 0:01f31e923fe2 80 // This may be the case for measuring 1-Wire ground detect on channels 2 and 3.
Pawel Zarembski 0:01f31e923fe2 81 if ((ch == SWD_GNDDET_CH) || (ch == HDR_GNDDET_CH)) {
Pawel Zarembski 0:01f31e923fe2 82 ctrl_tmp |= MXC_F_ADC_CTRL_BUF_BYPASS;
Pawel Zarembski 0:01f31e923fe2 83 }
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 // Write this configuration
Pawel Zarembski 0:01f31e923fe2 86 MXC_ADC->ctrl = ctrl_tmp;
Pawel Zarembski 0:01f31e923fe2 87
Pawel Zarembski 0:01f31e923fe2 88 // Clear conversion done interrupt flag
Pawel Zarembski 0:01f31e923fe2 89 MXC_ADC->intr = MXC_F_ADC_INTR_ADC_DONE_IF;
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91 // Start conversion
Pawel Zarembski 0:01f31e923fe2 92 MXC_ADC->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START;
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 while (!(MXC_ADC->intr & MXC_F_ADC_INTR_ADC_DONE_IF));
Pawel Zarembski 0:01f31e923fe2 95
Pawel Zarembski 0:01f31e923fe2 96 return (uint16_t)(MXC_ADC->data);
Pawel Zarembski 0:01f31e923fe2 97 }
Pawel Zarembski 0:01f31e923fe2 98
Pawel Zarembski 0:01f31e923fe2 99 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 100 void target_set_interface(TARGET_INTERFACE mode)
Pawel Zarembski 0:01f31e923fe2 101 {
Pawel Zarembski 0:01f31e923fe2 102 switch (mode) {
Pawel Zarembski 0:01f31e923fe2 103 case IO_SWD_EXT:
Pawel Zarembski 0:01f31e923fe2 104 swdio_port = PIN_SWDIO_PORT;
Pawel Zarembski 0:01f31e923fe2 105 swdio_pin = PIN_SWDIO_PIN;
Pawel Zarembski 0:01f31e923fe2 106 swclk_port = PIN_SWCLK_PORT;
Pawel Zarembski 0:01f31e923fe2 107 swclk_pin = PIN_SWCLK_PIN;
Pawel Zarembski 0:01f31e923fe2 108 nreset_port = PIN_nRESET_PORT;
Pawel Zarembski 0:01f31e923fe2 109 nreset_pin = PIN_nRESET_PIN;
Pawel Zarembski 0:01f31e923fe2 110
Pawel Zarembski 0:01f31e923fe2 111 MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); // Low to disable SWOUT
Pawel Zarembski 0:01f31e923fe2 112 MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); // High to power MAX14689
Pawel Zarembski 0:01f31e923fe2 113 MXC_SETBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn
Pawel Zarembski 0:01f31e923fe2 114 uart_set_instance(CDC_ACM_UART_SWD);
Pawel Zarembski 0:01f31e923fe2 115 break;
Pawel Zarembski 0:01f31e923fe2 116 case IO_DIP_EXT:
Pawel Zarembski 0:01f31e923fe2 117 swdio_port = PIN_DIP_SWDIO_PORT;
Pawel Zarembski 0:01f31e923fe2 118 swdio_pin = PIN_DIP_SWDIO_PIN;
Pawel Zarembski 0:01f31e923fe2 119 swclk_port = PIN_DIP_SWCLK_PORT;
Pawel Zarembski 0:01f31e923fe2 120 swclk_pin = PIN_DIP_SWCLK_PIN;
Pawel Zarembski 0:01f31e923fe2 121 nreset_port = PIN_DIP_nRESET_PORT;
Pawel Zarembski 0:01f31e923fe2 122 nreset_pin = PIN_DIP_nRESET_PIN;
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); // Low to disable SWOUT
Pawel Zarembski 0:01f31e923fe2 125 MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); // High to power MAX14689
Pawel Zarembski 0:01f31e923fe2 126 MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // Low to connect Bn <-> An
Pawel Zarembski 0:01f31e923fe2 127 uart_set_instance(CDC_ACM_UART_DIP);
Pawel Zarembski 0:01f31e923fe2 128 break;
Pawel Zarembski 0:01f31e923fe2 129 }
Pawel Zarembski 0:01f31e923fe2 130 }
Pawel Zarembski 0:01f31e923fe2 131
Pawel Zarembski 0:01f31e923fe2 132 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 133 void gpio_init(void)
Pawel Zarembski 0:01f31e923fe2 134 {
Pawel Zarembski 0:01f31e923fe2 135 int i;
Pawel Zarembski 0:01f31e923fe2 136 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 137
Pawel Zarembski 0:01f31e923fe2 138 // Ensure that the GPIO clock is enabled
Pawel Zarembski 0:01f31e923fe2 139 if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_S_CLKMAN_CLK_SCALE_DISABLED) {
Pawel Zarembski 0:01f31e923fe2 140 MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
Pawel Zarembski 0:01f31e923fe2 141 }
Pawel Zarembski 0:01f31e923fe2 142
Pawel Zarembski 0:01f31e923fe2 143 // Make all GPIO pins readable
Pawel Zarembski 0:01f31e923fe2 144 for (i = 0; i < MXC_GPIO_NUM_PORTS; i++) {
Pawel Zarembski 0:01f31e923fe2 145 MXC_GPIO->in_mode[i] = 0x00000000;
Pawel Zarembski 0:01f31e923fe2 146 }
Pawel Zarembski 0:01f31e923fe2 147
Pawel Zarembski 0:01f31e923fe2 148 // Set to enable the board to power VDDIOH and in turn the target micro
Pawel Zarembski 0:01f31e923fe2 149 // Clear to disable the board from powering VDDIOH
Pawel Zarembski 0:01f31e923fe2 150 MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN);
Pawel Zarembski 0:01f31e923fe2 151 out_mode = MXC_GPIO->out_mode[EN_VDDIOH_PORT];
Pawel Zarembski 0:01f31e923fe2 152 out_mode &= ~(0xFU << (4 * EN_VDDIOH_PIN));
Pawel Zarembski 0:01f31e923fe2 153 out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * EN_VDDIOH_PIN));
Pawel Zarembski 0:01f31e923fe2 154 MXC_GPIO->out_mode[EN_VDDIOH_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 // LED initial state off
Pawel Zarembski 0:01f31e923fe2 157 MXC_GPIO->out_val[PIN_DAP_LED_PORT] |= (1 << PIN_DAP_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 158 MXC_GPIO->out_val[PIN_MSD_LED_PORT] |= (1 << PIN_MSD_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 159 MXC_GPIO->out_val[PIN_CDC_LED_PORT] |= (1 << PIN_CDC_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 160
Pawel Zarembski 0:01f31e923fe2 161 // LED outputs
Pawel Zarembski 0:01f31e923fe2 162 out_mode = MXC_GPIO->out_mode[PIN_DAP_LED_PORT];
Pawel Zarembski 0:01f31e923fe2 163 out_mode &= ~(0xFU << (4 * PIN_DAP_LED_PIN));
Pawel Zarembski 0:01f31e923fe2 164 out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_DAP_LED_PIN));
Pawel Zarembski 0:01f31e923fe2 165 MXC_GPIO->out_mode[PIN_DAP_LED_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 166
Pawel Zarembski 0:01f31e923fe2 167 out_mode = MXC_GPIO->out_mode[PIN_MSD_LED_PORT];
Pawel Zarembski 0:01f31e923fe2 168 out_mode &= ~(0xFU << (4 * PIN_MSD_LED_PIN));
Pawel Zarembski 0:01f31e923fe2 169 out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_MSD_LED_PIN));
Pawel Zarembski 0:01f31e923fe2 170 MXC_GPIO->out_mode[PIN_MSD_LED_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 out_mode = MXC_GPIO->out_mode[PIN_CDC_LED_PORT];
Pawel Zarembski 0:01f31e923fe2 173 out_mode &= ~(0xFU << (4 * PIN_CDC_LED_PIN));
Pawel Zarembski 0:01f31e923fe2 174 out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_CDC_LED_PIN));
Pawel Zarembski 0:01f31e923fe2 175 MXC_GPIO->out_mode[PIN_CDC_LED_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 176
Pawel Zarembski 0:01f31e923fe2 177 // Button Input
Pawel Zarembski 0:01f31e923fe2 178 out_mode = MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT];
Pawel Zarembski 0:01f31e923fe2 179 out_mode &= ~(0xFU << (4 * PIN_RESET_IN_NO_FWRD_PIN));
Pawel Zarembski 0:01f31e923fe2 180 out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * PIN_RESET_IN_NO_FWRD_PIN));
Pawel Zarembski 0:01f31e923fe2 181 MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 182 MXC_GPIO->out_val[PIN_RESET_IN_NO_FWRD_PORT] |= (0x1U << PIN_RESET_IN_NO_FWRD_PIN);
Pawel Zarembski 0:01f31e923fe2 183
Pawel Zarembski 0:01f31e923fe2 184 // IOH_1W_EN (must be configured for strong drive)
Pawel Zarembski 0:01f31e923fe2 185 MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN);
Pawel Zarembski 0:01f31e923fe2 186 out_mode = MXC_GPIO->out_mode[IOH_OW_EN_PORT];
Pawel Zarembski 0:01f31e923fe2 187 out_mode &= ~(0xFU << (4 * IOH_OW_EN_PIN));
Pawel Zarembski 0:01f31e923fe2 188 out_mode |= (MXC_V_GPIO_OUT_MODE_FAST_DRIVE << (4 * IOH_OW_EN_PIN));
Pawel Zarembski 0:01f31e923fe2 189 MXC_GPIO->out_mode[IOH_OW_EN_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 190
Pawel Zarembski 0:01f31e923fe2 191 // SWD_DIP_SEL (must be configured for strong drive)
Pawel Zarembski 0:01f31e923fe2 192 MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN);
Pawel Zarembski 0:01f31e923fe2 193 out_mode = MXC_GPIO->out_mode[SWD_DIP_SEL_PORT];
Pawel Zarembski 0:01f31e923fe2 194 out_mode &= ~(0xFU << (4 * SWD_DIP_SEL_PIN));
Pawel Zarembski 0:01f31e923fe2 195 out_mode |= (MXC_V_GPIO_OUT_MODE_FAST_DRIVE << (4 * SWD_DIP_SEL_PIN));
Pawel Zarembski 0:01f31e923fe2 196 MXC_GPIO->out_mode[SWD_DIP_SEL_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 197
Pawel Zarembski 0:01f31e923fe2 198 // Strong pull-up disable
Pawel Zarembski 0:01f31e923fe2 199 MXC_SETBIT(&MXC_GPIO->out_val[OWM_SUP_PORT], OWM_SUP_PIN);
Pawel Zarembski 0:01f31e923fe2 200 out_mode = MXC_GPIO->out_mode[OWM_SUP_PORT];
Pawel Zarembski 0:01f31e923fe2 201 out_mode &= ~(0xFU << (4 * OWM_SUP_PIN));
Pawel Zarembski 0:01f31e923fe2 202 out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * OWM_SUP_PIN));
Pawel Zarembski 0:01f31e923fe2 203 MXC_GPIO->out_mode[OWM_SUP_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 204
Pawel Zarembski 0:01f31e923fe2 205 // VDDIOH driver isn't strong enough with the strong pull-up
Pawel Zarembski 0:01f31e923fe2 206 MXC_IOMAN->use_vddioh_1 &= ~(1U << (((OWM_PORT - 4) * 8) + OWM_PIN));
Pawel Zarembski 0:01f31e923fe2 207 // 1V8 VDDIO is not high enough to turn off the FET if VDDIOH is 3V3
Pawel Zarembski 0:01f31e923fe2 208 MXC_IOMAN->use_vddioh_1 |= (1U << (((OWM_PORT - 4) * 8) + OWM_SUP_PIN));
Pawel Zarembski 0:01f31e923fe2 209
Pawel Zarembski 0:01f31e923fe2 210 use_vddioh(PIN_nRESET_PORT, PIN_nRESET_PIN);
Pawel Zarembski 0:01f31e923fe2 211 use_vddioh(PIN_DIP_nRESET_PORT, PIN_DIP_nRESET_PIN);
Pawel Zarembski 0:01f31e923fe2 212 use_vddioh(PIN_SWCLK_PORT, PIN_SWCLK_PIN);
Pawel Zarembski 0:01f31e923fe2 213 use_vddioh(PIN_DIP_SWCLK_PORT, PIN_DIP_SWCLK_PIN);
Pawel Zarembski 0:01f31e923fe2 214 use_vddioh(PIN_SWDIO_PORT, PIN_SWDIO_PIN);
Pawel Zarembski 0:01f31e923fe2 215 use_vddioh(PIN_DIP_SWDIO_PORT, PIN_DIP_SWDIO_PIN);
Pawel Zarembski 0:01f31e923fe2 216 use_vddioh(PIN_TX_PORT, PIN_TX_PIN);
Pawel Zarembski 0:01f31e923fe2 217 use_vddioh(PIN_RX_PORT, PIN_RX_PIN);
Pawel Zarembski 0:01f31e923fe2 218 use_vddioh(PIN_DIP_TX_PORT, PIN_DIP_TX_PIN);
Pawel Zarembski 0:01f31e923fe2 219 use_vddioh(PIN_DIP_RX_PORT, PIN_DIP_RX_PIN);
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 // Setup the ADC; read the ADC to set IO interface
Pawel Zarembski 0:01f31e923fe2 222 MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
Pawel Zarembski 0:01f31e923fe2 223 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE;
Pawel Zarembski 0:01f31e923fe2 224
Pawel Zarembski 0:01f31e923fe2 225 MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU |
Pawel Zarembski 0:01f31e923fe2 226 MXC_F_ADC_CTRL_ADC_CLK_EN |
Pawel Zarembski 0:01f31e923fe2 227 MXC_F_ADC_CTRL_BUF_PU |
Pawel Zarembski 0:01f31e923fe2 228 MXC_F_ADC_CTRL_ADC_REFBUF_PU |
Pawel Zarembski 0:01f31e923fe2 229 MXC_F_ADC_CTRL_ADC_CHGPUMP_PU);
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 // Set IO interface
Pawel Zarembski 0:01f31e923fe2 232 if (readADC(SWD_VIO_CH) > VIO_ADC_MIN) {
Pawel Zarembski 0:01f31e923fe2 233 target_set_interface(IO_SWD_EXT);
Pawel Zarembski 0:01f31e923fe2 234 } else if (readADC(HDR_VIO_CH) > VIO_ADC_MIN) {
Pawel Zarembski 0:01f31e923fe2 235 target_set_interface(IO_DIP_EXT);
Pawel Zarembski 0:01f31e923fe2 236 } else {
Pawel Zarembski 0:01f31e923fe2 237 // Default to SWD interface
Pawel Zarembski 0:01f31e923fe2 238 target_set_interface(IO_SWD_EXT);
Pawel Zarembski 0:01f31e923fe2 239 }
Pawel Zarembski 0:01f31e923fe2 240
Pawel Zarembski 0:01f31e923fe2 241 }
Pawel Zarembski 0:01f31e923fe2 242
Pawel Zarembski 0:01f31e923fe2 243 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 244 void gpio_set_hid_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 245 {
Pawel Zarembski 0:01f31e923fe2 246 if (state == GPIO_LED_ON) {
Pawel Zarembski 0:01f31e923fe2 247 MXC_CLRBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 248 } else {
Pawel Zarembski 0:01f31e923fe2 249 MXC_SETBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 250 }
Pawel Zarembski 0:01f31e923fe2 251 }
Pawel Zarembski 0:01f31e923fe2 252
Pawel Zarembski 0:01f31e923fe2 253 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 254 void gpio_set_msc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 255 {
Pawel Zarembski 0:01f31e923fe2 256 if (state == GPIO_LED_ON) {
Pawel Zarembski 0:01f31e923fe2 257 MXC_CLRBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 258 } else {
Pawel Zarembski 0:01f31e923fe2 259 MXC_SETBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 260 }
Pawel Zarembski 0:01f31e923fe2 261 }
Pawel Zarembski 0:01f31e923fe2 262
Pawel Zarembski 0:01f31e923fe2 263 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 264 void gpio_set_cdc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 265 {
Pawel Zarembski 0:01f31e923fe2 266 if (state == GPIO_LED_ON) {
Pawel Zarembski 0:01f31e923fe2 267 MXC_CLRBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 268 } else {
Pawel Zarembski 0:01f31e923fe2 269 MXC_SETBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN);
Pawel Zarembski 0:01f31e923fe2 270 }
Pawel Zarembski 0:01f31e923fe2 271 }
Pawel Zarembski 0:01f31e923fe2 272
Pawel Zarembski 0:01f31e923fe2 273 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 274 uint8_t gpio_get_reset_btn_no_fwrd(void)
Pawel Zarembski 0:01f31e923fe2 275 {
Pawel Zarembski 0:01f31e923fe2 276 return !MXC_GETBIT(&MXC_GPIO->in_val[PIN_RESET_IN_NO_FWRD_PORT], PIN_RESET_IN_NO_FWRD_PIN);
Pawel Zarembski 0:01f31e923fe2 277 }
Pawel Zarembski 0:01f31e923fe2 278
Pawel Zarembski 0:01f31e923fe2 279 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 280 uint8_t gpio_get_reset_btn_fwrd(void)
Pawel Zarembski 0:01f31e923fe2 281 {
Pawel Zarembski 0:01f31e923fe2 282 return 0;
Pawel Zarembski 0:01f31e923fe2 283 }
Pawel Zarembski 0:01f31e923fe2 284
Pawel Zarembski 0:01f31e923fe2 285 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 286 void gpio_set_board_power(bool powerEnabled)
Pawel Zarembski 0:01f31e923fe2 287 {
Pawel Zarembski 0:01f31e923fe2 288 }