Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32625/adc_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /* **************************************************************************** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Pawel Zarembski |
0:01f31e923fe2 | 3 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
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0:01f31e923fe2 | 32 | *************************************************************************** */ |
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0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | /* Define to prevent redundant inclusion */ |
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0:01f31e923fe2 | 35 | #ifndef _MXC_ADC_REGS_H_ |
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0:01f31e923fe2 | 36 | #define _MXC_ADC_REGS_H_ |
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0:01f31e923fe2 | 37 | |
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0:01f31e923fe2 | 38 | /* **** Includes **** */ |
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0:01f31e923fe2 | 39 | #include <stdint.h> |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #ifdef __cplusplus |
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0:01f31e923fe2 | 42 | extern "C" { |
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0:01f31e923fe2 | 43 | #endif |
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0:01f31e923fe2 | 44 | |
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0:01f31e923fe2 | 45 | /// @cond |
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0:01f31e923fe2 | 46 | /* |
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0:01f31e923fe2 | 47 | If types are not defined elsewhere (CMSIS) define them here |
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0:01f31e923fe2 | 48 | */ |
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0:01f31e923fe2 | 49 | #ifndef __IO |
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0:01f31e923fe2 | 50 | #define __IO volatile |
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0:01f31e923fe2 | 51 | #endif |
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0:01f31e923fe2 | 52 | #ifndef __I |
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0:01f31e923fe2 | 53 | #define __I volatile const |
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0:01f31e923fe2 | 54 | #endif |
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0:01f31e923fe2 | 55 | #ifndef __O |
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0:01f31e923fe2 | 56 | #define __O volatile |
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0:01f31e923fe2 | 57 | #endif |
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0:01f31e923fe2 | 58 | #ifndef __R |
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0:01f31e923fe2 | 59 | #define __R volatile const |
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0:01f31e923fe2 | 60 | #endif |
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0:01f31e923fe2 | 61 | /// @endcond |
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0:01f31e923fe2 | 62 | |
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0:01f31e923fe2 | 63 | /* **** Definitions **** */ |
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0:01f31e923fe2 | 64 | |
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0:01f31e923fe2 | 65 | /** |
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0:01f31e923fe2 | 66 | * @defgroup adc_registers Registers |
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0:01f31e923fe2 | 67 | * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. |
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0:01f31e923fe2 | 68 | * @ingroup adc |
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0:01f31e923fe2 | 69 | * @{ |
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0:01f31e923fe2 | 70 | */ |
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0:01f31e923fe2 | 71 | |
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0:01f31e923fe2 | 72 | /** |
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0:01f31e923fe2 | 73 | * Structure type to access the ADC Registers. |
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0:01f31e923fe2 | 74 | */ |
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0:01f31e923fe2 | 75 | typedef struct { |
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0:01f31e923fe2 | 76 | __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> ADC CTRL Register */ |
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0:01f31e923fe2 | 77 | __IO uint32_t status; /**< <tt>\b 0x004:</tt> ADC STATUS Register */ |
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0:01f31e923fe2 | 78 | __IO uint32_t data; /**< <tt>\b 0x008:</tt> ADC DATA Register */ |
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0:01f31e923fe2 | 79 | __IO uint32_t intr; /**< <tt>\b 0x00C:</tt> ADC INTR Register */ |
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0:01f31e923fe2 | 80 | __IO uint32_t limit[4]; /**< <tt>\b 0x010:</tt> ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */ |
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0:01f31e923fe2 | 81 | __IO uint32_t afe_ctrl; /**< <tt>\b 0x020:</tt> ADC AFE_CTRL Register */ |
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0:01f31e923fe2 | 82 | __IO uint32_t ro_cal0; /**< <tt>\b 0x024:</tt> ADC RO_CAL0 Register */ |
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0:01f31e923fe2 | 83 | __IO uint32_t ro_cal1; /**< <tt>\b 0x028:</tt> ADC RO_CAL1 Register */ |
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0:01f31e923fe2 | 84 | __IO uint32_t ro_cal2; /**< <tt>\b 0x02C:</tt> ADC RO_CAL2 Register */ |
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0:01f31e923fe2 | 85 | } mxc_adc_regs_t; |
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0:01f31e923fe2 | 86 | /**@} end of group adc_registers */ |
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0:01f31e923fe2 | 87 | |
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0:01f31e923fe2 | 88 | |
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0:01f31e923fe2 | 89 | /* Register offsets for module ADC. */ |
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0:01f31e923fe2 | 90 | /** |
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0:01f31e923fe2 | 91 | * @defgroup ADC_Register_Offsets Register Offsets |
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0:01f31e923fe2 | 92 | * @ingroup adc_registers |
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0:01f31e923fe2 | 93 | * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. |
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0:01f31e923fe2 | 94 | * @{ |
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0:01f31e923fe2 | 95 | */ |
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0:01f31e923fe2 | 96 | #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt>\b 0x000</tt> */ |
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0:01f31e923fe2 | 97 | #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt>\b 0x004</tt> */ |
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0:01f31e923fe2 | 98 | #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt>\b 0x008</tt> */ |
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0:01f31e923fe2 | 99 | #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt>\b 0x00C</tt> */ |
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0:01f31e923fe2 | 100 | #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt>\b 0x010</tt> */ |
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0:01f31e923fe2 | 101 | #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt>\b 0x014</tt> */ |
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0:01f31e923fe2 | 102 | #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt>\b 0x018</tt> */ |
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0:01f31e923fe2 | 103 | #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt>\b 0x01C</tt> */ |
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0:01f31e923fe2 | 104 | #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt>\b 0x020</tt> */ |
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0:01f31e923fe2 | 105 | #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt>\b 0x024</tt> */ |
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0:01f31e923fe2 | 106 | #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt>\b 0x028</tt> */ |
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0:01f31e923fe2 | 107 | #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt>\b 0x02C</tt> */ |
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0:01f31e923fe2 | 108 | /**@} end of group adc_registers */ |
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0:01f31e923fe2 | 109 | |
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0:01f31e923fe2 | 110 | /** |
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0:01f31e923fe2 | 111 | * @defgroup ADC_CTRL_Register ADC_CTRL |
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0:01f31e923fe2 | 112 | * @brief Field Positions and Bit Masks for the ADC_CTRL register |
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0:01f31e923fe2 | 113 | * @ingroup adc_registers |
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0:01f31e923fe2 | 114 | * @{ |
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0:01f31e923fe2 | 115 | */ |
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0:01f31e923fe2 | 116 | #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */ |
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0:01f31e923fe2 | 117 | #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */ |
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0:01f31e923fe2 | 118 | #define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */ |
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0:01f31e923fe2 | 119 | #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */ |
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0:01f31e923fe2 | 120 | #define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */ |
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0:01f31e923fe2 | 121 | #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */ |
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0:01f31e923fe2 | 122 | #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */ |
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0:01f31e923fe2 | 123 | #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */ |
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0:01f31e923fe2 | 124 | #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */ |
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0:01f31e923fe2 | 125 | #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */ |
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0:01f31e923fe2 | 126 | #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */ |
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0:01f31e923fe2 | 127 | #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */ |
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0:01f31e923fe2 | 128 | #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */ |
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0:01f31e923fe2 | 129 | #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */ |
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0:01f31e923fe2 | 130 | #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */ |
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0:01f31e923fe2 | 131 | #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */ |
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0:01f31e923fe2 | 132 | #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */ |
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0:01f31e923fe2 | 133 | #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */ |
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0:01f31e923fe2 | 134 | #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */ |
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0:01f31e923fe2 | 135 | #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */ |
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0:01f31e923fe2 | 136 | #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */ |
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0:01f31e923fe2 | 137 | #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */ |
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0:01f31e923fe2 | 138 | #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */ |
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0:01f31e923fe2 | 139 | #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */ |
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0:01f31e923fe2 | 140 | #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */ |
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0:01f31e923fe2 | 141 | #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */ |
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0:01f31e923fe2 | 142 | #define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */ |
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0:01f31e923fe2 | 143 | #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */ |
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0:01f31e923fe2 | 144 | #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */ |
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0:01f31e923fe2 | 145 | #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */ |
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0:01f31e923fe2 | 146 | #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */ |
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0:01f31e923fe2 | 147 | #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */ |
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0:01f31e923fe2 | 148 | |
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0:01f31e923fe2 | 149 | /**@} end of group adc_ctrl_register */ |
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0:01f31e923fe2 | 150 | |
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0:01f31e923fe2 | 151 | /** |
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0:01f31e923fe2 | 152 | * @defgroup ADC_STATUS_Register ADC_STATUS |
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0:01f31e923fe2 | 153 | * @brief Field Positions and Bit Masks for the ADC_STATUS register |
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0:01f31e923fe2 | 154 | * @ingroup adc_registers |
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0:01f31e923fe2 | 155 | * @{ |
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0:01f31e923fe2 | 156 | */ |
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0:01f31e923fe2 | 157 | #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */ |
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0:01f31e923fe2 | 158 | #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */ |
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0:01f31e923fe2 | 159 | #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */ |
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0:01f31e923fe2 | 160 | #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */ |
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0:01f31e923fe2 | 161 | #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */ |
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0:01f31e923fe2 | 162 | #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */ |
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0:01f31e923fe2 | 163 | #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */ |
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0:01f31e923fe2 | 164 | #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */ |
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0:01f31e923fe2 | 165 | /**@} end of group ADC_STATUS_register */ |
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0:01f31e923fe2 | 166 | |
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0:01f31e923fe2 | 167 | /** |
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0:01f31e923fe2 | 168 | * @defgroup ADC_DATA_Register ADC_DATA |
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0:01f31e923fe2 | 169 | * @ingroup adc_registers |
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0:01f31e923fe2 | 170 | * @brief Field Positions and Bit Masks for the ADC_DATA register |
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0:01f31e923fe2 | 171 | * @{ |
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0:01f31e923fe2 | 172 | */ |
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0:01f31e923fe2 | 173 | #define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */ |
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0:01f31e923fe2 | 174 | #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */ |
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0:01f31e923fe2 | 175 | /**@} end of group ADC_DATA_register */ |
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0:01f31e923fe2 | 176 | |
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0:01f31e923fe2 | 177 | /** |
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0:01f31e923fe2 | 178 | * @defgroup ADC_INTR_Register ADC_INTR Register |
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0:01f31e923fe2 | 179 | * @ingroup adc_registers |
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0:01f31e923fe2 | 180 | * @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks |
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0:01f31e923fe2 | 181 | * @{ |
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0:01f31e923fe2 | 182 | */ |
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0:01f31e923fe2 | 183 | /** |
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0:01f31e923fe2 | 184 | * @defgroup ADC_INTR_IE_Register Interrupt Enable Bits |
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0:01f31e923fe2 | 185 | * @ingroup ADC_INTR_Register |
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0:01f31e923fe2 | 186 | * @brief Interrupt Enable Bit Positions and Masks |
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0:01f31e923fe2 | 187 | * @{ |
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0:01f31e923fe2 | 188 | */ |
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0:01f31e923fe2 | 189 | #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */ |
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0:01f31e923fe2 | 190 | #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */ |
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0:01f31e923fe2 | 191 | #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */ |
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0:01f31e923fe2 | 192 | #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */ |
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0:01f31e923fe2 | 193 | #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */ |
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0:01f31e923fe2 | 194 | #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */ |
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0:01f31e923fe2 | 195 | #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */ |
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0:01f31e923fe2 | 196 | #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */ |
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0:01f31e923fe2 | 197 | #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */ |
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0:01f31e923fe2 | 198 | #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */ |
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0:01f31e923fe2 | 199 | #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */ |
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0:01f31e923fe2 | 200 | #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */ |
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0:01f31e923fe2 | 201 | /**@} end of group ADC_INTR_IE_Register */ |
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0:01f31e923fe2 | 202 | |
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0:01f31e923fe2 | 203 | |
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0:01f31e923fe2 | 204 | /** |
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0:01f31e923fe2 | 205 | * @defgroup ADC_INTR_IF_Register Interrupt Flag Bits |
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0:01f31e923fe2 | 206 | * @ingroup ADC_INTR_Register |
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0:01f31e923fe2 | 207 | * @brief Interrupt Flag Bit Positions and Masks |
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0:01f31e923fe2 | 208 | * @{ |
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0:01f31e923fe2 | 209 | */ |
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0:01f31e923fe2 | 210 | #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */ |
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0:01f31e923fe2 | 211 | #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */ |
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0:01f31e923fe2 | 212 | #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */ |
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0:01f31e923fe2 | 213 | #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */ |
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0:01f31e923fe2 | 214 | #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */ |
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0:01f31e923fe2 | 215 | #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */ |
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0:01f31e923fe2 | 216 | #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */ |
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0:01f31e923fe2 | 217 | #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */ |
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0:01f31e923fe2 | 218 | #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */ |
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0:01f31e923fe2 | 219 | #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */ |
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0:01f31e923fe2 | 220 | #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */ |
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0:01f31e923fe2 | 221 | #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */ |
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0:01f31e923fe2 | 222 | #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */ |
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0:01f31e923fe2 | 223 | #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */ |
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0:01f31e923fe2 | 224 | /**@} end of group ADC_INTR_IF_Register */ |
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0:01f31e923fe2 | 225 | /**@} end of group ADC_INTR_Register */ |
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0:01f31e923fe2 | 226 | |
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0:01f31e923fe2 | 227 | /** |
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0:01f31e923fe2 | 228 | * @defgroup ADC_LIMIT0_Register ADC_LIMIT0 |
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0:01f31e923fe2 | 229 | * @ingroup adc_registers |
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0:01f31e923fe2 | 230 | * @brief Field Positions and Bit Masks for the ADC_LIMIT0 register |
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0:01f31e923fe2 | 231 | * @{ |
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0:01f31e923fe2 | 232 | */ |
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0:01f31e923fe2 | 233 | #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ |
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0:01f31e923fe2 | 234 | #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ |
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0:01f31e923fe2 | 235 | #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ |
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0:01f31e923fe2 | 236 | #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ |
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0:01f31e923fe2 | 237 | #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */ |
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0:01f31e923fe2 | 238 | #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */ |
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0:01f31e923fe2 | 239 | #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ |
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0:01f31e923fe2 | 240 | #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 241 | #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ |
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0:01f31e923fe2 | 242 | #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 243 | /**@} end of group ADC_LIMIT0_register */ |
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0:01f31e923fe2 | 244 | |
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0:01f31e923fe2 | 245 | /** |
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0:01f31e923fe2 | 246 | * @defgroup ADC_LIMIT1_Register ADC_LIMIT1 |
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0:01f31e923fe2 | 247 | * @ingroup adc_registers |
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0:01f31e923fe2 | 248 | * @brief Field Positions and Bit Masks for the ADC_LIMIT1 register |
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0:01f31e923fe2 | 249 | * @{ |
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0:01f31e923fe2 | 250 | */ |
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0:01f31e923fe2 | 251 | #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ |
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0:01f31e923fe2 | 252 | #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ |
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0:01f31e923fe2 | 253 | #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ |
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0:01f31e923fe2 | 254 | #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ |
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0:01f31e923fe2 | 255 | #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */ |
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0:01f31e923fe2 | 256 | #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */ |
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0:01f31e923fe2 | 257 | #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ |
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0:01f31e923fe2 | 258 | #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 259 | #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ |
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0:01f31e923fe2 | 260 | #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 261 | /**@} end of group ADC_LIMIT1_register */ |
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0:01f31e923fe2 | 262 | |
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0:01f31e923fe2 | 263 | /** |
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0:01f31e923fe2 | 264 | * @defgroup ADC_LIMIT2_Register ADC_LIMIT2 |
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0:01f31e923fe2 | 265 | * @ingroup adc_registers |
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0:01f31e923fe2 | 266 | * @brief Field Positions and Bit Masks for the ADC_LIMIT2 register |
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0:01f31e923fe2 | 267 | * @{ |
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0:01f31e923fe2 | 268 | */ |
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0:01f31e923fe2 | 269 | #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ |
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0:01f31e923fe2 | 270 | #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ |
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0:01f31e923fe2 | 271 | #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ |
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0:01f31e923fe2 | 272 | #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ |
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0:01f31e923fe2 | 273 | #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */ |
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0:01f31e923fe2 | 274 | #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */ |
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0:01f31e923fe2 | 275 | #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ |
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0:01f31e923fe2 | 276 | #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 277 | #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ |
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0:01f31e923fe2 | 278 | #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 279 | /**@} end of group ADC_LIMIT2_register */ |
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0:01f31e923fe2 | 280 | |
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0:01f31e923fe2 | 281 | /** |
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0:01f31e923fe2 | 282 | * @defgroup ADC_LIMIT3_Register ADC_LIMIT3 |
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0:01f31e923fe2 | 283 | * @ingroup adc_registers |
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0:01f31e923fe2 | 284 | * @brief Field Positions and Bit Masks for the ADC_LIMIT3 register |
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0:01f31e923fe2 | 285 | * @{ |
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0:01f31e923fe2 | 286 | */ |
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0:01f31e923fe2 | 287 | #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */ |
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0:01f31e923fe2 | 288 | #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */ |
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0:01f31e923fe2 | 289 | #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */ |
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0:01f31e923fe2 | 290 | #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */ |
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0:01f31e923fe2 | 291 | #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */ |
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0:01f31e923fe2 | 292 | #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */ |
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0:01f31e923fe2 | 293 | #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */ |
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0:01f31e923fe2 | 294 | #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 295 | #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */ |
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0:01f31e923fe2 | 296 | #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */ |
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0:01f31e923fe2 | 297 | /**@} end of group ADC_LIMIT3_register */ |
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0:01f31e923fe2 | 298 | |
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0:01f31e923fe2 | 299 | /** |
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0:01f31e923fe2 | 300 | * @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL |
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0:01f31e923fe2 | 301 | * @ingroup adc_registers |
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0:01f31e923fe2 | 302 | * @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register |
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0:01f31e923fe2 | 303 | * @{ |
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0:01f31e923fe2 | 304 | */ |
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0:01f31e923fe2 | 305 | #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */ |
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0:01f31e923fe2 | 306 | #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */ |
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0:01f31e923fe2 | 307 | #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */ |
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0:01f31e923fe2 | 308 | #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */ |
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0:01f31e923fe2 | 309 | /**@} end of group ADC_AFE_CTRL_register */ |
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0:01f31e923fe2 | 310 | |
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0:01f31e923fe2 | 311 | /** |
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0:01f31e923fe2 | 312 | * @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0 |
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0:01f31e923fe2 | 313 | * @ingroup adc_registers |
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0:01f31e923fe2 | 314 | * @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register |
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0:01f31e923fe2 | 315 | * @{ |
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0:01f31e923fe2 | 316 | */ |
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0:01f31e923fe2 | 317 | #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */ |
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0:01f31e923fe2 | 318 | #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */ |
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0:01f31e923fe2 | 319 | #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */ |
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0:01f31e923fe2 | 320 | #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */ |
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0:01f31e923fe2 | 321 | #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */ |
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0:01f31e923fe2 | 322 | #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */ |
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0:01f31e923fe2 | 323 | #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */ |
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0:01f31e923fe2 | 324 | #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */ |
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0:01f31e923fe2 | 325 | #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */ |
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0:01f31e923fe2 | 326 | #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */ |
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0:01f31e923fe2 | 327 | #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */ |
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0:01f31e923fe2 | 328 | #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */ |
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0:01f31e923fe2 | 329 | #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */ |
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0:01f31e923fe2 | 330 | #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */ |
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0:01f31e923fe2 | 331 | /**@} end of group ADC_RO_CAL0_register */ |
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0:01f31e923fe2 | 332 | |
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0:01f31e923fe2 | 333 | /** |
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0:01f31e923fe2 | 334 | * @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1 |
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0:01f31e923fe2 | 335 | * @ingroup adc_registers |
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0:01f31e923fe2 | 336 | * @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register |
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0:01f31e923fe2 | 337 | * @{ |
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0:01f31e923fe2 | 338 | */ |
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0:01f31e923fe2 | 339 | #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */ |
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0:01f31e923fe2 | 340 | #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */ |
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0:01f31e923fe2 | 341 | #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */ |
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0:01f31e923fe2 | 342 | #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */ |
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0:01f31e923fe2 | 343 | #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */ |
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0:01f31e923fe2 | 344 | #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */ |
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0:01f31e923fe2 | 345 | /**@} end of group RO_CAL1_register */ |
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0:01f31e923fe2 | 346 | |
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0:01f31e923fe2 | 347 | /** |
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0:01f31e923fe2 | 348 | * @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2 |
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0:01f31e923fe2 | 349 | * @ingroup adc_registers |
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0:01f31e923fe2 | 350 | * @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register |
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0:01f31e923fe2 | 351 | * @{ |
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0:01f31e923fe2 | 352 | */ |
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0:01f31e923fe2 | 353 | #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */ |
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0:01f31e923fe2 | 354 | #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */ |
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0:01f31e923fe2 | 355 | /**@} end of group RO_CAL2_register */ |
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0:01f31e923fe2 | 356 | |
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0:01f31e923fe2 | 357 | /** |
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0:01f31e923fe2 | 358 | * @defgroup ADC_CHSEL_values ADC Channel Select Values |
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0:01f31e923fe2 | 359 | * @ingroup ADC_CTRL_Register |
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0:01f31e923fe2 | 360 | * @brief Channel Select Values |
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0:01f31e923fe2 | 361 | * @{ |
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0:01f31e923fe2 | 362 | */ |
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0:01f31e923fe2 | 363 | #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */ |
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0:01f31e923fe2 | 364 | #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */ |
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0:01f31e923fe2 | 365 | #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */ |
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0:01f31e923fe2 | 366 | #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */ |
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0:01f31e923fe2 | 367 | #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */ |
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0:01f31e923fe2 | 368 | #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */ |
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0:01f31e923fe2 | 369 | #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */ |
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0:01f31e923fe2 | 370 | #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */ |
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0:01f31e923fe2 | 371 | #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */ |
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0:01f31e923fe2 | 372 | #define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */ |
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0:01f31e923fe2 | 373 | #define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */ |
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0:01f31e923fe2 | 374 | #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */ |
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0:01f31e923fe2 | 375 | #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */ |
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0:01f31e923fe2 | 376 | |
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0:01f31e923fe2 | 377 | /**@} end of group ADC_CHSEL_values */ |
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0:01f31e923fe2 | 378 | |
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0:01f31e923fe2 | 379 | #ifdef __cplusplus |
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0:01f31e923fe2 | 380 | } |
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0:01f31e923fe2 | 381 | #endif |
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0:01f31e923fe2 | 382 | |
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0:01f31e923fe2 | 383 | #endif /* _MXC_ADC_REGS_H_ */ |