Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32625/IO_Config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file IO_Config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "max32625.h"
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 #define EN_VDDIOH_PORT 3
Pawel Zarembski 0:01f31e923fe2 28 #define EN_VDDIOH_PIN 6
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 // The MAX14689 is powered with this pin
Pawel Zarembski 0:01f31e923fe2 31 #define IOH_OW_EN_PORT 2
Pawel Zarembski 0:01f31e923fe2 32 #define IOH_OW_EN_PIN 2
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 // Low selects NC pins HDR_OW and HDR_VIO
Pawel Zarembski 0:01f31e923fe2 35 // High selcts NO pins SWD_OW and SWD_VIO
Pawel Zarembski 0:01f31e923fe2 36 #define SWD_DIP_SEL_PORT 2
Pawel Zarembski 0:01f31e923fe2 37 #define SWD_DIP_SEL_PIN 3
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 // UART Tx
Pawel Zarembski 0:01f31e923fe2 40 #define PIN_TX_PORT 2
Pawel Zarembski 0:01f31e923fe2 41 #define PIN_TX_PIN 0
Pawel Zarembski 0:01f31e923fe2 42 #define PIN_DIP_TX_PORT 0
Pawel Zarembski 0:01f31e923fe2 43 #define PIN_DIP_TX_PIN 0
Pawel Zarembski 0:01f31e923fe2 44
Pawel Zarembski 0:01f31e923fe2 45 // UART Rx
Pawel Zarembski 0:01f31e923fe2 46 #define PIN_RX_PORT 2
Pawel Zarembski 0:01f31e923fe2 47 #define PIN_RX_PIN 1
Pawel Zarembski 0:01f31e923fe2 48 #define PIN_DIP_RX_PORT 0
Pawel Zarembski 0:01f31e923fe2 49 #define PIN_DIP_RX_PIN 1
Pawel Zarembski 0:01f31e923fe2 50
Pawel Zarembski 0:01f31e923fe2 51 // DAP LED
Pawel Zarembski 0:01f31e923fe2 52 #define PIN_DAP_LED_PORT 2
Pawel Zarembski 0:01f31e923fe2 53 #define PIN_DAP_LED_PIN 5
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 // MSD LED
Pawel Zarembski 0:01f31e923fe2 56 #define PIN_MSD_LED_PORT 2
Pawel Zarembski 0:01f31e923fe2 57 #define PIN_MSD_LED_PIN 4
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 // CDC LED
Pawel Zarembski 0:01f31e923fe2 60 #define PIN_CDC_LED_PORT 2
Pawel Zarembski 0:01f31e923fe2 61 #define PIN_CDC_LED_PIN 6
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 // Non-Forwarded Reset In Pin
Pawel Zarembski 0:01f31e923fe2 64 #define PIN_RESET_IN_NO_FWRD_PORT 2
Pawel Zarembski 0:01f31e923fe2 65 #define PIN_RESET_IN_NO_FWRD_PIN 7
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 // nRESET
Pawel Zarembski 0:01f31e923fe2 68 #define PIN_nRESET_PORT 3
Pawel Zarembski 0:01f31e923fe2 69 #define PIN_nRESET_PIN 7
Pawel Zarembski 0:01f31e923fe2 70 #define PIN_DIP_nRESET_PORT 0
Pawel Zarembski 0:01f31e923fe2 71 #define PIN_DIP_nRESET_PIN 4
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 // SWCLK
Pawel Zarembski 0:01f31e923fe2 74 #define PIN_SWCLK_PORT 3
Pawel Zarembski 0:01f31e923fe2 75 #define PIN_SWCLK_PIN 2
Pawel Zarembski 0:01f31e923fe2 76 #define PIN_DIP_SWCLK_PORT 0
Pawel Zarembski 0:01f31e923fe2 77 #define PIN_DIP_SWCLK_PIN 2
Pawel Zarembski 0:01f31e923fe2 78
Pawel Zarembski 0:01f31e923fe2 79 // SWDIO
Pawel Zarembski 0:01f31e923fe2 80 #define PIN_SWDIO_PORT 3
Pawel Zarembski 0:01f31e923fe2 81 #define PIN_SWDIO_PIN 3
Pawel Zarembski 0:01f31e923fe2 82 #define PIN_DIP_SWDIO_PORT 0
Pawel Zarembski 0:01f31e923fe2 83 #define PIN_DIP_SWDIO_PIN 3
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 // 1-Wire master I/O
Pawel Zarembski 0:01f31e923fe2 86 #define OWM_PORT 4
Pawel Zarembski 0:01f31e923fe2 87 #define OWM_PIN 0
Pawel Zarembski 0:01f31e923fe2 88 #define OWM_SUP_PORT 4
Pawel Zarembski 0:01f31e923fe2 89 #define OWM_SUP_PIN 1
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91 // ADC channels for target detection
Pawel Zarembski 0:01f31e923fe2 92 #define SWD_VIO_CH 5
Pawel Zarembski 0:01f31e923fe2 93 #define HDR_VIO_CH 4
Pawel Zarembski 0:01f31e923fe2 94 #define SWD_GNDDET_CH 3
Pawel Zarembski 0:01f31e923fe2 95 #define HDR_GNDDET_CH 2
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 typedef enum {
Pawel Zarembski 0:01f31e923fe2 98 IO_SWD_EXT,
Pawel Zarembski 0:01f31e923fe2 99 IO_DIP_EXT
Pawel Zarembski 0:01f31e923fe2 100 } TARGET_INTERFACE;
Pawel Zarembski 0:01f31e923fe2 101
Pawel Zarembski 0:01f31e923fe2 102 #define CDC_ACM_UART_SWD 2
Pawel Zarembski 0:01f31e923fe2 103 #define CDC_ACM_UART_DIP 0
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 #endif