Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32625/FlashPrg.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* CMSIS-DAP Interface Firmware
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2009-2013 ARM Limited
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Licensed under the Apache License, Version 2.0 (the "License");
Pawel Zarembski 0:01f31e923fe2 5 * you may not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 6 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 11 * distributed under the License is distributed on an "AS IS" BASIS,
Pawel Zarembski 0:01f31e923fe2 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 13 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 14 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 15 */
Pawel Zarembski 0:01f31e923fe2 16
Pawel Zarembski 0:01f31e923fe2 17 #include "FlashOS.h"
Pawel Zarembski 0:01f31e923fe2 18 #include "max32625.h"
Pawel Zarembski 0:01f31e923fe2 19 #include "flc_regs.h"
Pawel Zarembski 0:01f31e923fe2 20
Pawel Zarembski 0:01f31e923fe2 21 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 22 static inline int FLC_Busy(void)
Pawel Zarembski 0:01f31e923fe2 23 {
Pawel Zarembski 0:01f31e923fe2 24 return (MXC_FLC->ctrl & (MXC_F_FLC_CTRL_WRITE | MXC_F_FLC_CTRL_MASS_ERASE | MXC_F_FLC_CTRL_PAGE_ERASE));
Pawel Zarembski 0:01f31e923fe2 25 }
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 28 uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
Pawel Zarembski 0:01f31e923fe2 29 {
Pawel Zarembski 0:01f31e923fe2 30 /* Check if the flash controller is busy */
Pawel Zarembski 0:01f31e923fe2 31 if (FLC_Busy()) {
Pawel Zarembski 0:01f31e923fe2 32 return 1;
Pawel Zarembski 0:01f31e923fe2 33 }
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35 /* Enable automatic calculation of the clock divider to generate a 1MHz clock from the APB clock */
Pawel Zarembski 0:01f31e923fe2 36 MXC_FLC->perform |= MXC_F_FLC_PERFORM_AUTO_CLKDIV;
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 /* The flash controller will stall any reads while flash operations are in
Pawel Zarembski 0:01f31e923fe2 39 * progress. Disable the legacy failure detection logic that would flag reads
Pawel Zarembski 0:01f31e923fe2 40 * during flash operations as errors.
Pawel Zarembski 0:01f31e923fe2 41 */
Pawel Zarembski 0:01f31e923fe2 42 MXC_FLC->perform |= MXC_F_FLC_PERFORM_EN_PREVENT_FAIL;
Pawel Zarembski 0:01f31e923fe2 43
Pawel Zarembski 0:01f31e923fe2 44 return 0;
Pawel Zarembski 0:01f31e923fe2 45 }
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 48 uint32_t UnInit(uint32_t fnc)
Pawel Zarembski 0:01f31e923fe2 49 {
Pawel Zarembski 0:01f31e923fe2 50 /* Lock flash */
Pawel Zarembski 0:01f31e923fe2 51 MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
Pawel Zarembski 0:01f31e923fe2 52
Pawel Zarembski 0:01f31e923fe2 53 return 0; // Finished without Errors
Pawel Zarembski 0:01f31e923fe2 54 }
Pawel Zarembski 0:01f31e923fe2 55
Pawel Zarembski 0:01f31e923fe2 56 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 57 /*
Pawel Zarembski 0:01f31e923fe2 58 * Erase complete Flash Memory
Pawel Zarembski 0:01f31e923fe2 59 * Return Value: 0 - OK, 1 - Failed
Pawel Zarembski 0:01f31e923fe2 60 */
Pawel Zarembski 0:01f31e923fe2 61 int EraseChip(void)
Pawel Zarembski 0:01f31e923fe2 62 {
Pawel Zarembski 0:01f31e923fe2 63 /* Check if the flash controller is busy */
Pawel Zarembski 0:01f31e923fe2 64 if (FLC_Busy()) {
Pawel Zarembski 0:01f31e923fe2 65 return 1;
Pawel Zarembski 0:01f31e923fe2 66 }
Pawel Zarembski 0:01f31e923fe2 67
Pawel Zarembski 0:01f31e923fe2 68 /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
Pawel Zarembski 0:01f31e923fe2 69 MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 /* Unlock flash */
Pawel Zarembski 0:01f31e923fe2 72 MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 /* Write the Erase Code */
Pawel Zarembski 0:01f31e923fe2 75 MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | (MXC_V_FLC_ERASE_CODE_MASS_ERASE << MXC_F_FLC_CTRL_ERASE_CODE_POS);
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 /* Start the mass erase */
Pawel Zarembski 0:01f31e923fe2 78 MXC_FLC->ctrl |= MXC_F_FLC_CTRL_MASS_ERASE;
Pawel Zarembski 0:01f31e923fe2 79
Pawel Zarembski 0:01f31e923fe2 80 /* Wait until flash operation is complete */
Pawel Zarembski 0:01f31e923fe2 81 while (FLC_Busy());
Pawel Zarembski 0:01f31e923fe2 82
Pawel Zarembski 0:01f31e923fe2 83 /* Lock flash */
Pawel Zarembski 0:01f31e923fe2 84 MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
Pawel Zarembski 0:01f31e923fe2 85
Pawel Zarembski 0:01f31e923fe2 86 /* Check for failures */
Pawel Zarembski 0:01f31e923fe2 87 if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
Pawel Zarembski 0:01f31e923fe2 88 /* Interrupt flags can only be written to zero, so this is safe */
Pawel Zarembski 0:01f31e923fe2 89 MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
Pawel Zarembski 0:01f31e923fe2 90 return 1;
Pawel Zarembski 0:01f31e923fe2 91 }
Pawel Zarembski 0:01f31e923fe2 92
Pawel Zarembski 0:01f31e923fe2 93 return 0;
Pawel Zarembski 0:01f31e923fe2 94 }
Pawel Zarembski 0:01f31e923fe2 95
Pawel Zarembski 0:01f31e923fe2 96 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 97 /*
Pawel Zarembski 0:01f31e923fe2 98 * Erase Sector in Flash Memory
Pawel Zarembski 0:01f31e923fe2 99 * Parameter: address: Sector Address
Pawel Zarembski 0:01f31e923fe2 100 * Return Value: 0 - OK, 1 - Failed
Pawel Zarembski 0:01f31e923fe2 101 */
Pawel Zarembski 0:01f31e923fe2 102 int EraseSector(unsigned long address)
Pawel Zarembski 0:01f31e923fe2 103 {
Pawel Zarembski 0:01f31e923fe2 104 /* Wait until flash operation is complete */
Pawel Zarembski 0:01f31e923fe2 105 while (FLC_Busy());
Pawel Zarembski 0:01f31e923fe2 106
Pawel Zarembski 0:01f31e923fe2 107 /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
Pawel Zarembski 0:01f31e923fe2 108 MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
Pawel Zarembski 0:01f31e923fe2 109
Pawel Zarembski 0:01f31e923fe2 110 /* Unlock flash */
Pawel Zarembski 0:01f31e923fe2 111 MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 /* Write page erase code */
Pawel Zarembski 0:01f31e923fe2 114 MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | (MXC_V_FLC_ERASE_CODE_PAGE_ERASE << MXC_F_FLC_CTRL_ERASE_CODE_POS);
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 /* Erase the request page */
Pawel Zarembski 0:01f31e923fe2 117 MXC_FLC->faddr = address;
Pawel Zarembski 0:01f31e923fe2 118 MXC_FLC->ctrl |= MXC_F_FLC_CTRL_PAGE_ERASE;
Pawel Zarembski 0:01f31e923fe2 119
Pawel Zarembski 0:01f31e923fe2 120 /* Wait until flash operation is complete */
Pawel Zarembski 0:01f31e923fe2 121 while (FLC_Busy());
Pawel Zarembski 0:01f31e923fe2 122
Pawel Zarembski 0:01f31e923fe2 123 /* Lock flash */
Pawel Zarembski 0:01f31e923fe2 124 MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126 /* Check for failures */
Pawel Zarembski 0:01f31e923fe2 127 if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
Pawel Zarembski 0:01f31e923fe2 128 /* Interrupt flags can only be written to zero, so this is safe */
Pawel Zarembski 0:01f31e923fe2 129 MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
Pawel Zarembski 0:01f31e923fe2 130 return 1;
Pawel Zarembski 0:01f31e923fe2 131 }
Pawel Zarembski 0:01f31e923fe2 132
Pawel Zarembski 0:01f31e923fe2 133 return 0;
Pawel Zarembski 0:01f31e923fe2 134 }
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 /******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 137 /*
Pawel Zarembski 0:01f31e923fe2 138 * Program Page in Flash Memory
Pawel Zarembski 0:01f31e923fe2 139 * Parameter: address: Page Start Address
Pawel Zarembski 0:01f31e923fe2 140 * size: Page Size
Pawel Zarembski 0:01f31e923fe2 141 * buffer: Page Data
Pawel Zarembski 0:01f31e923fe2 142 * Return Value: 0 - OK, 1 - Failed
Pawel Zarembski 0:01f31e923fe2 143 */
Pawel Zarembski 0:01f31e923fe2 144 int ProgramPage(unsigned long address, unsigned long size, unsigned char *buffer8)
Pawel Zarembski 0:01f31e923fe2 145 {
Pawel Zarembski 0:01f31e923fe2 146 unsigned long remaining = size;
Pawel Zarembski 0:01f31e923fe2 147 unsigned long *buffer = (unsigned long *)buffer8;
Pawel Zarembski 0:01f31e923fe2 148
Pawel Zarembski 0:01f31e923fe2 149 // Only accept 32-bit aligned pointers
Pawel Zarembski 0:01f31e923fe2 150 if ((unsigned long)buffer8 & 0x3) {
Pawel Zarembski 0:01f31e923fe2 151 return 1;
Pawel Zarembski 0:01f31e923fe2 152 }
Pawel Zarembski 0:01f31e923fe2 153 buffer = (unsigned long *)buffer8;
Pawel Zarembski 0:01f31e923fe2 154
Pawel Zarembski 0:01f31e923fe2 155 /* Check if the flash controller is busy */
Pawel Zarembski 0:01f31e923fe2 156 if (FLC_Busy()) {
Pawel Zarembski 0:01f31e923fe2 157 return 1;
Pawel Zarembski 0:01f31e923fe2 158 }
Pawel Zarembski 0:01f31e923fe2 159
Pawel Zarembski 0:01f31e923fe2 160 /* Unlock flash */
Pawel Zarembski 0:01f31e923fe2 161 MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
Pawel Zarembski 0:01f31e923fe2 162
Pawel Zarembski 0:01f31e923fe2 163 while (remaining >= 4) {
Pawel Zarembski 0:01f31e923fe2 164 MXC_FLC->faddr = address;
Pawel Zarembski 0:01f31e923fe2 165 MXC_FLC->fdata = *buffer++;
Pawel Zarembski 0:01f31e923fe2 166 MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE_ENABLE;
Pawel Zarembski 0:01f31e923fe2 167 MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE;
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 /* Wait until flash operation is complete */
Pawel Zarembski 0:01f31e923fe2 170 while (FLC_Busy());
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 address += 4;
Pawel Zarembski 0:01f31e923fe2 173 remaining -= 4;
Pawel Zarembski 0:01f31e923fe2 174 }
Pawel Zarembski 0:01f31e923fe2 175
Pawel Zarembski 0:01f31e923fe2 176 if (remaining > 0) {
Pawel Zarembski 0:01f31e923fe2 177 uint32_t last_word;
Pawel Zarembski 0:01f31e923fe2 178 uint32_t mask;
Pawel Zarembski 0:01f31e923fe2 179
Pawel Zarembski 0:01f31e923fe2 180 last_word = 0xffffffff;
Pawel Zarembski 0:01f31e923fe2 181 mask = 0xff;
Pawel Zarembski 0:01f31e923fe2 182
Pawel Zarembski 0:01f31e923fe2 183 while (remaining > 0) {
Pawel Zarembski 0:01f31e923fe2 184 last_word &= (*buffer | ~mask);
Pawel Zarembski 0:01f31e923fe2 185 mask <<= 8;
Pawel Zarembski 0:01f31e923fe2 186 remaining--;
Pawel Zarembski 0:01f31e923fe2 187 }
Pawel Zarembski 0:01f31e923fe2 188
Pawel Zarembski 0:01f31e923fe2 189 MXC_FLC->faddr = address;
Pawel Zarembski 0:01f31e923fe2 190 MXC_FLC->fdata = last_word;
Pawel Zarembski 0:01f31e923fe2 191 MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE_ENABLE;
Pawel Zarembski 0:01f31e923fe2 192
Pawel Zarembski 0:01f31e923fe2 193 /* Wait until flash operation is complete */
Pawel Zarembski 0:01f31e923fe2 194 while (FLC_Busy());
Pawel Zarembski 0:01f31e923fe2 195 }
Pawel Zarembski 0:01f31e923fe2 196
Pawel Zarembski 0:01f31e923fe2 197 /* Lock flash */
Pawel Zarembski 0:01f31e923fe2 198 MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
Pawel Zarembski 0:01f31e923fe2 199
Pawel Zarembski 0:01f31e923fe2 200 /* Check for failures */
Pawel Zarembski 0:01f31e923fe2 201 if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
Pawel Zarembski 0:01f31e923fe2 202 /* Interrupt flags can only be written to zero, so this is safe */
Pawel Zarembski 0:01f31e923fe2 203 MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
Pawel Zarembski 0:01f31e923fe2 204 return 1;
Pawel Zarembski 0:01f31e923fe2 205 }
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207 return 0;
Pawel Zarembski 0:01f31e923fe2 208 }