Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32620/pwrman_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /******************************************************************************* |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
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0:01f31e923fe2 | 3 | * |
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0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
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0:01f31e923fe2 | 32 | ******************************************************************************/ |
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0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | #ifndef _MXC_PWRMAN_REGS_H_ |
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0:01f31e923fe2 | 35 | #define _MXC_PWRMAN_REGS_H_ |
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0:01f31e923fe2 | 36 | |
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0:01f31e923fe2 | 37 | #ifdef __cplusplus |
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0:01f31e923fe2 | 38 | extern "C" { |
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0:01f31e923fe2 | 39 | #endif |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #include <stdint.h> |
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0:01f31e923fe2 | 42 | |
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0:01f31e923fe2 | 43 | /* |
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0:01f31e923fe2 | 44 | If types are not defined elsewhere (CMSIS) define them here |
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0:01f31e923fe2 | 45 | */ |
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0:01f31e923fe2 | 46 | #ifndef __IO |
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0:01f31e923fe2 | 47 | #define __IO volatile |
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0:01f31e923fe2 | 48 | #endif |
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0:01f31e923fe2 | 49 | #ifndef __I |
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0:01f31e923fe2 | 50 | #define __I volatile const |
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0:01f31e923fe2 | 51 | #endif |
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0:01f31e923fe2 | 52 | #ifndef __O |
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0:01f31e923fe2 | 53 | #define __O volatile |
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0:01f31e923fe2 | 54 | #endif |
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0:01f31e923fe2 | 55 | #ifndef __R |
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0:01f31e923fe2 | 56 | #define __R volatile const |
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0:01f31e923fe2 | 57 | #endif |
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0:01f31e923fe2 | 58 | |
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0:01f31e923fe2 | 59 | |
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0:01f31e923fe2 | 60 | /** |
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0:01f31e923fe2 | 61 | * @brief Defines PAD Modes for Wake Up Detection. |
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0:01f31e923fe2 | 62 | */ |
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0:01f31e923fe2 | 63 | typedef enum { |
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0:01f31e923fe2 | 64 | /** WUD Mode for Selected PAD = Clear/Activate */ |
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0:01f31e923fe2 | 65 | MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, |
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0:01f31e923fe2 | 66 | /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ |
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0:01f31e923fe2 | 67 | MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, |
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0:01f31e923fe2 | 68 | /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ |
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0:01f31e923fe2 | 69 | MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, |
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0:01f31e923fe2 | 70 | /** WUD Mode for Selected PAD = No pad state change */ |
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0:01f31e923fe2 | 71 | MXC_E_PWRMAN_PAD_MODE_NONE |
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0:01f31e923fe2 | 72 | } |
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0:01f31e923fe2 | 73 | mxc_pwrman_pad_mode_t; |
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0:01f31e923fe2 | 74 | |
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0:01f31e923fe2 | 75 | /* |
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0:01f31e923fe2 | 76 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
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0:01f31e923fe2 | 77 | access to each register in module. |
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0:01f31e923fe2 | 78 | */ |
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0:01f31e923fe2 | 79 | |
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0:01f31e923fe2 | 80 | /* Offset Register Description |
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0:01f31e923fe2 | 81 | ============= ============================================================================ */ |
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0:01f31e923fe2 | 82 | typedef struct { |
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0:01f31e923fe2 | 83 | __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ |
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0:01f31e923fe2 | 84 | __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ |
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0:01f31e923fe2 | 85 | __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ |
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0:01f31e923fe2 | 86 | __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ |
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0:01f31e923fe2 | 87 | __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ |
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0:01f31e923fe2 | 88 | __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ |
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0:01f31e923fe2 | 89 | __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ |
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0:01f31e923fe2 | 90 | __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */ |
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0:01f31e923fe2 | 91 | __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */ |
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0:01f31e923fe2 | 92 | __R uint32_t rsv024[3]; /* 0x0024-0x002C */ |
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0:01f31e923fe2 | 93 | __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */ |
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0:01f31e923fe2 | 94 | __R uint32_t rsv034; /* 0x0034 */ |
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0:01f31e923fe2 | 95 | __IO uint32_t die_type; /* 0x0038 Die Type ID Register */ |
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0:01f31e923fe2 | 96 | __IO uint32_t base_part_num; /* 0x003C Base Part Number */ |
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0:01f31e923fe2 | 97 | __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ |
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0:01f31e923fe2 | 98 | __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ |
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0:01f31e923fe2 | 99 | __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ |
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0:01f31e923fe2 | 100 | } mxc_pwrman_regs_t; |
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0:01f31e923fe2 | 101 | |
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0:01f31e923fe2 | 102 | |
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0:01f31e923fe2 | 103 | /* |
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0:01f31e923fe2 | 104 | Register offsets for module PWRMAN. |
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0:01f31e923fe2 | 105 | */ |
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0:01f31e923fe2 | 106 | |
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0:01f31e923fe2 | 107 | #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) |
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0:01f31e923fe2 | 108 | #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) |
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0:01f31e923fe2 | 109 | #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) |
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0:01f31e923fe2 | 110 | #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) |
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0:01f31e923fe2 | 111 | #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) |
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0:01f31e923fe2 | 112 | #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) |
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0:01f31e923fe2 | 113 | #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) |
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0:01f31e923fe2 | 114 | #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL) |
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0:01f31e923fe2 | 115 | #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL) |
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0:01f31e923fe2 | 116 | #define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL) |
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0:01f31e923fe2 | 117 | #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) |
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0:01f31e923fe2 | 118 | #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) |
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0:01f31e923fe2 | 119 | #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) |
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0:01f31e923fe2 | 120 | #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) |
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0:01f31e923fe2 | 121 | #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) |
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0:01f31e923fe2 | 122 | |
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0:01f31e923fe2 | 123 | |
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0:01f31e923fe2 | 124 | /* |
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0:01f31e923fe2 | 125 | Field positions and masks for module PWRMAN. |
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0:01f31e923fe2 | 126 | */ |
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0:01f31e923fe2 | 127 | |
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0:01f31e923fe2 | 128 | #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 |
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0:01f31e923fe2 | 129 | #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) |
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0:01f31e923fe2 | 130 | #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 |
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0:01f31e923fe2 | 131 | #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) |
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0:01f31e923fe2 | 132 | #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 |
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0:01f31e923fe2 | 133 | #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) |
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0:01f31e923fe2 | 134 | #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 |
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0:01f31e923fe2 | 135 | #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) |
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0:01f31e923fe2 | 136 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 |
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0:01f31e923fe2 | 137 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) |
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0:01f31e923fe2 | 138 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 |
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0:01f31e923fe2 | 139 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) |
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0:01f31e923fe2 | 140 | #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 |
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0:01f31e923fe2 | 141 | #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) |
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0:01f31e923fe2 | 142 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17 |
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0:01f31e923fe2 | 143 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) |
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0:01f31e923fe2 | 144 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18 |
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0:01f31e923fe2 | 145 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) |
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0:01f31e923fe2 | 146 | #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19 |
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0:01f31e923fe2 | 147 | #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) |
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0:01f31e923fe2 | 148 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20 |
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0:01f31e923fe2 | 149 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) |
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0:01f31e923fe2 | 150 | #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 |
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0:01f31e923fe2 | 151 | #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) |
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0:01f31e923fe2 | 152 | #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 |
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0:01f31e923fe2 | 153 | #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) |
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0:01f31e923fe2 | 154 | #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 |
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0:01f31e923fe2 | 155 | #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) |
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0:01f31e923fe2 | 156 | |
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0:01f31e923fe2 | 157 | #define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0 |
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0:01f31e923fe2 | 158 | #define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS)) |
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0:01f31e923fe2 | 159 | #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1 |
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0:01f31e923fe2 | 160 | #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) |
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0:01f31e923fe2 | 161 | #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 |
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0:01f31e923fe2 | 162 | #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) |
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0:01f31e923fe2 | 163 | #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3 |
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0:01f31e923fe2 | 164 | #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) |
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0:01f31e923fe2 | 165 | #define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4 |
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0:01f31e923fe2 | 166 | #define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS)) |
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0:01f31e923fe2 | 167 | #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5 |
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0:01f31e923fe2 | 168 | #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS)) |
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0:01f31e923fe2 | 169 | #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6 |
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0:01f31e923fe2 | 170 | #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS)) |
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0:01f31e923fe2 | 171 | |
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0:01f31e923fe2 | 172 | #define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0 |
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0:01f31e923fe2 | 173 | #define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS)) |
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0:01f31e923fe2 | 174 | #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1 |
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0:01f31e923fe2 | 175 | #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) |
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0:01f31e923fe2 | 176 | #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 |
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0:01f31e923fe2 | 177 | #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) |
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0:01f31e923fe2 | 178 | #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3 |
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0:01f31e923fe2 | 179 | #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) |
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0:01f31e923fe2 | 180 | #define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4 |
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0:01f31e923fe2 | 181 | #define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS)) |
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0:01f31e923fe2 | 182 | #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5 |
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0:01f31e923fe2 | 183 | #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS)) |
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0:01f31e923fe2 | 184 | #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6 |
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0:01f31e923fe2 | 185 | #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS)) |
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0:01f31e923fe2 | 186 | |
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0:01f31e923fe2 | 187 | #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0 |
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0:01f31e923fe2 | 188 | #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS)) |
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0:01f31e923fe2 | 189 | #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1 |
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0:01f31e923fe2 | 190 | #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) |
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0:01f31e923fe2 | 191 | #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 |
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0:01f31e923fe2 | 192 | #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) |
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0:01f31e923fe2 | 193 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3 |
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0:01f31e923fe2 | 194 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) |
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0:01f31e923fe2 | 195 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4 |
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0:01f31e923fe2 | 196 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS)) |
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0:01f31e923fe2 | 197 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5 |
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0:01f31e923fe2 | 198 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS)) |
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0:01f31e923fe2 | 199 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6 |
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0:01f31e923fe2 | 200 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS)) |
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0:01f31e923fe2 | 201 | |
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0:01f31e923fe2 | 202 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 |
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0:01f31e923fe2 | 203 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) |
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0:01f31e923fe2 | 204 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 |
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0:01f31e923fe2 | 205 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) |
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0:01f31e923fe2 | 206 | #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 |
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0:01f31e923fe2 | 207 | #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) |
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0:01f31e923fe2 | 208 | #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16 |
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0:01f31e923fe2 | 209 | #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS)) |
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0:01f31e923fe2 | 210 | |
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0:01f31e923fe2 | 211 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 |
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0:01f31e923fe2 | 212 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) |
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0:01f31e923fe2 | 213 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 |
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0:01f31e923fe2 | 214 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) |
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0:01f31e923fe2 | 215 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 |
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0:01f31e923fe2 | 216 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) |
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0:01f31e923fe2 | 217 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 |
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0:01f31e923fe2 | 218 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) |
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0:01f31e923fe2 | 219 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 |
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0:01f31e923fe2 | 220 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) |
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0:01f31e923fe2 | 221 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 |
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0:01f31e923fe2 | 222 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) |
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0:01f31e923fe2 | 223 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 |
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0:01f31e923fe2 | 224 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) |
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0:01f31e923fe2 | 225 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 |
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0:01f31e923fe2 | 226 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) |
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0:01f31e923fe2 | 227 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 |
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0:01f31e923fe2 | 228 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) |
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0:01f31e923fe2 | 229 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 |
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0:01f31e923fe2 | 230 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) |
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0:01f31e923fe2 | 231 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 |
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0:01f31e923fe2 | 232 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) |
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0:01f31e923fe2 | 233 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 |
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0:01f31e923fe2 | 234 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) |
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0:01f31e923fe2 | 235 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 |
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0:01f31e923fe2 | 236 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) |
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0:01f31e923fe2 | 237 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 |
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0:01f31e923fe2 | 238 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) |
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0:01f31e923fe2 | 239 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 |
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0:01f31e923fe2 | 240 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) |
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0:01f31e923fe2 | 241 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 |
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0:01f31e923fe2 | 242 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) |
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0:01f31e923fe2 | 243 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 |
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0:01f31e923fe2 | 244 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) |
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0:01f31e923fe2 | 245 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 |
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0:01f31e923fe2 | 246 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) |
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0:01f31e923fe2 | 247 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 |
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0:01f31e923fe2 | 248 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) |
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0:01f31e923fe2 | 249 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 |
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0:01f31e923fe2 | 250 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) |
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0:01f31e923fe2 | 251 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 |
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0:01f31e923fe2 | 252 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) |
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0:01f31e923fe2 | 253 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 |
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0:01f31e923fe2 | 254 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) |
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0:01f31e923fe2 | 255 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 |
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0:01f31e923fe2 | 256 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) |
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0:01f31e923fe2 | 257 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 |
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0:01f31e923fe2 | 258 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) |
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0:01f31e923fe2 | 259 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 |
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0:01f31e923fe2 | 260 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) |
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0:01f31e923fe2 | 261 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 |
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0:01f31e923fe2 | 262 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) |
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0:01f31e923fe2 | 263 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 |
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0:01f31e923fe2 | 264 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) |
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0:01f31e923fe2 | 265 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 |
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0:01f31e923fe2 | 266 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) |
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0:01f31e923fe2 | 267 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 |
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0:01f31e923fe2 | 268 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) |
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0:01f31e923fe2 | 269 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 |
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0:01f31e923fe2 | 270 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) |
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0:01f31e923fe2 | 271 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 |
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0:01f31e923fe2 | 272 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) |
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0:01f31e923fe2 | 273 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 |
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0:01f31e923fe2 | 274 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) |
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0:01f31e923fe2 | 275 | |
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0:01f31e923fe2 | 276 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 |
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0:01f31e923fe2 | 277 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) |
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0:01f31e923fe2 | 278 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 |
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0:01f31e923fe2 | 279 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) |
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0:01f31e923fe2 | 280 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 |
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0:01f31e923fe2 | 281 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) |
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0:01f31e923fe2 | 282 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 |
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0:01f31e923fe2 | 283 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) |
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0:01f31e923fe2 | 284 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 |
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0:01f31e923fe2 | 285 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) |
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0:01f31e923fe2 | 286 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 |
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0:01f31e923fe2 | 287 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) |
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0:01f31e923fe2 | 288 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 |
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0:01f31e923fe2 | 289 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) |
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0:01f31e923fe2 | 290 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 |
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0:01f31e923fe2 | 291 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) |
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0:01f31e923fe2 | 292 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 |
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0:01f31e923fe2 | 293 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) |
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0:01f31e923fe2 | 294 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 |
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0:01f31e923fe2 | 295 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) |
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0:01f31e923fe2 | 296 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 |
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0:01f31e923fe2 | 297 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) |
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0:01f31e923fe2 | 298 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 |
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0:01f31e923fe2 | 299 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) |
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0:01f31e923fe2 | 300 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 |
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0:01f31e923fe2 | 301 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) |
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0:01f31e923fe2 | 302 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 |
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0:01f31e923fe2 | 303 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) |
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0:01f31e923fe2 | 304 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 |
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0:01f31e923fe2 | 305 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) |
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0:01f31e923fe2 | 306 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 |
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0:01f31e923fe2 | 307 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) |
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0:01f31e923fe2 | 308 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 |
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0:01f31e923fe2 | 309 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) |
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0:01f31e923fe2 | 310 | |
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0:01f31e923fe2 | 311 | #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0 |
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0:01f31e923fe2 | 312 | #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS)) |
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0:01f31e923fe2 | 313 | |
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0:01f31e923fe2 | 314 | #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 |
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0:01f31e923fe2 | 315 | #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) |
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0:01f31e923fe2 | 316 | |
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0:01f31e923fe2 | 317 | #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 |
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0:01f31e923fe2 | 318 | #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) |
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0:01f31e923fe2 | 319 | #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 |
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0:01f31e923fe2 | 320 | #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) |
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0:01f31e923fe2 | 321 | |
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0:01f31e923fe2 | 322 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 |
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0:01f31e923fe2 | 323 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) |
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0:01f31e923fe2 | 324 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 |
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0:01f31e923fe2 | 325 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) |
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0:01f31e923fe2 | 326 | |
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0:01f31e923fe2 | 327 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0 |
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0:01f31e923fe2 | 328 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) |
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0:01f31e923fe2 | 329 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1 |
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0:01f31e923fe2 | 330 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS)) |
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0:01f31e923fe2 | 331 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2 |
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0:01f31e923fe2 | 332 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS)) |
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0:01f31e923fe2 | 333 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3 |
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0:01f31e923fe2 | 334 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) |
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0:01f31e923fe2 | 335 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4 |
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0:01f31e923fe2 | 336 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) |
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0:01f31e923fe2 | 337 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5 |
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0:01f31e923fe2 | 338 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) |
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0:01f31e923fe2 | 339 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 |
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0:01f31e923fe2 | 340 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) |
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0:01f31e923fe2 | 341 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7 |
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0:01f31e923fe2 | 342 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) |
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0:01f31e923fe2 | 343 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8 |
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0:01f31e923fe2 | 344 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) |
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0:01f31e923fe2 | 345 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9 |
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0:01f31e923fe2 | 346 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) |
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0:01f31e923fe2 | 347 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10 |
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0:01f31e923fe2 | 348 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) |
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0:01f31e923fe2 | 349 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11 |
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0:01f31e923fe2 | 350 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) |
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0:01f31e923fe2 | 351 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12 |
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0:01f31e923fe2 | 352 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS)) |
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0:01f31e923fe2 | 353 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13 |
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0:01f31e923fe2 | 354 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS)) |
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0:01f31e923fe2 | 355 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14 |
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0:01f31e923fe2 | 356 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) |
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0:01f31e923fe2 | 357 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15 |
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0:01f31e923fe2 | 358 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) |
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0:01f31e923fe2 | 359 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16 |
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0:01f31e923fe2 | 360 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) |
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0:01f31e923fe2 | 361 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17 |
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0:01f31e923fe2 | 362 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS)) |
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0:01f31e923fe2 | 363 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18 |
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0:01f31e923fe2 | 364 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS)) |
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0:01f31e923fe2 | 365 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19 |
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0:01f31e923fe2 | 366 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) |
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0:01f31e923fe2 | 367 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20 |
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0:01f31e923fe2 | 368 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) |
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0:01f31e923fe2 | 369 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21 |
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0:01f31e923fe2 | 370 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS)) |
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0:01f31e923fe2 | 371 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 |
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0:01f31e923fe2 | 372 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) |
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0:01f31e923fe2 | 373 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23 |
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0:01f31e923fe2 | 374 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS)) |
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0:01f31e923fe2 | 375 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24 |
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0:01f31e923fe2 | 376 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS)) |
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0:01f31e923fe2 | 377 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25 |
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0:01f31e923fe2 | 378 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS)) |
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0:01f31e923fe2 | 379 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26 |
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0:01f31e923fe2 | 380 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS)) |
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0:01f31e923fe2 | 381 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27 |
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0:01f31e923fe2 | 382 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS)) |
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0:01f31e923fe2 | 383 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28 |
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0:01f31e923fe2 | 384 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) |
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0:01f31e923fe2 | 385 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29 |
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0:01f31e923fe2 | 386 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS)) |
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0:01f31e923fe2 | 387 | |
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0:01f31e923fe2 | 388 | |
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0:01f31e923fe2 | 389 | |
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0:01f31e923fe2 | 390 | #ifdef __cplusplus |
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0:01f31e923fe2 | 391 | } |
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0:01f31e923fe2 | 392 | #endif |
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0:01f31e923fe2 | 393 | |
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0:01f31e923fe2 | 394 | #endif /* _MXC_PWRMAN_REGS_H_ */ |