Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/maxim/max32620/flc_regs.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /******************************************************************************* |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
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0:01f31e923fe2 | 3 | * |
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0:01f31e923fe2 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Pawel Zarembski |
0:01f31e923fe2 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Pawel Zarembski |
0:01f31e923fe2 | 6 | * to deal in the Software without restriction, including without limitation |
| Pawel Zarembski |
0:01f31e923fe2 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Pawel Zarembski |
0:01f31e923fe2 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Pawel Zarembski |
0:01f31e923fe2 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * The above copyright notice and this permission notice shall be included |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * in all copies or substantial portions of the Software. |
| Pawel Zarembski |
0:01f31e923fe2 | 13 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Pawel Zarembski |
0:01f31e923fe2 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Pawel Zarembski |
0:01f31e923fe2 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Pawel Zarembski |
0:01f31e923fe2 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Pawel Zarembski |
0:01f31e923fe2 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Pawel Zarembski |
0:01f31e923fe2 | 21 | * |
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0:01f31e923fe2 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Pawel Zarembski |
0:01f31e923fe2 | 24 | * Products, Inc. Branding Policy. |
| Pawel Zarembski |
0:01f31e923fe2 | 25 | * |
| Pawel Zarembski |
0:01f31e923fe2 | 26 | * The mere transfer of this software does not imply any licenses |
| Pawel Zarembski |
0:01f31e923fe2 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Pawel Zarembski |
0:01f31e923fe2 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Pawel Zarembski |
0:01f31e923fe2 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Pawel Zarembski |
0:01f31e923fe2 | 30 | * ownership rights. |
| Pawel Zarembski |
0:01f31e923fe2 | 31 | * |
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0:01f31e923fe2 | 32 | ******************************************************************************/ |
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0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | #ifndef _MXC_FLC_REGS_H_ |
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0:01f31e923fe2 | 35 | #define _MXC_FLC_REGS_H_ |
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0:01f31e923fe2 | 36 | |
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0:01f31e923fe2 | 37 | #ifdef __cplusplus |
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0:01f31e923fe2 | 38 | extern "C" { |
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0:01f31e923fe2 | 39 | #endif |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | #include <stdint.h> |
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0:01f31e923fe2 | 42 | |
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0:01f31e923fe2 | 43 | /* |
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0:01f31e923fe2 | 44 | If types are not defined elsewhere (CMSIS) define them here |
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0:01f31e923fe2 | 45 | */ |
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0:01f31e923fe2 | 46 | #ifndef __IO |
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0:01f31e923fe2 | 47 | #define __IO volatile |
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0:01f31e923fe2 | 48 | #endif |
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0:01f31e923fe2 | 49 | #ifndef __I |
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0:01f31e923fe2 | 50 | #define __I volatile const |
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0:01f31e923fe2 | 51 | #endif |
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0:01f31e923fe2 | 52 | #ifndef __O |
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0:01f31e923fe2 | 53 | #define __O volatile |
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0:01f31e923fe2 | 54 | #endif |
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0:01f31e923fe2 | 55 | #ifndef __R |
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0:01f31e923fe2 | 56 | #define __R volatile const |
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0:01f31e923fe2 | 57 | #endif |
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0:01f31e923fe2 | 58 | |
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0:01f31e923fe2 | 59 | |
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0:01f31e923fe2 | 60 | #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) |
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0:01f31e923fe2 | 61 | #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) |
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0:01f31e923fe2 | 62 | #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) |
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0:01f31e923fe2 | 63 | |
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0:01f31e923fe2 | 64 | /* |
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0:01f31e923fe2 | 65 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
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0:01f31e923fe2 | 66 | access to each register in module. |
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0:01f31e923fe2 | 67 | */ |
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0:01f31e923fe2 | 68 | |
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0:01f31e923fe2 | 69 | /* Offset Register Description |
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0:01f31e923fe2 | 70 | ============= ============================================================================ */ |
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0:01f31e923fe2 | 71 | typedef struct { |
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0:01f31e923fe2 | 72 | __IO uint32_t faddr; /* 0x0000 Flash Operation Address */ |
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0:01f31e923fe2 | 73 | __IO uint32_t fckdiv; /* 0x0004 Flash Clock Pulse Divisor */ |
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0:01f31e923fe2 | 74 | __IO uint32_t ctrl; /* 0x0008 Flash Control Register */ |
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0:01f31e923fe2 | 75 | __R uint32_t rsv00C[6]; /* 0x000C-0x0020 */ |
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0:01f31e923fe2 | 76 | __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */ |
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0:01f31e923fe2 | 77 | __R uint32_t rsv028[2]; /* 0x0028-0x002C */ |
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0:01f31e923fe2 | 78 | __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */ |
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0:01f31e923fe2 | 79 | __R uint32_t rsv034[7]; /* 0x0034-0x004C */ |
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0:01f31e923fe2 | 80 | __IO uint32_t perform; /* 0x0050 Flash Performance Settings */ |
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0:01f31e923fe2 | 81 | __IO uint32_t tacc; /* 0x0054 Flash Read Cycle Config */ |
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0:01f31e923fe2 | 82 | __IO uint32_t tprog; /* 0x0058 Flash Write Cycle Config */ |
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0:01f31e923fe2 | 83 | __R uint32_t rsv05C[9]; /* 0x005C-0x007C */ |
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0:01f31e923fe2 | 84 | __IO uint32_t status; /* 0x0080 Security Status Flags */ |
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0:01f31e923fe2 | 85 | __R uint32_t rsv084; /* 0x0084 */ |
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0:01f31e923fe2 | 86 | __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */ |
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0:01f31e923fe2 | 87 | __R uint32_t rsv08C[4]; /* 0x008C-0x0098 */ |
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0:01f31e923fe2 | 88 | __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */ |
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0:01f31e923fe2 | 89 | __R uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */ |
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0:01f31e923fe2 | 90 | __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */ |
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0:01f31e923fe2 | 91 | __R uint32_t rsv104[15]; /* 0x0104-0x013C */ |
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0:01f31e923fe2 | 92 | __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */ |
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0:01f31e923fe2 | 93 | __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */ |
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0:01f31e923fe2 | 94 | __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */ |
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0:01f31e923fe2 | 95 | __R uint32_t rsv14C[9]; /* 0x014C-0x016C */ |
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0:01f31e923fe2 | 96 | __IO uint32_t bl_ctrl; /* 0x0170 Bootloader Control Register */ |
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0:01f31e923fe2 | 97 | __IO uint32_t twk; /* 0x0174 PDM33 Register */ |
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0:01f31e923fe2 | 98 | __R uint32_t rsv178; /* 0x0178 */ |
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0:01f31e923fe2 | 99 | __IO uint32_t slm; /* 0x017C Sleep Mode Register */ |
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0:01f31e923fe2 | 100 | __R uint32_t rsv180[32]; /* 0x0180-0x01FC */ |
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0:01f31e923fe2 | 101 | __IO uint32_t disable_xr0; /* 0x0200 Disable Flash Page Exec/Read Register 0 */ |
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0:01f31e923fe2 | 102 | __IO uint32_t disable_xr1; /* 0x0204 Disable Flash Page Exec/Read Register 1 */ |
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0:01f31e923fe2 | 103 | __IO uint32_t disable_xr2; /* 0x0208 Disable Flash Page Exec/Read Register 2 */ |
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0:01f31e923fe2 | 104 | __IO uint32_t disable_xr3; /* 0x020C Disable Flash Page Exec/Read Register 3 */ |
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0:01f31e923fe2 | 105 | __IO uint32_t disable_xr4; /* 0x0210 Disable Flash Page Exec/Read Register 4 */ |
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0:01f31e923fe2 | 106 | __IO uint32_t disable_xr5; /* 0x0214 Disable Flash Page Exec/Read Register 5 */ |
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0:01f31e923fe2 | 107 | __IO uint32_t disable_xr6; /* 0x0218 Disable Flash Page Exec/Read Register 6 */ |
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0:01f31e923fe2 | 108 | __IO uint32_t disable_xr7; /* 0x021C Disable Flash Page Exec/Read Register 7 */ |
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0:01f31e923fe2 | 109 | __R uint32_t rsv220[56]; /* 0x0220-0x02FC */ |
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0:01f31e923fe2 | 110 | __IO uint32_t disable_we0; /* 0x0300 Disable Flash Page Write/Erase Register 0 */ |
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0:01f31e923fe2 | 111 | __IO uint32_t disable_we1; /* 0x0304 Disable Flash Page Write/Erase Register 1 */ |
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0:01f31e923fe2 | 112 | __IO uint32_t disable_we2; /* 0x0308 Disable Flash Page Write/Erase Register 2 */ |
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0:01f31e923fe2 | 113 | __IO uint32_t disable_we3; /* 0x030C Disable Flash Page Write/Erase Register 3 */ |
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0:01f31e923fe2 | 114 | __IO uint32_t disable_we4; /* 0x0310 Disable Flash Page Write/Erase Register 4 */ |
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0:01f31e923fe2 | 115 | __IO uint32_t disable_we5; /* 0x0314 Disable Flash Page Write/Erase Register 5 */ |
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0:01f31e923fe2 | 116 | __IO uint32_t disable_we6; /* 0x0318 Disable Flash Page Write/Erase Register 6 */ |
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0:01f31e923fe2 | 117 | __IO uint32_t disable_we7; /* 0x031C Disable Flash Page Write/Erase Register 7 */ |
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0:01f31e923fe2 | 118 | } mxc_flc_regs_t; |
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0:01f31e923fe2 | 119 | |
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0:01f31e923fe2 | 120 | |
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0:01f31e923fe2 | 121 | /* |
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0:01f31e923fe2 | 122 | Register offsets for module FLC. |
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0:01f31e923fe2 | 123 | */ |
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0:01f31e923fe2 | 124 | |
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0:01f31e923fe2 | 125 | #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) |
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0:01f31e923fe2 | 126 | #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) |
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0:01f31e923fe2 | 127 | #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) |
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0:01f31e923fe2 | 128 | #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) |
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0:01f31e923fe2 | 129 | #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) |
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0:01f31e923fe2 | 130 | #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) |
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0:01f31e923fe2 | 131 | #define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) |
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0:01f31e923fe2 | 132 | #define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) |
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0:01f31e923fe2 | 133 | #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) |
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0:01f31e923fe2 | 134 | #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) |
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0:01f31e923fe2 | 135 | #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) |
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0:01f31e923fe2 | 136 | #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) |
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0:01f31e923fe2 | 137 | #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) |
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0:01f31e923fe2 | 138 | #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) |
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0:01f31e923fe2 | 139 | #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) |
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0:01f31e923fe2 | 140 | #define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) |
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0:01f31e923fe2 | 141 | #define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) |
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0:01f31e923fe2 | 142 | #define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) |
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0:01f31e923fe2 | 143 | #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) |
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0:01f31e923fe2 | 144 | #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) |
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0:01f31e923fe2 | 145 | #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) |
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0:01f31e923fe2 | 146 | #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) |
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0:01f31e923fe2 | 147 | #define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) |
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0:01f31e923fe2 | 148 | #define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) |
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0:01f31e923fe2 | 149 | #define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) |
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0:01f31e923fe2 | 150 | #define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) |
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0:01f31e923fe2 | 151 | #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) |
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0:01f31e923fe2 | 152 | #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) |
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0:01f31e923fe2 | 153 | #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) |
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0:01f31e923fe2 | 154 | #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) |
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0:01f31e923fe2 | 155 | #define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) |
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0:01f31e923fe2 | 156 | #define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) |
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0:01f31e923fe2 | 157 | #define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) |
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0:01f31e923fe2 | 158 | #define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) |
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0:01f31e923fe2 | 159 | |
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0:01f31e923fe2 | 160 | |
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0:01f31e923fe2 | 161 | /* |
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0:01f31e923fe2 | 162 | Field positions and masks for module FLC. |
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0:01f31e923fe2 | 163 | */ |
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0:01f31e923fe2 | 164 | |
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0:01f31e923fe2 | 165 | #define MXC_F_FLC_FADDR_FADDR_POS 0 |
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0:01f31e923fe2 | 166 | #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) |
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0:01f31e923fe2 | 167 | |
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0:01f31e923fe2 | 168 | #define MXC_F_FLC_FCKDIV_FCKDIV_POS 0 |
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0:01f31e923fe2 | 169 | #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) |
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0:01f31e923fe2 | 170 | #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 |
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0:01f31e923fe2 | 171 | #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) |
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0:01f31e923fe2 | 172 | |
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0:01f31e923fe2 | 173 | #define MXC_F_FLC_CTRL_WRITE_POS 0 |
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0:01f31e923fe2 | 174 | #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) |
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0:01f31e923fe2 | 175 | #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 |
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0:01f31e923fe2 | 176 | #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) |
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0:01f31e923fe2 | 177 | #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 |
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0:01f31e923fe2 | 178 | #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) |
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0:01f31e923fe2 | 179 | #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 |
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0:01f31e923fe2 | 180 | #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) |
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0:01f31e923fe2 | 181 | #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 |
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0:01f31e923fe2 | 182 | #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) |
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0:01f31e923fe2 | 183 | #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 |
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0:01f31e923fe2 | 184 | #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) |
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0:01f31e923fe2 | 185 | #define MXC_F_FLC_CTRL_PENDING_POS 24 |
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0:01f31e923fe2 | 186 | #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) |
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0:01f31e923fe2 | 187 | #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 |
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0:01f31e923fe2 | 188 | #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) |
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0:01f31e923fe2 | 189 | #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 |
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0:01f31e923fe2 | 190 | #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) |
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0:01f31e923fe2 | 191 | #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 |
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0:01f31e923fe2 | 192 | #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) |
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0:01f31e923fe2 | 193 | |
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0:01f31e923fe2 | 194 | #define MXC_F_FLC_INTR_FINISHED_IF_POS 0 |
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0:01f31e923fe2 | 195 | #define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) |
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0:01f31e923fe2 | 196 | #define MXC_F_FLC_INTR_FAILED_IF_POS 1 |
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0:01f31e923fe2 | 197 | #define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) |
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0:01f31e923fe2 | 198 | #define MXC_F_FLC_INTR_FINISHED_IE_POS 8 |
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0:01f31e923fe2 | 199 | #define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) |
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0:01f31e923fe2 | 200 | #define MXC_F_FLC_INTR_FAILED_IE_POS 9 |
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0:01f31e923fe2 | 201 | #define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) |
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0:01f31e923fe2 | 202 | #define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 |
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0:01f31e923fe2 | 203 | #define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) |
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0:01f31e923fe2 | 204 | |
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0:01f31e923fe2 | 205 | #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 |
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0:01f31e923fe2 | 206 | #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) |
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0:01f31e923fe2 | 207 | #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 |
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0:01f31e923fe2 | 208 | #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) |
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0:01f31e923fe2 | 209 | #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 |
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0:01f31e923fe2 | 210 | #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) |
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0:01f31e923fe2 | 211 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 |
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0:01f31e923fe2 | 212 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) |
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0:01f31e923fe2 | 213 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 |
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0:01f31e923fe2 | 214 | #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) |
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0:01f31e923fe2 | 215 | #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 |
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0:01f31e923fe2 | 216 | #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) |
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0:01f31e923fe2 | 217 | #define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 |
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0:01f31e923fe2 | 218 | #define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) |
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0:01f31e923fe2 | 219 | #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 |
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0:01f31e923fe2 | 220 | #define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) |
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0:01f31e923fe2 | 221 | |
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0:01f31e923fe2 | 222 | #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 |
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0:01f31e923fe2 | 223 | #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) |
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0:01f31e923fe2 | 224 | #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 |
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0:01f31e923fe2 | 225 | #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) |
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0:01f31e923fe2 | 226 | #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 |
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0:01f31e923fe2 | 227 | #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) |
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0:01f31e923fe2 | 228 | #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 |
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0:01f31e923fe2 | 229 | #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) |
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0:01f31e923fe2 | 230 | #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 |
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0:01f31e923fe2 | 231 | #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) |
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0:01f31e923fe2 | 232 | |
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0:01f31e923fe2 | 233 | #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 |
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0:01f31e923fe2 | 234 | #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) |
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0:01f31e923fe2 | 235 | #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 |
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0:01f31e923fe2 | 236 | #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) |
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0:01f31e923fe2 | 237 | #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 |
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0:01f31e923fe2 | 238 | #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) |
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0:01f31e923fe2 | 239 | #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 |
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0:01f31e923fe2 | 240 | #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) |
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0:01f31e923fe2 | 241 | #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 |
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0:01f31e923fe2 | 242 | #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) |
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0:01f31e923fe2 | 243 | |
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0:01f31e923fe2 | 244 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 |
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0:01f31e923fe2 | 245 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) |
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0:01f31e923fe2 | 246 | #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 |
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0:01f31e923fe2 | 247 | #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) |
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0:01f31e923fe2 | 248 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 |
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0:01f31e923fe2 | 249 | #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) |
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0:01f31e923fe2 | 250 | #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 |
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0:01f31e923fe2 | 251 | #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) |
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0:01f31e923fe2 | 252 | |
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0:01f31e923fe2 | 253 | #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 |
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0:01f31e923fe2 | 254 | #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) |
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0:01f31e923fe2 | 255 | #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 |
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0:01f31e923fe2 | 256 | #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) |
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0:01f31e923fe2 | 257 | #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 |
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0:01f31e923fe2 | 258 | #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) |
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0:01f31e923fe2 | 259 | #define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 |
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0:01f31e923fe2 | 260 | #define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) |
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0:01f31e923fe2 | 261 | #define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 |
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0:01f31e923fe2 | 262 | #define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) |
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0:01f31e923fe2 | 263 | #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 |
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0:01f31e923fe2 | 264 | #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) |
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0:01f31e923fe2 | 265 | #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 |
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0:01f31e923fe2 | 266 | #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) |
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0:01f31e923fe2 | 267 | |
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0:01f31e923fe2 | 268 | #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 |
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0:01f31e923fe2 | 269 | #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) |
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0:01f31e923fe2 | 270 | #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 |
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0:01f31e923fe2 | 271 | #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) |
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0:01f31e923fe2 | 272 | #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 |
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0:01f31e923fe2 | 273 | #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) |
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0:01f31e923fe2 | 274 | #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 |
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0:01f31e923fe2 | 275 | #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) |
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0:01f31e923fe2 | 276 | #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 |
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0:01f31e923fe2 | 277 | #define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) |
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0:01f31e923fe2 | 278 | #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 |
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0:01f31e923fe2 | 279 | #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) |
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0:01f31e923fe2 | 280 | |
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0:01f31e923fe2 | 281 | #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 |
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0:01f31e923fe2 | 282 | #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) |
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0:01f31e923fe2 | 283 | #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 |
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0:01f31e923fe2 | 284 | #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) |
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0:01f31e923fe2 | 285 | #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 |
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0:01f31e923fe2 | 286 | #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) |
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0:01f31e923fe2 | 287 | #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 |
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0:01f31e923fe2 | 288 | #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) |
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0:01f31e923fe2 | 289 | #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 |
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0:01f31e923fe2 | 290 | #define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) |
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0:01f31e923fe2 | 291 | #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 |
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0:01f31e923fe2 | 292 | #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) |
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0:01f31e923fe2 | 293 | |
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0:01f31e923fe2 | 294 | |
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0:01f31e923fe2 | 295 | |
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0:01f31e923fe2 | 296 | #ifdef __cplusplus |
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0:01f31e923fe2 | 297 | } |
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0:01f31e923fe2 | 298 | #endif |
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0:01f31e923fe2 | 299 | |
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0:01f31e923fe2 | 300 | #endif /* _MXC_FLC_REGS_H_ */ |