Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32620/DAP_config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 #ifndef __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 2 #define __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 3
Pawel Zarembski 0:01f31e923fe2 4 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 5 /**
Pawel Zarembski 0:01f31e923fe2 6 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
Pawel Zarembski 0:01f31e923fe2 7 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 8 @{
Pawel Zarembski 0:01f31e923fe2 9 Provides definitions about:
Pawel Zarembski 0:01f31e923fe2 10 - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 11 - Debug Unit communication packet size.
Pawel Zarembski 0:01f31e923fe2 12 - Debug Access Port communication mode (JTAG or SWD).
Pawel Zarembski 0:01f31e923fe2 13 - Optional information about a connected Target Device (for Evaluation Boards).
Pawel Zarembski 0:01f31e923fe2 14 */
Pawel Zarembski 0:01f31e923fe2 15
Pawel Zarembski 0:01f31e923fe2 16 #include <stdio.h>
Pawel Zarembski 0:01f31e923fe2 17 #include "max32620.h" // Debug Unit Cortex-M Processor Header File
Pawel Zarembski 0:01f31e923fe2 18 #include "clkman_regs.h"
Pawel Zarembski 0:01f31e923fe2 19 #include "gpio_regs.h"
Pawel Zarembski 0:01f31e923fe2 20 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
Pawel Zarembski 0:01f31e923fe2 23 /// This value is used to calculate the SWD/JTAG clock speed.
Pawel Zarembski 0:01f31e923fe2 24 #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
Pawel Zarembski 0:01f31e923fe2 25
Pawel Zarembski 0:01f31e923fe2 26 /// Number of processor cycles for I/O Port write operations.
Pawel Zarembski 0:01f31e923fe2 27 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
Pawel Zarembski 0:01f31e923fe2 28 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
Pawel Zarembski 0:01f31e923fe2 29 /// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
Pawel Zarembski 0:01f31e923fe2 30 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
Pawel Zarembski 0:01f31e923fe2 31 /// required.
Pawel Zarembski 0:01f31e923fe2 32 #define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 35 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 36 #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 /// Indicate that JTAG communication mode is available at the Debug Port.
Pawel Zarembski 0:01f31e923fe2 39 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 40 #define DAP_JTAG 0 ///< JTAG Mode: 1 = available
Pawel Zarembski 0:01f31e923fe2 41
Pawel Zarembski 0:01f31e923fe2 42 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 43 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
Pawel Zarembski 0:01f31e923fe2 44 #define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
Pawel Zarembski 0:01f31e923fe2 45
Pawel Zarembski 0:01f31e923fe2 46 /// Default communication mode on the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 47 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
Pawel Zarembski 0:01f31e923fe2 48 #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
Pawel Zarembski 0:01f31e923fe2 49
Pawel Zarembski 0:01f31e923fe2 50 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
Pawel Zarembski 0:01f31e923fe2 51 /// Used to initialize the default SWD/JTAG clock frequency.
Pawel Zarembski 0:01f31e923fe2 52 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
Pawel Zarembski 0:01f31e923fe2 53 #define DAP_DEFAULT_SWJ_CLOCK 3000000 ///< Default SWD/JTAG clock frequency in Hz.
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 /// Maximum Package Size for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 56 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 57 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 58 #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 59
Pawel Zarembski 0:01f31e923fe2 60 /// Maximum Package Buffers for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 61 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 62 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
Pawel Zarembski 0:01f31e923fe2 63 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 64 #define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 65
Pawel Zarembski 0:01f31e923fe2 66 /// Indicate that UART Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 67 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 68 #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 /// Maximum SWO UART Baudrate
Pawel Zarembski 0:01f31e923fe2 71 #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 74 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 75 #define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 /// SWO Trace Buffer Size.
Pawel Zarembski 0:01f31e923fe2 78 #define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
Pawel Zarembski 0:01f31e923fe2 79
Pawel Zarembski 0:01f31e923fe2 80 /// SWO Streaming Trace.
Pawel Zarembski 0:01f31e923fe2 81 #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 82
Pawel Zarembski 0:01f31e923fe2 83 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
Pawel Zarembski 0:01f31e923fe2 84 #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
Pawel Zarembski 0:01f31e923fe2 85
Pawel Zarembski 0:01f31e923fe2 86 /// Debug Unit is connected to fixed Target Device.
Pawel Zarembski 0:01f31e923fe2 87 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
Pawel Zarembski 0:01f31e923fe2 88 /// known device. In this case a Device Vendor and Device Name string is stored which
Pawel Zarembski 0:01f31e923fe2 89 /// may be used by the debugger or IDE to configure device parameters.
Pawel Zarembski 0:01f31e923fe2 90 #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
Pawel Zarembski 0:01f31e923fe2 91
Pawel Zarembski 0:01f31e923fe2 92 #if TARGET_DEVICE_FIXED
Pawel Zarembski 0:01f31e923fe2 93 #define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
Pawel Zarembski 0:01f31e923fe2 94 #define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
Pawel Zarembski 0:01f31e923fe2 95 #endif
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 ///@}
Pawel Zarembski 0:01f31e923fe2 98
Pawel Zarembski 0:01f31e923fe2 99 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 100 /**
Pawel Zarembski 0:01f31e923fe2 101 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
Pawel Zarembski 0:01f31e923fe2 102 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 103 @{
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
Pawel Zarembski 0:01f31e923fe2 106 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
Pawel Zarembski 0:01f31e923fe2 107 interface of a device. The following I/O Pins are provided:
Pawel Zarembski 0:01f31e923fe2 108
Pawel Zarembski 0:01f31e923fe2 109 JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
Pawel Zarembski 0:01f31e923fe2 110 ---------------------------- | -------------------- | ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 111 TCK: Test Clock | SWCLK: Clock | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 112 TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
Pawel Zarembski 0:01f31e923fe2 113 TDI: Test Data Input | | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 114 TDO: Test Data Output | | Input
Pawel Zarembski 0:01f31e923fe2 115 nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 116 nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118
Pawel Zarembski 0:01f31e923fe2 119 DAP Hardware I/O Pin Access Functions
Pawel Zarembski 0:01f31e923fe2 120 -------------------------------------
Pawel Zarembski 0:01f31e923fe2 121 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
Pawel Zarembski 0:01f31e923fe2 122 these I/O Pins.
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
Pawel Zarembski 0:01f31e923fe2 125 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
Pawel Zarembski 0:01f31e923fe2 126 peripherals that can independently write/read a single I/O pin without affecting any other pins
Pawel Zarembski 0:01f31e923fe2 127 of the same I/O port. The following SWDIO I/O Pin functions are provided:
Pawel Zarembski 0:01f31e923fe2 128 - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 129 - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 130 - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 131 - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 132 */
Pawel Zarembski 0:01f31e923fe2 133
Pawel Zarembski 0:01f31e923fe2 134
Pawel Zarembski 0:01f31e923fe2 135 // Configure DAP I/O pins ------------------------------
Pawel Zarembski 0:01f31e923fe2 136
Pawel Zarembski 0:01f31e923fe2 137 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Pawel Zarembski 0:01f31e923fe2 138 Configures the DAP Hardware I/O pins for JTAG mode:
Pawel Zarembski 0:01f31e923fe2 139 - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
Pawel Zarembski 0:01f31e923fe2 140 - TDO to input mode.
Pawel Zarembski 0:01f31e923fe2 141 */
Pawel Zarembski 0:01f31e923fe2 142 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
Pawel Zarembski 0:01f31e923fe2 143
Pawel Zarembski 0:01f31e923fe2 144 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 145
Pawel Zarembski 0:01f31e923fe2 146 /* Ensure that the GPIO clock is enabled */
Pawel Zarembski 0:01f31e923fe2 147 if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
Pawel Zarembski 0:01f31e923fe2 148 MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
Pawel Zarembski 0:01f31e923fe2 149 }
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 // Setup the JTAG/SWD pins
Pawel Zarembski 0:01f31e923fe2 152 MXC_GPIO->out_val[TRGT_PORT] = 0xFF; // set all pins high
Pawel Zarembski 0:01f31e923fe2 153
Pawel Zarembski 0:01f31e923fe2 154 out_mode = MXC_GPIO->out_mode[TRGT_PORT];
Pawel Zarembski 0:01f31e923fe2 155 out_mode &= ~(0xF << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 156 out_mode &= ~(0xF << (4 * RSTN_PIN));
Pawel Zarembski 0:01f31e923fe2 157 out_mode &= ~(0xF << (4 * TDI_PIN));
Pawel Zarembski 0:01f31e923fe2 158 out_mode &= ~(0xF << (4 * TCK_PIN));
Pawel Zarembski 0:01f31e923fe2 159 out_mode &= ~(0xF << (4 * TMS_PIN));
Pawel Zarembski 0:01f31e923fe2 160 out_mode &= ~(0xF << (4 * TDO_PIN));
Pawel Zarembski 0:01f31e923fe2 161
Pawel Zarembski 0:01f31e923fe2 162 out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * RSTN_PIN));
Pawel Zarembski 0:01f31e923fe2 163 out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 164 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TCK_PIN));
Pawel Zarembski 0:01f31e923fe2 165 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TMS_PIN));
Pawel Zarembski 0:01f31e923fe2 166 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TDI_PIN));
Pawel Zarembski 0:01f31e923fe2 167 MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 // Setup the BUFFEN pin
Pawel Zarembski 0:01f31e923fe2 170 MXC_GPIO->out_val[BUFFEN_PORT] = 0xFF; // set all pins high
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 out_mode = MXC_GPIO->out_mode[BUFFEN_PORT];
Pawel Zarembski 0:01f31e923fe2 173 out_mode &= ~(0xF << (4 * BUFFEN_PIN));
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * BUFFEN_PIN));
Pawel Zarembski 0:01f31e923fe2 176 MXC_GPIO->out_mode[BUFFEN_PIN] = out_mode;
Pawel Zarembski 0:01f31e923fe2 177
Pawel Zarembski 0:01f31e923fe2 178 }
Pawel Zarembski 0:01f31e923fe2 179
Pawel Zarembski 0:01f31e923fe2 180 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Pawel Zarembski 0:01f31e923fe2 181 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
Pawel Zarembski 0:01f31e923fe2 182 - SWCLK, SWDIO, nRESET to output mode and set to default high level.
Pawel Zarembski 0:01f31e923fe2 183 - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
Pawel Zarembski 0:01f31e923fe2 184 */
Pawel Zarembski 0:01f31e923fe2 185 __STATIC_INLINE void PORT_SWD_SETUP (void) {
Pawel Zarembski 0:01f31e923fe2 186
Pawel Zarembski 0:01f31e923fe2 187 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 188
Pawel Zarembski 0:01f31e923fe2 189 /* Ensure that the GPIO clock is enabled */
Pawel Zarembski 0:01f31e923fe2 190 if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
Pawel Zarembski 0:01f31e923fe2 191 MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
Pawel Zarembski 0:01f31e923fe2 192 }
Pawel Zarembski 0:01f31e923fe2 193
Pawel Zarembski 0:01f31e923fe2 194 // Setup the JTAG/SWD pins
Pawel Zarembski 0:01f31e923fe2 195 MXC_GPIO->out_val[TRGT_PORT] = 0xFF; // set all pins high
Pawel Zarembski 0:01f31e923fe2 196
Pawel Zarembski 0:01f31e923fe2 197 out_mode = MXC_GPIO->out_mode[TRGT_PORT];
Pawel Zarembski 0:01f31e923fe2 198 out_mode &= ~(0xF << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 199 out_mode &= ~(0xF << (4 * SWCLK_PIN));
Pawel Zarembski 0:01f31e923fe2 200 out_mode &= ~(0xF << (4 * SWDIO_PIN));
Pawel Zarembski 0:01f31e923fe2 201
Pawel Zarembski 0:01f31e923fe2 202 out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 203 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWCLK_PIN));
Pawel Zarembski 0:01f31e923fe2 204 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWDIO_PIN));
Pawel Zarembski 0:01f31e923fe2 205 MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207 // Setup the BUFFEN pin
Pawel Zarembski 0:01f31e923fe2 208 MXC_GPIO->out_val[BUFFEN_PORT] = 0xFF; // set all pins high
Pawel Zarembski 0:01f31e923fe2 209
Pawel Zarembski 0:01f31e923fe2 210 out_mode = MXC_GPIO->out_mode[BUFFEN_PORT];
Pawel Zarembski 0:01f31e923fe2 211 out_mode &= ~(0xF << (4 * BUFFEN_PIN));
Pawel Zarembski 0:01f31e923fe2 212
Pawel Zarembski 0:01f31e923fe2 213 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * BUFFEN_PIN));
Pawel Zarembski 0:01f31e923fe2 214 MXC_GPIO->out_mode[BUFFEN_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 215 }
Pawel Zarembski 0:01f31e923fe2 216
Pawel Zarembski 0:01f31e923fe2 217 /** Disable JTAG/SWD I/O Pins.
Pawel Zarembski 0:01f31e923fe2 218 Disables the DAP Hardware I/O pins which configures:
Pawel Zarembski 0:01f31e923fe2 219 - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
Pawel Zarembski 0:01f31e923fe2 220 */
Pawel Zarembski 0:01f31e923fe2 221 __STATIC_INLINE void PORT_OFF (void) {
Pawel Zarembski 0:01f31e923fe2 222
Pawel Zarembski 0:01f31e923fe2 223 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 224 out_mode = MXC_GPIO->out_mode[TRGT_PORT];
Pawel Zarembski 0:01f31e923fe2 225 out_mode &= ~(0xF << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 226 out_mode &= ~(0xF << (4 * RSTN_PIN));
Pawel Zarembski 0:01f31e923fe2 227 out_mode &= ~(0xF << (4 * TDI_PIN));
Pawel Zarembski 0:01f31e923fe2 228 out_mode &= ~(0xF << (4 * TCK_PIN));
Pawel Zarembski 0:01f31e923fe2 229 out_mode &= ~(0xF << (4 * TMS_PIN));
Pawel Zarembski 0:01f31e923fe2 230 out_mode &= ~(0xF << (4 * TDO_PIN));
Pawel Zarembski 0:01f31e923fe2 231
Pawel Zarembski 0:01f31e923fe2 232 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 233 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * RSTN_PIN));
Pawel Zarembski 0:01f31e923fe2 234 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDI_PIN));
Pawel Zarembski 0:01f31e923fe2 235 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TCK_PIN));
Pawel Zarembski 0:01f31e923fe2 236 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TMS_PIN));
Pawel Zarembski 0:01f31e923fe2 237 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDO_PIN));
Pawel Zarembski 0:01f31e923fe2 238
Pawel Zarembski 0:01f31e923fe2 239 MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 240 }
Pawel Zarembski 0:01f31e923fe2 241
Pawel Zarembski 0:01f31e923fe2 242
Pawel Zarembski 0:01f31e923fe2 243 // SWCLK/TCK I/O pin -------------------------------------
Pawel Zarembski 0:01f31e923fe2 244
Pawel Zarembski 0:01f31e923fe2 245 /** SWCLK/TCK I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 246 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 247 */
Pawel Zarembski 0:01f31e923fe2 248 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
Pawel Zarembski 0:01f31e923fe2 249 return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TCK_PIN);
Pawel Zarembski 0:01f31e923fe2 250 }
Pawel Zarembski 0:01f31e923fe2 251
Pawel Zarembski 0:01f31e923fe2 252 /** SWCLK/TCK I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 253 Set the SWCLK/TCK DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 254 */
Pawel Zarembski 0:01f31e923fe2 255 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
Pawel Zarembski 0:01f31e923fe2 256 MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TCK_PIN);
Pawel Zarembski 0:01f31e923fe2 257 }
Pawel Zarembski 0:01f31e923fe2 258
Pawel Zarembski 0:01f31e923fe2 259 /** SWCLK/TCK I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 260 Set the SWCLK/TCK DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 261 */
Pawel Zarembski 0:01f31e923fe2 262 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
Pawel Zarembski 0:01f31e923fe2 263 MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TCK_PIN);
Pawel Zarembski 0:01f31e923fe2 264 }
Pawel Zarembski 0:01f31e923fe2 265
Pawel Zarembski 0:01f31e923fe2 266
Pawel Zarembski 0:01f31e923fe2 267 // SWDIO/TMS Pin I/O --------------------------------------
Pawel Zarembski 0:01f31e923fe2 268
Pawel Zarembski 0:01f31e923fe2 269 /** SWDIO/TMS I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 270 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 271 */
Pawel Zarembski 0:01f31e923fe2 272 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
Pawel Zarembski 0:01f31e923fe2 273 return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TMS_PIN);
Pawel Zarembski 0:01f31e923fe2 274 }
Pawel Zarembski 0:01f31e923fe2 275
Pawel Zarembski 0:01f31e923fe2 276 /** SWDIO/TMS I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 277 Set the SWDIO/TMS DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 278 */
Pawel Zarembski 0:01f31e923fe2 279 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
Pawel Zarembski 0:01f31e923fe2 280 MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TMS_PIN);
Pawel Zarembski 0:01f31e923fe2 281 }
Pawel Zarembski 0:01f31e923fe2 282
Pawel Zarembski 0:01f31e923fe2 283 /** SWDIO/TMS I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 284 Set the SWDIO/TMS DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 285 */
Pawel Zarembski 0:01f31e923fe2 286 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
Pawel Zarembski 0:01f31e923fe2 287 MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TMS_PIN);
Pawel Zarembski 0:01f31e923fe2 288 }
Pawel Zarembski 0:01f31e923fe2 289
Pawel Zarembski 0:01f31e923fe2 290 /** SWDIO I/O pin: Get Input (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 291 \return Current status of the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 292 */
Pawel Zarembski 0:01f31e923fe2 293 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
Pawel Zarembski 0:01f31e923fe2 294 return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], SWDIO_PIN);
Pawel Zarembski 0:01f31e923fe2 295 }
Pawel Zarembski 0:01f31e923fe2 296
Pawel Zarembski 0:01f31e923fe2 297 /** SWDIO I/O pin: Set Output (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 298 \param bit Output value for the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 299 */
Pawel Zarembski 0:01f31e923fe2 300 __STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit){
Pawel Zarembski 0:01f31e923fe2 301 if (bit & 1) {
Pawel Zarembski 0:01f31e923fe2 302 MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], SWDIO_PIN);
Pawel Zarembski 0:01f31e923fe2 303 } else {
Pawel Zarembski 0:01f31e923fe2 304 MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], SWDIO_PIN);
Pawel Zarembski 0:01f31e923fe2 305 }
Pawel Zarembski 0:01f31e923fe2 306 }
Pawel Zarembski 0:01f31e923fe2 307
Pawel Zarembski 0:01f31e923fe2 308 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 309 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
Pawel Zarembski 0:01f31e923fe2 310 called prior \ref PIN_SWDIO_OUT function calls.
Pawel Zarembski 0:01f31e923fe2 311 */
Pawel Zarembski 0:01f31e923fe2 312 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
Pawel Zarembski 0:01f31e923fe2 313 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 314
Pawel Zarembski 0:01f31e923fe2 315 out_mode = MXC_GPIO->out_mode[TRGT_PORT];
Pawel Zarembski 0:01f31e923fe2 316 out_mode &= ~(0xF << (4 * SWDIO_PIN));
Pawel Zarembski 0:01f31e923fe2 317 out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWDIO_PIN));
Pawel Zarembski 0:01f31e923fe2 318
Pawel Zarembski 0:01f31e923fe2 319 MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 320 }
Pawel Zarembski 0:01f31e923fe2 321
Pawel Zarembski 0:01f31e923fe2 322 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 323 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
Pawel Zarembski 0:01f31e923fe2 324 called prior \ref PIN_SWDIO_IN function calls.
Pawel Zarembski 0:01f31e923fe2 325 */
Pawel Zarembski 0:01f31e923fe2 326 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
Pawel Zarembski 0:01f31e923fe2 327 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 328
Pawel Zarembski 0:01f31e923fe2 329 out_mode = MXC_GPIO->out_mode[TRGT_PORT];
Pawel Zarembski 0:01f31e923fe2 330 out_mode &= ~(0xF << (4 * SWDIO_PIN));
Pawel Zarembski 0:01f31e923fe2 331
Pawel Zarembski 0:01f31e923fe2 332 MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 333 }
Pawel Zarembski 0:01f31e923fe2 334
Pawel Zarembski 0:01f31e923fe2 335
Pawel Zarembski 0:01f31e923fe2 336 // TDI Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 337
Pawel Zarembski 0:01f31e923fe2 338 /** TDI I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 339 \return Current status of the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 340 */
Pawel Zarembski 0:01f31e923fe2 341 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
Pawel Zarembski 0:01f31e923fe2 342 return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TDI_PIN);
Pawel Zarembski 0:01f31e923fe2 343 }
Pawel Zarembski 0:01f31e923fe2 344
Pawel Zarembski 0:01f31e923fe2 345 /** TDI I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 346 \param bit Output value for the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 347 */
Pawel Zarembski 0:01f31e923fe2 348 __STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
Pawel Zarembski 0:01f31e923fe2 349 if (bit & 1) {
Pawel Zarembski 0:01f31e923fe2 350 MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TDI_PIN);
Pawel Zarembski 0:01f31e923fe2 351 } else {
Pawel Zarembski 0:01f31e923fe2 352 MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TDI_PIN);
Pawel Zarembski 0:01f31e923fe2 353 }
Pawel Zarembski 0:01f31e923fe2 354 }
Pawel Zarembski 0:01f31e923fe2 355
Pawel Zarembski 0:01f31e923fe2 356
Pawel Zarembski 0:01f31e923fe2 357 // TDO Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 358
Pawel Zarembski 0:01f31e923fe2 359 /** TDO I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 360 \return Current status of the TDO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 361 */
Pawel Zarembski 0:01f31e923fe2 362 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
Pawel Zarembski 0:01f31e923fe2 363 return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TDO_PIN);
Pawel Zarembski 0:01f31e923fe2 364 }
Pawel Zarembski 0:01f31e923fe2 365
Pawel Zarembski 0:01f31e923fe2 366
Pawel Zarembski 0:01f31e923fe2 367 // nTRST Pin I/O -------------------------------------------
Pawel Zarembski 0:01f31e923fe2 368
Pawel Zarembski 0:01f31e923fe2 369 /** nTRST I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 370 \return Current status of the nTRST DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 371 */
Pawel Zarembski 0:01f31e923fe2 372 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
Pawel Zarembski 0:01f31e923fe2 373 return 0;
Pawel Zarembski 0:01f31e923fe2 374 }
Pawel Zarembski 0:01f31e923fe2 375
Pawel Zarembski 0:01f31e923fe2 376 /** nTRST I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 377 \param bit JTAG TRST Test Reset pin status:
Pawel Zarembski 0:01f31e923fe2 378 - 0: issue a JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 379 - 1: release JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 380 */
Pawel Zarembski 0:01f31e923fe2 381 __STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
Pawel Zarembski 0:01f31e923fe2 382 }
Pawel Zarembski 0:01f31e923fe2 383
Pawel Zarembski 0:01f31e923fe2 384 // nRESET Pin I/O------------------------------------------
Pawel Zarembski 0:01f31e923fe2 385
Pawel Zarembski 0:01f31e923fe2 386 /** nRESET I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 387 \return Current status of the nRESET DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 388 */
Pawel Zarembski 0:01f31e923fe2 389 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
Pawel Zarembski 0:01f31e923fe2 390 return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], SRST_PIN);
Pawel Zarembski 0:01f31e923fe2 391 }
Pawel Zarembski 0:01f31e923fe2 392
Pawel Zarembski 0:01f31e923fe2 393 /** nRESET I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 394 \param bit target device hardware reset pin status:
Pawel Zarembski 0:01f31e923fe2 395 - 0: issue a device hardware reset.
Pawel Zarembski 0:01f31e923fe2 396 - 1: release device hardware reset.
Pawel Zarembski 0:01f31e923fe2 397 */
Pawel Zarembski 0:01f31e923fe2 398 __STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
Pawel Zarembski 0:01f31e923fe2 399 if (bit) {
Pawel Zarembski 0:01f31e923fe2 400 MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], SRST_PIN);
Pawel Zarembski 0:01f31e923fe2 401 } else {
Pawel Zarembski 0:01f31e923fe2 402 MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], SRST_PIN);
Pawel Zarembski 0:01f31e923fe2 403 }
Pawel Zarembski 0:01f31e923fe2 404 }
Pawel Zarembski 0:01f31e923fe2 405
Pawel Zarembski 0:01f31e923fe2 406 ///@}
Pawel Zarembski 0:01f31e923fe2 407
Pawel Zarembski 0:01f31e923fe2 408
Pawel Zarembski 0:01f31e923fe2 409 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 410 /**
Pawel Zarembski 0:01f31e923fe2 411 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
Pawel Zarembski 0:01f31e923fe2 412 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 413 @{
Pawel Zarembski 0:01f31e923fe2 414
Pawel Zarembski 0:01f31e923fe2 415 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 416
Pawel Zarembski 0:01f31e923fe2 417 It is recommended to provide the following LEDs for status indication:
Pawel Zarembski 0:01f31e923fe2 418 - Connect LED: is active when the DAP hardware is connected to a debugger.
Pawel Zarembski 0:01f31e923fe2 419 - Running LED: is active when the debugger has put the target device into running state.
Pawel Zarembski 0:01f31e923fe2 420 */
Pawel Zarembski 0:01f31e923fe2 421
Pawel Zarembski 0:01f31e923fe2 422 /** Debug Unit: Set status of Connected LED.
Pawel Zarembski 0:01f31e923fe2 423 \param bit status of the Connect LED.
Pawel Zarembski 0:01f31e923fe2 424 - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 425 - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 426 */
Pawel Zarembski 0:01f31e923fe2 427 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
Pawel Zarembski 0:01f31e923fe2 428 }
Pawel Zarembski 0:01f31e923fe2 429
Pawel Zarembski 0:01f31e923fe2 430 /** Debug Unit: Set status Target Running LED.
Pawel Zarembski 0:01f31e923fe2 431 \param bit status of the Target Running LED.
Pawel Zarembski 0:01f31e923fe2 432 - 1: Target Running LED ON: program execution in target started.
Pawel Zarembski 0:01f31e923fe2 433 - 0: Target Running LED OFF: program execution in target stopped.
Pawel Zarembski 0:01f31e923fe2 434 */
Pawel Zarembski 0:01f31e923fe2 435 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
Pawel Zarembski 0:01f31e923fe2 436 }
Pawel Zarembski 0:01f31e923fe2 437
Pawel Zarembski 0:01f31e923fe2 438 ///@}
Pawel Zarembski 0:01f31e923fe2 439
Pawel Zarembski 0:01f31e923fe2 440
Pawel Zarembski 0:01f31e923fe2 441 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 442 /**
Pawel Zarembski 0:01f31e923fe2 443 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
Pawel Zarembski 0:01f31e923fe2 444 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 445 @{
Pawel Zarembski 0:01f31e923fe2 446 Access function for Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 447
Pawel Zarembski 0:01f31e923fe2 448 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
Pawel Zarembski 0:01f31e923fe2 449 default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
Pawel Zarembski 0:01f31e923fe2 450
Pawel Zarembski 0:01f31e923fe2 451 */
Pawel Zarembski 0:01f31e923fe2 452
Pawel Zarembski 0:01f31e923fe2 453 /** Get timestamp of Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 454 \return Current timestamp value.
Pawel Zarembski 0:01f31e923fe2 455 */
Pawel Zarembski 0:01f31e923fe2 456 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
Pawel Zarembski 0:01f31e923fe2 457 return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
Pawel Zarembski 0:01f31e923fe2 458 }
Pawel Zarembski 0:01f31e923fe2 459
Pawel Zarembski 0:01f31e923fe2 460 ///@}
Pawel Zarembski 0:01f31e923fe2 461
Pawel Zarembski 0:01f31e923fe2 462
Pawel Zarembski 0:01f31e923fe2 463 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 464 /**
Pawel Zarembski 0:01f31e923fe2 465 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
Pawel Zarembski 0:01f31e923fe2 466 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 467 @{
Pawel Zarembski 0:01f31e923fe2 468
Pawel Zarembski 0:01f31e923fe2 469 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
Pawel Zarembski 0:01f31e923fe2 470 */
Pawel Zarembski 0:01f31e923fe2 471
Pawel Zarembski 0:01f31e923fe2 472 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
Pawel Zarembski 0:01f31e923fe2 473 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Pawel Zarembski 0:01f31e923fe2 474 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
Pawel Zarembski 0:01f31e923fe2 475 - I/O clock system enabled.
Pawel Zarembski 0:01f31e923fe2 476 - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
Pawel Zarembski 0:01f31e923fe2 477 - for nTRST, nRESET a weak pull-up (if available) is enabled.
Pawel Zarembski 0:01f31e923fe2 478 - LED output pins are enabled and LEDs are turned off.
Pawel Zarembski 0:01f31e923fe2 479 */
Pawel Zarembski 0:01f31e923fe2 480 __STATIC_INLINE void DAP_SETUP (void) {
Pawel Zarembski 0:01f31e923fe2 481 uint32_t out_mode;
Pawel Zarembski 0:01f31e923fe2 482 out_mode = MXC_GPIO->out_mode[TRGT_PORT];
Pawel Zarembski 0:01f31e923fe2 483 out_mode &= ~(0xF << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 484 out_mode &= ~(0xF << (4 * RSTN_PIN));
Pawel Zarembski 0:01f31e923fe2 485 out_mode &= ~(0xF << (4 * TDI_PIN));
Pawel Zarembski 0:01f31e923fe2 486 out_mode &= ~(0xF << (4 * TCK_PIN));
Pawel Zarembski 0:01f31e923fe2 487 out_mode &= ~(0xF << (4 * TMS_PIN));
Pawel Zarembski 0:01f31e923fe2 488 out_mode &= ~(0xF << (4 * TDO_PIN));
Pawel Zarembski 0:01f31e923fe2 489
Pawel Zarembski 0:01f31e923fe2 490 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * SRST_PIN));
Pawel Zarembski 0:01f31e923fe2 491 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * RSTN_PIN));
Pawel Zarembski 0:01f31e923fe2 492 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDI_PIN));
Pawel Zarembski 0:01f31e923fe2 493 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TCK_PIN));
Pawel Zarembski 0:01f31e923fe2 494 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TMS_PIN));
Pawel Zarembski 0:01f31e923fe2 495 out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDO_PIN));
Pawel Zarembski 0:01f31e923fe2 496
Pawel Zarembski 0:01f31e923fe2 497 MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
Pawel Zarembski 0:01f31e923fe2 498 }
Pawel Zarembski 0:01f31e923fe2 499
Pawel Zarembski 0:01f31e923fe2 500 /** Reset Target Device with custom specific I/O pin or command sequence.
Pawel Zarembski 0:01f31e923fe2 501 This function allows the optional implementation of a device specific reset sequence.
Pawel Zarembski 0:01f31e923fe2 502 It is called when the command \ref DAP_ResetTarget and is for example required
Pawel Zarembski 0:01f31e923fe2 503 when a device needs a time-critical unlock sequence that enables the debug port.
Pawel Zarembski 0:01f31e923fe2 504 \return 0 = no device specific reset sequence is implemented.\n
Pawel Zarembski 0:01f31e923fe2 505 1 = a device specific reset sequence is implemented.
Pawel Zarembski 0:01f31e923fe2 506 */
Pawel Zarembski 0:01f31e923fe2 507 __STATIC_INLINE uint32_t RESET_TARGET (void) {
Pawel Zarembski 0:01f31e923fe2 508 return (0); // change to '1' when a device reset sequence is implemented
Pawel Zarembski 0:01f31e923fe2 509 }
Pawel Zarembski 0:01f31e923fe2 510
Pawel Zarembski 0:01f31e923fe2 511 ///@}
Pawel Zarembski 0:01f31e923fe2 512
Pawel Zarembski 0:01f31e923fe2 513
Pawel Zarembski 0:01f31e923fe2 514 #endif /* __DAP_CONFIG_H__ */