DAPLink Reset - Repostiory containing DAPLink source code with Re…

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Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:: Pawel Zarembski
Date:: Tue Apr 07 12:55:42 2020 +0200
Revision:: 0:01f31e923fe2

hani: DAPLink with reset workaround

Who changed what in which revision?

User	Revision	Line number	New contents of line
Pawel Zarembski	0:01f31e923fe2	1	/*
Pawel Zarembski	0:01f31e923fe2	2	** ###################################################################
Pawel Zarembski	0:01f31e923fe2	3	** Processors: MKL26Z128CAL4
Pawel Zarembski	0:01f31e923fe2	4	** MKL26Z128VFM4
Pawel Zarembski	0:01f31e923fe2	5	** MKL26Z128VFT4
Pawel Zarembski	0:01f31e923fe2	6	** MKL26Z128VLH4
Pawel Zarembski	0:01f31e923fe2	7	** MKL26Z128VLL4
Pawel Zarembski	0:01f31e923fe2	8	** MKL26Z128VMC4
Pawel Zarembski	0:01f31e923fe2	9	** MKL26Z256VLH4
Pawel Zarembski	0:01f31e923fe2	10	** MKL26Z256VLL4
Pawel Zarembski	0:01f31e923fe2	11	** MKL26Z256VMC4
Pawel Zarembski	0:01f31e923fe2	12	** MKL26Z256VMP4
Pawel Zarembski	0:01f31e923fe2	13	** MKL26Z32VFM4
Pawel Zarembski	0:01f31e923fe2	14	** MKL26Z32VFT4
Pawel Zarembski	0:01f31e923fe2	15	** MKL26Z32VLH4
Pawel Zarembski	0:01f31e923fe2	16	** MKL26Z64VFM4
Pawel Zarembski	0:01f31e923fe2	17	** MKL26Z64VFT4
Pawel Zarembski	0:01f31e923fe2	18	** MKL26Z64VLH4
Pawel Zarembski	0:01f31e923fe2	19	**
Pawel Zarembski	0:01f31e923fe2	20	** Compilers: Keil ARM C/C++ Compiler
Pawel Zarembski	0:01f31e923fe2	21	** Freescale C/C++ for Embedded ARM
Pawel Zarembski	0:01f31e923fe2	22	** GNU C Compiler
Pawel Zarembski	0:01f31e923fe2	23	** IAR ANSI C/C++ Compiler for ARM
Pawel Zarembski	0:01f31e923fe2	24	**
Pawel Zarembski	0:01f31e923fe2	25	** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
Pawel Zarembski	0:01f31e923fe2	26	** KL26P121M48SF4RM, Rev.2, Dec 2012
Pawel Zarembski	0:01f31e923fe2	27	**
Pawel Zarembski	0:01f31e923fe2	28	** Version: rev. 1.8, 2015-07-29
Pawel Zarembski	0:01f31e923fe2	29	** Build: b160126
Pawel Zarembski	0:01f31e923fe2	30	**
Pawel Zarembski	0:01f31e923fe2	31	** Abstract:
Pawel Zarembski	0:01f31e923fe2	32	** CMSIS Peripheral Access Layer for MKL26Z4
Pawel Zarembski	0:01f31e923fe2	33	**
Pawel Zarembski	0:01f31e923fe2	34	** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
Pawel Zarembski	0:01f31e923fe2	35	** All rights reserved.
Pawel Zarembski	0:01f31e923fe2	36	**
Pawel Zarembski	0:01f31e923fe2	37	** Redistribution and use in source and binary forms, with or without modification,
Pawel Zarembski	0:01f31e923fe2	38	** are permitted provided that the following conditions are met:
Pawel Zarembski	0:01f31e923fe2	39	**
Pawel Zarembski	0:01f31e923fe2	40	** o Redistributions of source code must retain the above copyright notice, this list
Pawel Zarembski	0:01f31e923fe2	41	** of conditions and the following disclaimer.
Pawel Zarembski	0:01f31e923fe2	42	**
Pawel Zarembski	0:01f31e923fe2	43	** o Redistributions in binary form must reproduce the above copyright notice, this
Pawel Zarembski	0:01f31e923fe2	44	** list of conditions and the following disclaimer in the documentation and/or
Pawel Zarembski	0:01f31e923fe2	45	** other materials provided with the distribution.
Pawel Zarembski	0:01f31e923fe2	46	**
Pawel Zarembski	0:01f31e923fe2	47	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Pawel Zarembski	0:01f31e923fe2	48	** contributors may be used to endorse or promote products derived from this
Pawel Zarembski	0:01f31e923fe2	49	** software without specific prior written permission.
Pawel Zarembski	0:01f31e923fe2	50	**
Pawel Zarembski	0:01f31e923fe2	51	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Pawel Zarembski	0:01f31e923fe2	52	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Pawel Zarembski	0:01f31e923fe2	53	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Pawel Zarembski	0:01f31e923fe2	54	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Pawel Zarembski	0:01f31e923fe2	55	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Pawel Zarembski	0:01f31e923fe2	56	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Pawel Zarembski	0:01f31e923fe2	57	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Pawel Zarembski	0:01f31e923fe2	58	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Pawel Zarembski	0:01f31e923fe2	59	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Pawel Zarembski	0:01f31e923fe2	60	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Pawel Zarembski	0:01f31e923fe2	61	**
Pawel Zarembski	0:01f31e923fe2	62	** http: www.freescale.com
Pawel Zarembski	0:01f31e923fe2	63	** mail: support@freescale.com
Pawel Zarembski	0:01f31e923fe2	64	**
Pawel Zarembski	0:01f31e923fe2	65	** Revisions:
Pawel Zarembski	0:01f31e923fe2	66	** - rev. 1.0 (2012-12-12)
Pawel Zarembski	0:01f31e923fe2	67	** Initial version.
Pawel Zarembski	0:01f31e923fe2	68	** - rev. 1.1 (2013-04-05)
Pawel Zarembski	0:01f31e923fe2	69	** Changed start of doxygen comment.
Pawel Zarembski	0:01f31e923fe2	70	** - rev. 1.2 (2013-04-12)
Pawel Zarembski	0:01f31e923fe2	71	** SystemInit function fixed for clock configuration 1.
Pawel Zarembski	0:01f31e923fe2	72	** Name of the interrupt num. 31 updated to reflect proper function.
Pawel Zarembski	0:01f31e923fe2	73	** - rev. 1.3 (2014-05-27)
Pawel Zarembski	0:01f31e923fe2	74	** Updated to Kinetis SDK support standard.
Pawel Zarembski	0:01f31e923fe2	75	** MCG OSC clock select supported (MCG_C7[OSCSEL]).
Pawel Zarembski	0:01f31e923fe2	76	** - rev. 1.4 (2014-07-25)
Pawel Zarembski	0:01f31e923fe2	77	** System initialization updated:
Pawel Zarembski	0:01f31e923fe2	78	** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
Pawel Zarembski	0:01f31e923fe2	79	** - VLLSx wake-up recovery added.
Pawel Zarembski	0:01f31e923fe2	80	** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
Pawel Zarembski	0:01f31e923fe2	81	** - rev. 1.5 (2014-08-28)
Pawel Zarembski	0:01f31e923fe2	82	** Update of system files - default clock configuration changed, fix of OSC initialization.
Pawel Zarembski	0:01f31e923fe2	83	** Update of startup files - possibility to override DefaultISR added.
Pawel Zarembski	0:01f31e923fe2	84	** - rev. 1.6 (2014-10-14)
Pawel Zarembski	0:01f31e923fe2	85	** Renamed interrupt vector LPTimer to LPTMR0
Pawel Zarembski	0:01f31e923fe2	86	** - rev. 1.7 (2015-02-18)
Pawel Zarembski	0:01f31e923fe2	87	** Renamed interrupt vector LLW to LLWU
Pawel Zarembski	0:01f31e923fe2	88	** - rev. 1.8 (2015-07-29)
Pawel Zarembski	0:01f31e923fe2	89	** Correction of backward compatibility.
Pawel Zarembski	0:01f31e923fe2	90	**
Pawel Zarembski	0:01f31e923fe2	91	** ###################################################################
Pawel Zarembski	0:01f31e923fe2	92	*/
Pawel Zarembski	0:01f31e923fe2	93
Pawel Zarembski	0:01f31e923fe2	94	/*!
Pawel Zarembski	0:01f31e923fe2	95	* @file MKL26Z4.h
Pawel Zarembski	0:01f31e923fe2	96	* @version 1.8
Pawel Zarembski	0:01f31e923fe2	97	* @date 2015-07-29
Pawel Zarembski	0:01f31e923fe2	98	* @brief CMSIS Peripheral Access Layer for MKL26Z4
Pawel Zarembski	0:01f31e923fe2	99	*
Pawel Zarembski	0:01f31e923fe2	100	* CMSIS Peripheral Access Layer for MKL26Z4
Pawel Zarembski	0:01f31e923fe2	101	*/
Pawel Zarembski	0:01f31e923fe2	102
Pawel Zarembski	0:01f31e923fe2	103	#ifndef _MKL26Z4_H_
Pawel Zarembski	0:01f31e923fe2	104	#define _MKL26Z4_H_ /*< Symbol preventing repeated inclusion /
Pawel Zarembski	0:01f31e923fe2	105
Pawel Zarembski	0:01f31e923fe2	106	/** Memory map major version (memory maps with equal major version number are
Pawel Zarembski	0:01f31e923fe2	107	* compatible) */
Pawel Zarembski	0:01f31e923fe2	108	#define MCU_MEM_MAP_VERSION 0x0100U
Pawel Zarembski	0:01f31e923fe2	109	/** Memory map minor version */
Pawel Zarembski	0:01f31e923fe2	110	#define MCU_MEM_MAP_VERSION_MINOR 0x0008U
Pawel Zarembski	0:01f31e923fe2	111
Pawel Zarembski	0:01f31e923fe2	112
Pawel Zarembski	0:01f31e923fe2	113	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	114	-- Interrupt vector numbers
Pawel Zarembski	0:01f31e923fe2	115	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	116
Pawel Zarembski	0:01f31e923fe2	117	/*!
Pawel Zarembski	0:01f31e923fe2	118	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Pawel Zarembski	0:01f31e923fe2	119	* @{
Pawel Zarembski	0:01f31e923fe2	120	*/
Pawel Zarembski	0:01f31e923fe2	121
Pawel Zarembski	0:01f31e923fe2	122	/** Interrupt Number Definitions */
Pawel Zarembski	0:01f31e923fe2	123	#define NUMBER_OF_INT_VECTORS 48 /*< Number of interrupts in the Vector table /
Pawel Zarembski	0:01f31e923fe2	124
Pawel Zarembski	0:01f31e923fe2	125	typedef enum IRQn {
Pawel Zarembski	0:01f31e923fe2	126	/* Auxiliary constants */
Pawel Zarembski	0:01f31e923fe2	127	NotAvail_IRQn = -128, /*< Not available device specific interrupt /
Pawel Zarembski	0:01f31e923fe2	128
Pawel Zarembski	0:01f31e923fe2	129	/* Core interrupts */
Pawel Zarembski	0:01f31e923fe2	130	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
Pawel Zarembski	0:01f31e923fe2	131	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
Pawel Zarembski	0:01f31e923fe2	132	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
Pawel Zarembski	0:01f31e923fe2	133	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
Pawel Zarembski	0:01f31e923fe2	134	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
Pawel Zarembski	0:01f31e923fe2	135
Pawel Zarembski	0:01f31e923fe2	136	/* Device specific interrupts */
Pawel Zarembski	0:01f31e923fe2	137	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete and error interrupt /
Pawel Zarembski	0:01f31e923fe2	138	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete and error interrupt /
Pawel Zarembski	0:01f31e923fe2	139	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete and error interrupt /
Pawel Zarembski	0:01f31e923fe2	140	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete and error interrupt /
Pawel Zarembski	0:01f31e923fe2	141	Reserved20_IRQn = 4, /*< Reserved interrupt /
Pawel Zarembski	0:01f31e923fe2	142	FTFA_IRQn = 5, /*< FTFA command complete and read collision /
Pawel Zarembski	0:01f31e923fe2	143	LVD_LVW_IRQn = 6, /*< Low-voltage detect, low-voltage warning /
Pawel Zarembski	0:01f31e923fe2	144	LLWU_IRQn = 7, /*< Low Leakage Wakeup /
Pawel Zarembski	0:01f31e923fe2	145	I2C0_IRQn = 8, /*< I2C0 interrupt /
Pawel Zarembski	0:01f31e923fe2	146	I2C1_IRQn = 9, /*< I2C1 interrupt /
Pawel Zarembski	0:01f31e923fe2	147	SPI0_IRQn = 10, /*< SPI0 single interrupt vector for all sources /
Pawel Zarembski	0:01f31e923fe2	148	SPI1_IRQn = 11, /*< SPI1 single interrupt vector for all sources /
Pawel Zarembski	0:01f31e923fe2	149	UART0_IRQn = 12, /*< UART0 status and error /
Pawel Zarembski	0:01f31e923fe2	150	UART1_IRQn = 13, /*< UART1 status and error /
Pawel Zarembski	0:01f31e923fe2	151	UART2_IRQn = 14, /*< UART2 status and error /
Pawel Zarembski	0:01f31e923fe2	152	ADC0_IRQn = 15, /*< ADC0 interrupt /
Pawel Zarembski	0:01f31e923fe2	153	CMP0_IRQn = 16, /*< CMP0 interrupt /
Pawel Zarembski	0:01f31e923fe2	154	TPM0_IRQn = 17, /*< TPM0 single interrupt vector for all sources /
Pawel Zarembski	0:01f31e923fe2	155	TPM1_IRQn = 18, /*< TPM1 single interrupt vector for all sources /
Pawel Zarembski	0:01f31e923fe2	156	TPM2_IRQn = 19, /*< TPM2 single interrupt vector for all sources /
Pawel Zarembski	0:01f31e923fe2	157	RTC_IRQn = 20, /*< RTC alarm interrupt /
Pawel Zarembski	0:01f31e923fe2	158	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
Pawel Zarembski	0:01f31e923fe2	159	PIT_IRQn = 22, /*< PIT single interrupt vector for all channels /
Pawel Zarembski	0:01f31e923fe2	160	I2S0_IRQn = 23, /*< I2S0 Single interrupt vector for all sources /
Pawel Zarembski	0:01f31e923fe2	161	USB0_IRQn = 24, /*< USB0 OTG /
Pawel Zarembski	0:01f31e923fe2	162	DAC0_IRQn = 25, /*< DAC0 interrupt /
Pawel Zarembski	0:01f31e923fe2	163	TSI0_IRQn = 26, /*< TSI0 interrupt /
Pawel Zarembski	0:01f31e923fe2	164	MCG_IRQn = 27, /*< MCG interrupt /
Pawel Zarembski	0:01f31e923fe2	165	LPTMR0_IRQn = 28, /*< LPTMR0 interrupt /
Pawel Zarembski	0:01f31e923fe2	166	Reserved45_IRQn = 29, /*< Reserved interrupt /
Pawel Zarembski	0:01f31e923fe2	167	PORTA_IRQn = 30, /*< PORTA pin detect /
Pawel Zarembski	0:01f31e923fe2	168	PORTC_PORTD_IRQn = 31 /*< Single interrupt vector for PORTC and PORTD pin detect /
Pawel Zarembski	0:01f31e923fe2	169	} IRQn_Type;
Pawel Zarembski	0:01f31e923fe2	170
Pawel Zarembski	0:01f31e923fe2	171	/*!
Pawel Zarembski	0:01f31e923fe2	172	* @}
Pawel Zarembski	0:01f31e923fe2	173	/ / end of group Interrupt_vector_numbers */
Pawel Zarembski	0:01f31e923fe2	174
Pawel Zarembski	0:01f31e923fe2	175
Pawel Zarembski	0:01f31e923fe2	176	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	177	-- Cortex M0 Core Configuration
Pawel Zarembski	0:01f31e923fe2	178	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	179
Pawel Zarembski	0:01f31e923fe2	180	/*!
Pawel Zarembski	0:01f31e923fe2	181	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
Pawel Zarembski	0:01f31e923fe2	182	* @{
Pawel Zarembski	0:01f31e923fe2	183	*/
Pawel Zarembski	0:01f31e923fe2	184
Pawel Zarembski	0:01f31e923fe2	185	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
Pawel Zarembski	0:01f31e923fe2	186	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
Pawel Zarembski	0:01f31e923fe2	187	#define __VTOR_PRESENT 1 /*< Defines if VTOR is present or not /
Pawel Zarembski	0:01f31e923fe2	188	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
Pawel Zarembski	0:01f31e923fe2	189	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
Pawel Zarembski	0:01f31e923fe2	190
Pawel Zarembski	0:01f31e923fe2	191	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
Pawel Zarembski	0:01f31e923fe2	192	#include "system_MKL26Z4.h" /* Device specific configuration file */
Pawel Zarembski	0:01f31e923fe2	193
Pawel Zarembski	0:01f31e923fe2	194	/*!
Pawel Zarembski	0:01f31e923fe2	195	* @}
Pawel Zarembski	0:01f31e923fe2	196	/ / end of group Cortex_Core_Configuration */
Pawel Zarembski	0:01f31e923fe2	197
Pawel Zarembski	0:01f31e923fe2	198
Pawel Zarembski	0:01f31e923fe2	199	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	200	-- Mapping Information
Pawel Zarembski	0:01f31e923fe2	201	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	202
Pawel Zarembski	0:01f31e923fe2	203	/*!
Pawel Zarembski	0:01f31e923fe2	204	* @addtogroup Mapping_Information Mapping Information
Pawel Zarembski	0:01f31e923fe2	205	* @{
Pawel Zarembski	0:01f31e923fe2	206	*/
Pawel Zarembski	0:01f31e923fe2	207
Pawel Zarembski	0:01f31e923fe2	208	/** Mapping Information */
Pawel Zarembski	0:01f31e923fe2	209	/*!
Pawel Zarembski	0:01f31e923fe2	210	* @addtogroup edma_request
Pawel Zarembski	0:01f31e923fe2	211	* @{
Pawel Zarembski	0:01f31e923fe2	212	*/
Pawel Zarembski	0:01f31e923fe2	213
Pawel Zarembski	0:01f31e923fe2	214	/*******************************************************************************
Pawel Zarembski	0:01f31e923fe2	215	* Definitions
Pawel Zarembski	0:01f31e923fe2	216	******************************************************************************/
Pawel Zarembski	0:01f31e923fe2	217
Pawel Zarembski	0:01f31e923fe2	218	/*!
Pawel Zarembski	0:01f31e923fe2	219	* @brief Structure for the DMA hardware request
Pawel Zarembski	0:01f31e923fe2	220	*
Pawel Zarembski	0:01f31e923fe2	221	* Defines the structure for the DMA hardware request collections. The user can configure the
Pawel Zarembski	0:01f31e923fe2	222	* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
Pawel Zarembski	0:01f31e923fe2	223	* of the hardware request varies according to the to SoC.
Pawel Zarembski	0:01f31e923fe2	224	*/
Pawel Zarembski	0:01f31e923fe2	225	typedef enum _dma_request_source
Pawel Zarembski	0:01f31e923fe2	226	{
Pawel Zarembski	0:01f31e923fe2	227	kDmaRequestMux0Disable = 0\|0x100U, /*< Disable /
Pawel Zarembski	0:01f31e923fe2	228	kDmaRequestMux0Reserved1 = 1\|0x100U, /*< Reserved1 /
Pawel Zarembski	0:01f31e923fe2	229	kDmaRequestMux0UART0Rx = 2\|0x100U, /*< UART0 receive complete /
Pawel Zarembski	0:01f31e923fe2	230	kDmaRequestMux0LPSCI0Rx = 2\|0x100U, /*< UART0 receive complete /
Pawel Zarembski	0:01f31e923fe2	231	kDmaRequestMux0UART0Tx = 3\|0x100U, /*< UART0 transmit complete /
Pawel Zarembski	0:01f31e923fe2	232	kDmaRequestMux0LPSCI0Tx = 3\|0x100U, /*< UART0 transmit complete /
Pawel Zarembski	0:01f31e923fe2	233	kDmaRequestMux0UART1Rx = 4\|0x100U, /*< UART1 receive complete /
Pawel Zarembski	0:01f31e923fe2	234	kDmaRequestMux0UART1Tx = 5\|0x100U, /*< UART1 transmit complete /
Pawel Zarembski	0:01f31e923fe2	235	kDmaRequestMux0UART2Rx = 6\|0x100U, /*< UART2 receive complete /
Pawel Zarembski	0:01f31e923fe2	236	kDmaRequestMux0UART2Tx = 7\|0x100U, /*< UART2 transmit complete /
Pawel Zarembski	0:01f31e923fe2	237	kDmaRequestMux0Reserved8 = 8\|0x100U, /*< Reserved8 /
Pawel Zarembski	0:01f31e923fe2	238	kDmaRequestMux0Reserved9 = 9\|0x100U, /*< Reserved9 /
Pawel Zarembski	0:01f31e923fe2	239	kDmaRequestMux0Reserved10 = 10\|0x100U, /*< Reserved10 /
Pawel Zarembski	0:01f31e923fe2	240	kDmaRequestMux0Reserved11 = 11\|0x100U, /*< Reserved11 /
Pawel Zarembski	0:01f31e923fe2	241	kDmaRequestMux0Reserved12 = 12\|0x100U, /*< Reserved12 /
Pawel Zarembski	0:01f31e923fe2	242	kDmaRequestMux0Reserved13 = 13\|0x100U, /*< Reserved13 /
Pawel Zarembski	0:01f31e923fe2	243	kDmaRequestMux0I2S0Rx = 14\|0x100U, /*< I2S0 receive complete /
Pawel Zarembski	0:01f31e923fe2	244	kDmaRequestMux0I2S0Tx = 15\|0x100U, /*< I2S0 transmit complete /
Pawel Zarembski	0:01f31e923fe2	245	kDmaRequestMux0SPI0Rx = 16\|0x100U, /*< SPI0 receive complete /
Pawel Zarembski	0:01f31e923fe2	246	kDmaRequestMux0SPI0Tx = 17\|0x100U, /*< SPI0 transmit complete /
Pawel Zarembski	0:01f31e923fe2	247	kDmaRequestMux0SPI1Rx = 18\|0x100U, /*< SPI1 receive complete /
Pawel Zarembski	0:01f31e923fe2	248	kDmaRequestMux0SPI1Tx = 19\|0x100U, /*< SPI1 transmit complete /
Pawel Zarembski	0:01f31e923fe2	249	kDmaRequestMux0Reserved20 = 20\|0x100U, /*< Reserved20 /
Pawel Zarembski	0:01f31e923fe2	250	kDmaRequestMux0Reserved21 = 21\|0x100U, /*< Reserved21 /
Pawel Zarembski	0:01f31e923fe2	251	kDmaRequestMux0I2C0 = 22\|0x100U, /*< I2C0 transmission complete /
Pawel Zarembski	0:01f31e923fe2	252	kDmaRequestMux0I2C1 = 23\|0x100U, /*< I2C1 transmission complete /
Pawel Zarembski	0:01f31e923fe2	253	kDmaRequestMux0TPM0Channel0 = 24\|0x100U, /*< TPM0 channel 0 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	254	kDmaRequestMux0TPM0Channel1 = 25\|0x100U, /*< TPM0 channel 1 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	255	kDmaRequestMux0TPM0Channel2 = 26\|0x100U, /*< TPM0 channel 2 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	256	kDmaRequestMux0TPM0Channel3 = 27\|0x100U, /*< TPM0 channel 3 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	257	kDmaRequestMux0TPM0Channel4 = 28\|0x100U, /*< TPM0 channel 4 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	258	kDmaRequestMux0TPM0Channel5 = 29\|0x100U, /*< TPM0 channel 5 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	259	kDmaRequestMux0Reserved30 = 30\|0x100U, /*< Reserved30 /
Pawel Zarembski	0:01f31e923fe2	260	kDmaRequestMux0Reserved31 = 31\|0x100U, /*< Reserved31 /
Pawel Zarembski	0:01f31e923fe2	261	kDmaRequestMux0TPM1Channel0 = 32\|0x100U, /*< TPM1 channel 0 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	262	kDmaRequestMux0TPM1Channel1 = 33\|0x100U, /*< TPM1 channel 1 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	263	kDmaRequestMux0TPM2Channel0 = 34\|0x100U, /*< TPM2 channel 0 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	264	kDmaRequestMux0TPM2Channel1 = 35\|0x100U, /*< TPM2 channel 1 event (CMP or CAP) /
Pawel Zarembski	0:01f31e923fe2	265	kDmaRequestMux0Reserved36 = 36\|0x100U, /*< Reserved36 /
Pawel Zarembski	0:01f31e923fe2	266	kDmaRequestMux0Reserved37 = 37\|0x100U, /*< Reserved37 /
Pawel Zarembski	0:01f31e923fe2	267	kDmaRequestMux0Reserved38 = 38\|0x100U, /*< Reserved38 /
Pawel Zarembski	0:01f31e923fe2	268	kDmaRequestMux0Reserved39 = 39\|0x100U, /*< Reserved39 /
Pawel Zarembski	0:01f31e923fe2	269	kDmaRequestMux0ADC0 = 40\|0x100U, /*< ADC0 conversion complete /
Pawel Zarembski	0:01f31e923fe2	270	kDmaRequestMux0Reserved41 = 41\|0x100U, /*< Reserved41 /
Pawel Zarembski	0:01f31e923fe2	271	kDmaRequestMux0CMP0 = 42\|0x100U, /*< CMP0 Output /
Pawel Zarembski	0:01f31e923fe2	272	kDmaRequestMux0Reserved43 = 43\|0x100U, /*< Reserved43 /
Pawel Zarembski	0:01f31e923fe2	273	kDmaRequestMux0Reserved44 = 44\|0x100U, /*< Reserved44 /
Pawel Zarembski	0:01f31e923fe2	274	kDmaRequestMux0DAC0 = 45\|0x100U, /*< DAC0 buffer pointer reaches upper or lower limit /
Pawel Zarembski	0:01f31e923fe2	275	kDmaRequestMux0Reserved46 = 46\|0x100U, /*< Reserved46 /
Pawel Zarembski	0:01f31e923fe2	276	kDmaRequestMux0Reserved47 = 47\|0x100U, /*< Reserved47 /
Pawel Zarembski	0:01f31e923fe2	277	kDmaRequestMux0Reserved48 = 48\|0x100U, /*< Reserved48 /
Pawel Zarembski	0:01f31e923fe2	278	kDmaRequestMux0PortA = 49\|0x100U, /*< PORTA rising, falling or both edges /
Pawel Zarembski	0:01f31e923fe2	279	kDmaRequestMux0Reserved50 = 50\|0x100U, /*< Reserved50 /
Pawel Zarembski	0:01f31e923fe2	280	kDmaRequestMux0PortC = 51\|0x100U, /*< PORTC rising, falling or both edges /
Pawel Zarembski	0:01f31e923fe2	281	kDmaRequestMux0PortD = 52\|0x100U, /*< PORTD rising, falling or both edges /
Pawel Zarembski	0:01f31e923fe2	282	kDmaRequestMux0Reserved53 = 53\|0x100U, /*< Reserved53 /
Pawel Zarembski	0:01f31e923fe2	283	kDmaRequestMux0TPM0Overflow = 54\|0x100U, /*< TPM0 overflow /
Pawel Zarembski	0:01f31e923fe2	284	kDmaRequestMux0TPM1Overflow = 55\|0x100U, /*< TPM1 overflow /
Pawel Zarembski	0:01f31e923fe2	285	kDmaRequestMux0TPM2Overflow = 56\|0x100U, /*< TPM2 overflow /
Pawel Zarembski	0:01f31e923fe2	286	kDmaRequestMux0TSI = 57\|0x100U, /*< TSI0 event /
Pawel Zarembski	0:01f31e923fe2	287	kDmaRequestMux0Reserved58 = 58\|0x100U, /*< Reserved58 /
Pawel Zarembski	0:01f31e923fe2	288	kDmaRequestMux0Reserved59 = 59\|0x100U, /*< Reserved59 /
Pawel Zarembski	0:01f31e923fe2	289	kDmaRequestMux0AlwaysOn60 = 60\|0x100U, /*< Always enabled 60 /
Pawel Zarembski	0:01f31e923fe2	290	kDmaRequestMux0AlwaysOn61 = 61\|0x100U, /*< Always enabled 61 /
Pawel Zarembski	0:01f31e923fe2	291	kDmaRequestMux0AlwaysOn62 = 62\|0x100U, /*< Always enabled 62 /
Pawel Zarembski	0:01f31e923fe2	292	kDmaRequestMux0AlwaysOn63 = 63\|0x100U, /*< Always enabled 63 /
Pawel Zarembski	0:01f31e923fe2	293	} dma_request_source_t;
Pawel Zarembski	0:01f31e923fe2	294
Pawel Zarembski	0:01f31e923fe2	295	/* @} */
Pawel Zarembski	0:01f31e923fe2	296
Pawel Zarembski	0:01f31e923fe2	297
Pawel Zarembski	0:01f31e923fe2	298	/*!
Pawel Zarembski	0:01f31e923fe2	299	* @}
Pawel Zarembski	0:01f31e923fe2	300	/ / end of group Mapping_Information */
Pawel Zarembski	0:01f31e923fe2	301
Pawel Zarembski	0:01f31e923fe2	302
Pawel Zarembski	0:01f31e923fe2	303	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	304	-- Device Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	305	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	306
Pawel Zarembski	0:01f31e923fe2	307	/*!
Pawel Zarembski	0:01f31e923fe2	308	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	309	* @{
Pawel Zarembski	0:01f31e923fe2	310	*/
Pawel Zarembski	0:01f31e923fe2	311
Pawel Zarembski	0:01f31e923fe2	312
Pawel Zarembski	0:01f31e923fe2	313	/*
Pawel Zarembski	0:01f31e923fe2	314	** Start of section using anonymous unions
Pawel Zarembski	0:01f31e923fe2	315	*/
Pawel Zarembski	0:01f31e923fe2	316
Pawel Zarembski	0:01f31e923fe2	317	#if defined(__ARMCC_VERSION)
Pawel Zarembski	0:01f31e923fe2	318	#pragma push
Pawel Zarembski	0:01f31e923fe2	319	#pragma anon_unions
Pawel Zarembski	0:01f31e923fe2	320	#elif defined(__CWCC__)
Pawel Zarembski	0:01f31e923fe2	321	#pragma push
Pawel Zarembski	0:01f31e923fe2	322	#pragma cpp_extensions on
Pawel Zarembski	0:01f31e923fe2	323	#elif defined(__GNUC__)
Pawel Zarembski	0:01f31e923fe2	324	/* anonymous unions are enabled by default */
Pawel Zarembski	0:01f31e923fe2	325	#elif defined(__IAR_SYSTEMS_ICC__)
Pawel Zarembski	0:01f31e923fe2	326	#pragma language=extended
Pawel Zarembski	0:01f31e923fe2	327	#else
Pawel Zarembski	0:01f31e923fe2	328	#error Not supported compiler type
Pawel Zarembski	0:01f31e923fe2	329	#endif
Pawel Zarembski	0:01f31e923fe2	330
Pawel Zarembski	0:01f31e923fe2	331	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	332	-- ADC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	333	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	334
Pawel Zarembski	0:01f31e923fe2	335	/*!
Pawel Zarembski	0:01f31e923fe2	336	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	337	* @{
Pawel Zarembski	0:01f31e923fe2	338	*/
Pawel Zarembski	0:01f31e923fe2	339
Pawel Zarembski	0:01f31e923fe2	340	/** ADC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	341	typedef struct {
Pawel Zarembski	0:01f31e923fe2	342	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	343	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	344	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	345	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	346	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	347	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	348	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
Pawel Zarembski	0:01f31e923fe2	349	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
Pawel Zarembski	0:01f31e923fe2	350	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
Pawel Zarembski	0:01f31e923fe2	351	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
Pawel Zarembski	0:01f31e923fe2	352	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
Pawel Zarembski	0:01f31e923fe2	353	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
Pawel Zarembski	0:01f31e923fe2	354	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
Pawel Zarembski	0:01f31e923fe2	355	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
Pawel Zarembski	0:01f31e923fe2	356	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
Pawel Zarembski	0:01f31e923fe2	357	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
Pawel Zarembski	0:01f31e923fe2	358	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
Pawel Zarembski	0:01f31e923fe2	359	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
Pawel Zarembski	0:01f31e923fe2	360	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	361	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
Pawel Zarembski	0:01f31e923fe2	362	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
Pawel Zarembski	0:01f31e923fe2	363	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
Pawel Zarembski	0:01f31e923fe2	364	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
Pawel Zarembski	0:01f31e923fe2	365	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
Pawel Zarembski	0:01f31e923fe2	366	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
Pawel Zarembski	0:01f31e923fe2	367	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
Pawel Zarembski	0:01f31e923fe2	368	} ADC_Type;
Pawel Zarembski	0:01f31e923fe2	369
Pawel Zarembski	0:01f31e923fe2	370	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	371	-- ADC Register Masks
Pawel Zarembski	0:01f31e923fe2	372	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	373
Pawel Zarembski	0:01f31e923fe2	374	/*!
Pawel Zarembski	0:01f31e923fe2	375	* @addtogroup ADC_Register_Masks ADC Register Masks
Pawel Zarembski	0:01f31e923fe2	376	* @{
Pawel Zarembski	0:01f31e923fe2	377	*/
Pawel Zarembski	0:01f31e923fe2	378
Pawel Zarembski	0:01f31e923fe2	379	/! @name SC1 - ADC Status and Control Registers 1 /
Pawel Zarembski	0:01f31e923fe2	380	#define ADC_SC1_ADCH_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	381	#define ADC_SC1_ADCH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	382	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
Pawel Zarembski	0:01f31e923fe2	383	#define ADC_SC1_DIFF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	384	#define ADC_SC1_DIFF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	385	#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
Pawel Zarembski	0:01f31e923fe2	386	#define ADC_SC1_AIEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	387	#define ADC_SC1_AIEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	388	#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	389	#define ADC_SC1_COCO_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	390	#define ADC_SC1_COCO_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	391	#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
Pawel Zarembski	0:01f31e923fe2	392
Pawel Zarembski	0:01f31e923fe2	393	/* The count of ADC_SC1 */
Pawel Zarembski	0:01f31e923fe2	394	#define ADC_SC1_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	395
Pawel Zarembski	0:01f31e923fe2	396	/! @name CFG1 - ADC Configuration Register 1 /
Pawel Zarembski	0:01f31e923fe2	397	#define ADC_CFG1_ADICLK_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	398	#define ADC_CFG1_ADICLK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	399	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
Pawel Zarembski	0:01f31e923fe2	400	#define ADC_CFG1_MODE_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	401	#define ADC_CFG1_MODE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	402	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
Pawel Zarembski	0:01f31e923fe2	403	#define ADC_CFG1_ADLSMP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	404	#define ADC_CFG1_ADLSMP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	405	#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
Pawel Zarembski	0:01f31e923fe2	406	#define ADC_CFG1_ADIV_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	407	#define ADC_CFG1_ADIV_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	408	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
Pawel Zarembski	0:01f31e923fe2	409	#define ADC_CFG1_ADLPC_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	410	#define ADC_CFG1_ADLPC_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	411	#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
Pawel Zarembski	0:01f31e923fe2	412
Pawel Zarembski	0:01f31e923fe2	413	/! @name CFG2 - ADC Configuration Register 2 /
Pawel Zarembski	0:01f31e923fe2	414	#define ADC_CFG2_ADLSTS_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	415	#define ADC_CFG2_ADLSTS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	416	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
Pawel Zarembski	0:01f31e923fe2	417	#define ADC_CFG2_ADHSC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	418	#define ADC_CFG2_ADHSC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	419	#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
Pawel Zarembski	0:01f31e923fe2	420	#define ADC_CFG2_ADACKEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	421	#define ADC_CFG2_ADACKEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	422	#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	423	#define ADC_CFG2_MUXSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	424	#define ADC_CFG2_MUXSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	425	#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	426
Pawel Zarembski	0:01f31e923fe2	427	/! @name R - ADC Data Result Register /
Pawel Zarembski	0:01f31e923fe2	428	#define ADC_R_D_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	429	#define ADC_R_D_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	430	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
Pawel Zarembski	0:01f31e923fe2	431
Pawel Zarembski	0:01f31e923fe2	432	/* The count of ADC_R */
Pawel Zarembski	0:01f31e923fe2	433	#define ADC_R_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	434
Pawel Zarembski	0:01f31e923fe2	435	/! @name CV1 - Compare Value Registers /
Pawel Zarembski	0:01f31e923fe2	436	#define ADC_CV1_CV_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	437	#define ADC_CV1_CV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	438	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
Pawel Zarembski	0:01f31e923fe2	439
Pawel Zarembski	0:01f31e923fe2	440	/! @name CV2 - Compare Value Registers /
Pawel Zarembski	0:01f31e923fe2	441	#define ADC_CV2_CV_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	442	#define ADC_CV2_CV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	443	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
Pawel Zarembski	0:01f31e923fe2	444
Pawel Zarembski	0:01f31e923fe2	445	/! @name SC2 - Status and Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	446	#define ADC_SC2_REFSEL_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	447	#define ADC_SC2_REFSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	448	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	449	#define ADC_SC2_DMAEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	450	#define ADC_SC2_DMAEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	451	#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	452	#define ADC_SC2_ACREN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	453	#define ADC_SC2_ACREN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	454	#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
Pawel Zarembski	0:01f31e923fe2	455	#define ADC_SC2_ACFGT_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	456	#define ADC_SC2_ACFGT_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	457	#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
Pawel Zarembski	0:01f31e923fe2	458	#define ADC_SC2_ACFE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	459	#define ADC_SC2_ACFE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	460	#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
Pawel Zarembski	0:01f31e923fe2	461	#define ADC_SC2_ADTRG_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	462	#define ADC_SC2_ADTRG_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	463	#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
Pawel Zarembski	0:01f31e923fe2	464	#define ADC_SC2_ADACT_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	465	#define ADC_SC2_ADACT_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	466	#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
Pawel Zarembski	0:01f31e923fe2	467
Pawel Zarembski	0:01f31e923fe2	468	/! @name SC3 - Status and Control Register 3 /
Pawel Zarembski	0:01f31e923fe2	469	#define ADC_SC3_AVGS_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	470	#define ADC_SC3_AVGS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	471	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
Pawel Zarembski	0:01f31e923fe2	472	#define ADC_SC3_AVGE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	473	#define ADC_SC3_AVGE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	474	#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
Pawel Zarembski	0:01f31e923fe2	475	#define ADC_SC3_ADCO_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	476	#define ADC_SC3_ADCO_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	477	#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
Pawel Zarembski	0:01f31e923fe2	478	#define ADC_SC3_CALF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	479	#define ADC_SC3_CALF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	480	#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
Pawel Zarembski	0:01f31e923fe2	481	#define ADC_SC3_CAL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	482	#define ADC_SC3_CAL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	483	#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
Pawel Zarembski	0:01f31e923fe2	484
Pawel Zarembski	0:01f31e923fe2	485	/! @name OFS - ADC Offset Correction Register /
Pawel Zarembski	0:01f31e923fe2	486	#define ADC_OFS_OFS_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	487	#define ADC_OFS_OFS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	488	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
Pawel Zarembski	0:01f31e923fe2	489
Pawel Zarembski	0:01f31e923fe2	490	/! @name PG - ADC Plus-Side Gain Register /
Pawel Zarembski	0:01f31e923fe2	491	#define ADC_PG_PG_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	492	#define ADC_PG_PG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	493	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
Pawel Zarembski	0:01f31e923fe2	494
Pawel Zarembski	0:01f31e923fe2	495	/! @name MG - ADC Minus-Side Gain Register /
Pawel Zarembski	0:01f31e923fe2	496	#define ADC_MG_MG_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	497	#define ADC_MG_MG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	498	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
Pawel Zarembski	0:01f31e923fe2	499
Pawel Zarembski	0:01f31e923fe2	500	/! @name CLPD - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	501	#define ADC_CLPD_CLPD_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	502	#define ADC_CLPD_CLPD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	503	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
Pawel Zarembski	0:01f31e923fe2	504
Pawel Zarembski	0:01f31e923fe2	505	/! @name CLPS - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	506	#define ADC_CLPS_CLPS_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	507	#define ADC_CLPS_CLPS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	508	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
Pawel Zarembski	0:01f31e923fe2	509
Pawel Zarembski	0:01f31e923fe2	510	/! @name CLP4 - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	511	#define ADC_CLP4_CLP4_MASK (0x3FFU)
Pawel Zarembski	0:01f31e923fe2	512	#define ADC_CLP4_CLP4_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	513	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
Pawel Zarembski	0:01f31e923fe2	514
Pawel Zarembski	0:01f31e923fe2	515	/! @name CLP3 - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	516	#define ADC_CLP3_CLP3_MASK (0x1FFU)
Pawel Zarembski	0:01f31e923fe2	517	#define ADC_CLP3_CLP3_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	518	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
Pawel Zarembski	0:01f31e923fe2	519
Pawel Zarembski	0:01f31e923fe2	520	/! @name CLP2 - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	521	#define ADC_CLP2_CLP2_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	522	#define ADC_CLP2_CLP2_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	523	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
Pawel Zarembski	0:01f31e923fe2	524
Pawel Zarembski	0:01f31e923fe2	525	/! @name CLP1 - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	526	#define ADC_CLP1_CLP1_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	527	#define ADC_CLP1_CLP1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	528	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
Pawel Zarembski	0:01f31e923fe2	529
Pawel Zarembski	0:01f31e923fe2	530	/! @name CLP0 - ADC Plus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	531	#define ADC_CLP0_CLP0_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	532	#define ADC_CLP0_CLP0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	533	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
Pawel Zarembski	0:01f31e923fe2	534
Pawel Zarembski	0:01f31e923fe2	535	/! @name CLMD - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	536	#define ADC_CLMD_CLMD_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	537	#define ADC_CLMD_CLMD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	538	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
Pawel Zarembski	0:01f31e923fe2	539
Pawel Zarembski	0:01f31e923fe2	540	/! @name CLMS - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	541	#define ADC_CLMS_CLMS_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	542	#define ADC_CLMS_CLMS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	543	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
Pawel Zarembski	0:01f31e923fe2	544
Pawel Zarembski	0:01f31e923fe2	545	/! @name CLM4 - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	546	#define ADC_CLM4_CLM4_MASK (0x3FFU)
Pawel Zarembski	0:01f31e923fe2	547	#define ADC_CLM4_CLM4_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	548	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
Pawel Zarembski	0:01f31e923fe2	549
Pawel Zarembski	0:01f31e923fe2	550	/! @name CLM3 - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	551	#define ADC_CLM3_CLM3_MASK (0x1FFU)
Pawel Zarembski	0:01f31e923fe2	552	#define ADC_CLM3_CLM3_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	553	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
Pawel Zarembski	0:01f31e923fe2	554
Pawel Zarembski	0:01f31e923fe2	555	/! @name CLM2 - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	556	#define ADC_CLM2_CLM2_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	557	#define ADC_CLM2_CLM2_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	558	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
Pawel Zarembski	0:01f31e923fe2	559
Pawel Zarembski	0:01f31e923fe2	560	/! @name CLM1 - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	561	#define ADC_CLM1_CLM1_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	562	#define ADC_CLM1_CLM1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	563	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
Pawel Zarembski	0:01f31e923fe2	564
Pawel Zarembski	0:01f31e923fe2	565	/! @name CLM0 - ADC Minus-Side General Calibration Value Register /
Pawel Zarembski	0:01f31e923fe2	566	#define ADC_CLM0_CLM0_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	567	#define ADC_CLM0_CLM0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	568	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
Pawel Zarembski	0:01f31e923fe2	569
Pawel Zarembski	0:01f31e923fe2	570
Pawel Zarembski	0:01f31e923fe2	571	/*!
Pawel Zarembski	0:01f31e923fe2	572	* @}
Pawel Zarembski	0:01f31e923fe2	573	/ / end of group ADC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	574
Pawel Zarembski	0:01f31e923fe2	575
Pawel Zarembski	0:01f31e923fe2	576	/* ADC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	577	/** Peripheral ADC0 base address */
Pawel Zarembski	0:01f31e923fe2	578	#define ADC0_BASE (0x4003B000u)
Pawel Zarembski	0:01f31e923fe2	579	/** Peripheral ADC0 base pointer */
Pawel Zarembski	0:01f31e923fe2	580	#define ADC0 ((ADC_Type *)ADC0_BASE)
Pawel Zarembski	0:01f31e923fe2	581	/** Array initializer of ADC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	582	#define ADC_BASE_ADDRS { ADC0_BASE }
Pawel Zarembski	0:01f31e923fe2	583	/** Array initializer of ADC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	584	#define ADC_BASE_PTRS { ADC0 }
Pawel Zarembski	0:01f31e923fe2	585	/** Interrupt vectors for the ADC peripheral type */
Pawel Zarembski	0:01f31e923fe2	586	#define ADC_IRQS { ADC0_IRQn }
Pawel Zarembski	0:01f31e923fe2	587
Pawel Zarembski	0:01f31e923fe2	588	/*!
Pawel Zarembski	0:01f31e923fe2	589	* @}
Pawel Zarembski	0:01f31e923fe2	590	/ / end of group ADC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	591
Pawel Zarembski	0:01f31e923fe2	592
Pawel Zarembski	0:01f31e923fe2	593	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	594	-- CMP Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	595	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	596
Pawel Zarembski	0:01f31e923fe2	597	/*!
Pawel Zarembski	0:01f31e923fe2	598	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	599	* @{
Pawel Zarembski	0:01f31e923fe2	600	*/
Pawel Zarembski	0:01f31e923fe2	601
Pawel Zarembski	0:01f31e923fe2	602	/** CMP - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	603	typedef struct {
Pawel Zarembski	0:01f31e923fe2	604	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	605	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	606	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	607	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	608	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	609	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	610	} CMP_Type;
Pawel Zarembski	0:01f31e923fe2	611
Pawel Zarembski	0:01f31e923fe2	612	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	613	-- CMP Register Masks
Pawel Zarembski	0:01f31e923fe2	614	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	615
Pawel Zarembski	0:01f31e923fe2	616	/*!
Pawel Zarembski	0:01f31e923fe2	617	* @addtogroup CMP_Register_Masks CMP Register Masks
Pawel Zarembski	0:01f31e923fe2	618	* @{
Pawel Zarembski	0:01f31e923fe2	619	*/
Pawel Zarembski	0:01f31e923fe2	620
Pawel Zarembski	0:01f31e923fe2	621	/! @name CR0 - CMP Control Register 0 /
Pawel Zarembski	0:01f31e923fe2	622	#define CMP_CR0_HYSTCTR_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	623	#define CMP_CR0_HYSTCTR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	624	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
Pawel Zarembski	0:01f31e923fe2	625	#define CMP_CR0_FILTER_CNT_MASK (0x70U)
Pawel Zarembski	0:01f31e923fe2	626	#define CMP_CR0_FILTER_CNT_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	627	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
Pawel Zarembski	0:01f31e923fe2	628
Pawel Zarembski	0:01f31e923fe2	629	/! @name CR1 - CMP Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	630	#define CMP_CR1_EN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	631	#define CMP_CR1_EN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	632	#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
Pawel Zarembski	0:01f31e923fe2	633	#define CMP_CR1_OPE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	634	#define CMP_CR1_OPE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	635	#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
Pawel Zarembski	0:01f31e923fe2	636	#define CMP_CR1_COS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	637	#define CMP_CR1_COS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	638	#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
Pawel Zarembski	0:01f31e923fe2	639	#define CMP_CR1_INV_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	640	#define CMP_CR1_INV_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	641	#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
Pawel Zarembski	0:01f31e923fe2	642	#define CMP_CR1_PMODE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	643	#define CMP_CR1_PMODE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	644	#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	645	#define CMP_CR1_TRIGM_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	646	#define CMP_CR1_TRIGM_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	647	#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
Pawel Zarembski	0:01f31e923fe2	648	#define CMP_CR1_WE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	649	#define CMP_CR1_WE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	650	#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
Pawel Zarembski	0:01f31e923fe2	651	#define CMP_CR1_SE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	652	#define CMP_CR1_SE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	653	#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
Pawel Zarembski	0:01f31e923fe2	654
Pawel Zarembski	0:01f31e923fe2	655	/! @name FPR - CMP Filter Period Register /
Pawel Zarembski	0:01f31e923fe2	656	#define CMP_FPR_FILT_PER_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	657	#define CMP_FPR_FILT_PER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	658	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
Pawel Zarembski	0:01f31e923fe2	659
Pawel Zarembski	0:01f31e923fe2	660	/! @name SCR - CMP Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	661	#define CMP_SCR_COUT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	662	#define CMP_SCR_COUT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	663	#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
Pawel Zarembski	0:01f31e923fe2	664	#define CMP_SCR_CFF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	665	#define CMP_SCR_CFF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	666	#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
Pawel Zarembski	0:01f31e923fe2	667	#define CMP_SCR_CFR_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	668	#define CMP_SCR_CFR_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	669	#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
Pawel Zarembski	0:01f31e923fe2	670	#define CMP_SCR_IEF_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	671	#define CMP_SCR_IEF_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	672	#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
Pawel Zarembski	0:01f31e923fe2	673	#define CMP_SCR_IER_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	674	#define CMP_SCR_IER_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	675	#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
Pawel Zarembski	0:01f31e923fe2	676	#define CMP_SCR_DMAEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	677	#define CMP_SCR_DMAEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	678	#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	679
Pawel Zarembski	0:01f31e923fe2	680	/! @name DACCR - DAC Control Register /
Pawel Zarembski	0:01f31e923fe2	681	#define CMP_DACCR_VOSEL_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	682	#define CMP_DACCR_VOSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	683	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	684	#define CMP_DACCR_VRSEL_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	685	#define CMP_DACCR_VRSEL_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	686	#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	687	#define CMP_DACCR_DACEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	688	#define CMP_DACCR_DACEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	689	#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
Pawel Zarembski	0:01f31e923fe2	690
Pawel Zarembski	0:01f31e923fe2	691	/! @name MUXCR - MUX Control Register /
Pawel Zarembski	0:01f31e923fe2	692	#define CMP_MUXCR_MSEL_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	693	#define CMP_MUXCR_MSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	694	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	695	#define CMP_MUXCR_PSEL_MASK (0x38U)
Pawel Zarembski	0:01f31e923fe2	696	#define CMP_MUXCR_PSEL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	697	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	698	#define CMP_MUXCR_PSTM_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	699	#define CMP_MUXCR_PSTM_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	700	#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
Pawel Zarembski	0:01f31e923fe2	701
Pawel Zarembski	0:01f31e923fe2	702
Pawel Zarembski	0:01f31e923fe2	703	/*!
Pawel Zarembski	0:01f31e923fe2	704	* @}
Pawel Zarembski	0:01f31e923fe2	705	/ / end of group CMP_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	706
Pawel Zarembski	0:01f31e923fe2	707
Pawel Zarembski	0:01f31e923fe2	708	/* CMP - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	709	/** Peripheral CMP0 base address */
Pawel Zarembski	0:01f31e923fe2	710	#define CMP0_BASE (0x40073000u)
Pawel Zarembski	0:01f31e923fe2	711	/** Peripheral CMP0 base pointer */
Pawel Zarembski	0:01f31e923fe2	712	#define CMP0 ((CMP_Type *)CMP0_BASE)
Pawel Zarembski	0:01f31e923fe2	713	/** Array initializer of CMP peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	714	#define CMP_BASE_ADDRS { CMP0_BASE }
Pawel Zarembski	0:01f31e923fe2	715	/** Array initializer of CMP peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	716	#define CMP_BASE_PTRS { CMP0 }
Pawel Zarembski	0:01f31e923fe2	717	/** Interrupt vectors for the CMP peripheral type */
Pawel Zarembski	0:01f31e923fe2	718	#define CMP_IRQS { CMP0_IRQn }
Pawel Zarembski	0:01f31e923fe2	719
Pawel Zarembski	0:01f31e923fe2	720	/*!
Pawel Zarembski	0:01f31e923fe2	721	* @}
Pawel Zarembski	0:01f31e923fe2	722	/ / end of group CMP_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	723
Pawel Zarembski	0:01f31e923fe2	724
Pawel Zarembski	0:01f31e923fe2	725	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	726	-- DAC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	727	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	728
Pawel Zarembski	0:01f31e923fe2	729	/*!
Pawel Zarembski	0:01f31e923fe2	730	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	731	* @{
Pawel Zarembski	0:01f31e923fe2	732	*/
Pawel Zarembski	0:01f31e923fe2	733
Pawel Zarembski	0:01f31e923fe2	734	/** DAC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	735	typedef struct {
Pawel Zarembski	0:01f31e923fe2	736	struct { /* offset: 0x0, array step: 0x2 */
Pawel Zarembski	0:01f31e923fe2	737	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
Pawel Zarembski	0:01f31e923fe2	738	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
Pawel Zarembski	0:01f31e923fe2	739	} DAT[2];
Pawel Zarembski	0:01f31e923fe2	740	uint8_t RESERVED_0[28];
Pawel Zarembski	0:01f31e923fe2	741	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
Pawel Zarembski	0:01f31e923fe2	742	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
Pawel Zarembski	0:01f31e923fe2	743	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
Pawel Zarembski	0:01f31e923fe2	744	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
Pawel Zarembski	0:01f31e923fe2	745	} DAC_Type;
Pawel Zarembski	0:01f31e923fe2	746
Pawel Zarembski	0:01f31e923fe2	747	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	748	-- DAC Register Masks
Pawel Zarembski	0:01f31e923fe2	749	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	750
Pawel Zarembski	0:01f31e923fe2	751	/*!
Pawel Zarembski	0:01f31e923fe2	752	* @addtogroup DAC_Register_Masks DAC Register Masks
Pawel Zarembski	0:01f31e923fe2	753	* @{
Pawel Zarembski	0:01f31e923fe2	754	*/
Pawel Zarembski	0:01f31e923fe2	755
Pawel Zarembski	0:01f31e923fe2	756	/! @name DATL - DAC Data Low Register /
Pawel Zarembski	0:01f31e923fe2	757	#define DAC_DATL_DATA0_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	758	#define DAC_DATL_DATA0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	759	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
Pawel Zarembski	0:01f31e923fe2	760
Pawel Zarembski	0:01f31e923fe2	761	/* The count of DAC_DATL */
Pawel Zarembski	0:01f31e923fe2	762	#define DAC_DATL_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	763
Pawel Zarembski	0:01f31e923fe2	764	/! @name DATH - DAC Data High Register /
Pawel Zarembski	0:01f31e923fe2	765	#define DAC_DATH_DATA1_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	766	#define DAC_DATH_DATA1_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	767	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
Pawel Zarembski	0:01f31e923fe2	768
Pawel Zarembski	0:01f31e923fe2	769	/* The count of DAC_DATH */
Pawel Zarembski	0:01f31e923fe2	770	#define DAC_DATH_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	771
Pawel Zarembski	0:01f31e923fe2	772	/! @name SR - DAC Status Register /
Pawel Zarembski	0:01f31e923fe2	773	#define DAC_SR_DACBFRPBF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	774	#define DAC_SR_DACBFRPBF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	775	#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
Pawel Zarembski	0:01f31e923fe2	776	#define DAC_SR_DACBFRPTF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	777	#define DAC_SR_DACBFRPTF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	778	#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
Pawel Zarembski	0:01f31e923fe2	779
Pawel Zarembski	0:01f31e923fe2	780	/! @name C0 - DAC Control Register /
Pawel Zarembski	0:01f31e923fe2	781	#define DAC_C0_DACBBIEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	782	#define DAC_C0_DACBBIEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	783	#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	784	#define DAC_C0_DACBTIEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	785	#define DAC_C0_DACBTIEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	786	#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	787	#define DAC_C0_LPEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	788	#define DAC_C0_LPEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	789	#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	790	#define DAC_C0_DACSWTRG_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	791	#define DAC_C0_DACSWTRG_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	792	#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
Pawel Zarembski	0:01f31e923fe2	793	#define DAC_C0_DACTRGSEL_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	794	#define DAC_C0_DACTRGSEL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	795	#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	796	#define DAC_C0_DACRFS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	797	#define DAC_C0_DACRFS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	798	#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
Pawel Zarembski	0:01f31e923fe2	799	#define DAC_C0_DACEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	800	#define DAC_C0_DACEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	801	#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
Pawel Zarembski	0:01f31e923fe2	802
Pawel Zarembski	0:01f31e923fe2	803	/! @name C1 - DAC Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	804	#define DAC_C1_DACBFEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	805	#define DAC_C1_DACBFEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	806	#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	807	#define DAC_C1_DACBFMD_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	808	#define DAC_C1_DACBFMD_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	809	#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
Pawel Zarembski	0:01f31e923fe2	810	#define DAC_C1_DMAEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	811	#define DAC_C1_DMAEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	812	#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	813
Pawel Zarembski	0:01f31e923fe2	814	/! @name C2 - DAC Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	815	#define DAC_C2_DACBFUP_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	816	#define DAC_C2_DACBFUP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	817	#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
Pawel Zarembski	0:01f31e923fe2	818	#define DAC_C2_DACBFRP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	819	#define DAC_C2_DACBFRP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	820	#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
Pawel Zarembski	0:01f31e923fe2	821
Pawel Zarembski	0:01f31e923fe2	822
Pawel Zarembski	0:01f31e923fe2	823	/*!
Pawel Zarembski	0:01f31e923fe2	824	* @}
Pawel Zarembski	0:01f31e923fe2	825	/ / end of group DAC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	826
Pawel Zarembski	0:01f31e923fe2	827
Pawel Zarembski	0:01f31e923fe2	828	/* DAC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	829	/** Peripheral DAC0 base address */
Pawel Zarembski	0:01f31e923fe2	830	#define DAC0_BASE (0x4003F000u)
Pawel Zarembski	0:01f31e923fe2	831	/** Peripheral DAC0 base pointer */
Pawel Zarembski	0:01f31e923fe2	832	#define DAC0 ((DAC_Type *)DAC0_BASE)
Pawel Zarembski	0:01f31e923fe2	833	/** Array initializer of DAC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	834	#define DAC_BASE_ADDRS { DAC0_BASE }
Pawel Zarembski	0:01f31e923fe2	835	/** Array initializer of DAC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	836	#define DAC_BASE_PTRS { DAC0 }
Pawel Zarembski	0:01f31e923fe2	837	/** Interrupt vectors for the DAC peripheral type */
Pawel Zarembski	0:01f31e923fe2	838	#define DAC_IRQS { DAC0_IRQn }
Pawel Zarembski	0:01f31e923fe2	839
Pawel Zarembski	0:01f31e923fe2	840	/*!
Pawel Zarembski	0:01f31e923fe2	841	* @}
Pawel Zarembski	0:01f31e923fe2	842	/ / end of group DAC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	843
Pawel Zarembski	0:01f31e923fe2	844
Pawel Zarembski	0:01f31e923fe2	845	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	846	-- DMA Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	847	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	848
Pawel Zarembski	0:01f31e923fe2	849	/*!
Pawel Zarembski	0:01f31e923fe2	850	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	851	* @{
Pawel Zarembski	0:01f31e923fe2	852	*/
Pawel Zarembski	0:01f31e923fe2	853
Pawel Zarembski	0:01f31e923fe2	854	/** DMA - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	855	typedef struct {
Pawel Zarembski	0:01f31e923fe2	856	uint8_t RESERVED_0[256];
Pawel Zarembski	0:01f31e923fe2	857	struct { /* offset: 0x100, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	858	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	859	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	860	union { /* offset: 0x108, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	861	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	862	struct { /* offset: 0x108, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	863	uint8_t RESERVED_0[3];
Pawel Zarembski	0:01f31e923fe2	864	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	865	} DMA_DSR_ACCESS8BIT;
Pawel Zarembski	0:01f31e923fe2	866	};
Pawel Zarembski	0:01f31e923fe2	867	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	868	} DMA[4];
Pawel Zarembski	0:01f31e923fe2	869	} DMA_Type;
Pawel Zarembski	0:01f31e923fe2	870
Pawel Zarembski	0:01f31e923fe2	871	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	872	-- DMA Register Masks
Pawel Zarembski	0:01f31e923fe2	873	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	874
Pawel Zarembski	0:01f31e923fe2	875	/*!
Pawel Zarembski	0:01f31e923fe2	876	* @addtogroup DMA_Register_Masks DMA Register Masks
Pawel Zarembski	0:01f31e923fe2	877	* @{
Pawel Zarembski	0:01f31e923fe2	878	*/
Pawel Zarembski	0:01f31e923fe2	879
Pawel Zarembski	0:01f31e923fe2	880	/! @name SAR - Source Address Register /
Pawel Zarembski	0:01f31e923fe2	881	#define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	882	#define DMA_SAR_SAR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	883	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
Pawel Zarembski	0:01f31e923fe2	884
Pawel Zarembski	0:01f31e923fe2	885	/* The count of DMA_SAR */
Pawel Zarembski	0:01f31e923fe2	886	#define DMA_SAR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	887
Pawel Zarembski	0:01f31e923fe2	888	/! @name DAR - Destination Address Register /
Pawel Zarembski	0:01f31e923fe2	889	#define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	890	#define DMA_DAR_DAR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	891	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
Pawel Zarembski	0:01f31e923fe2	892
Pawel Zarembski	0:01f31e923fe2	893	/* The count of DMA_DAR */
Pawel Zarembski	0:01f31e923fe2	894	#define DMA_DAR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	895
Pawel Zarembski	0:01f31e923fe2	896	/! @name DSR_BCR - DMA Status Register / Byte Count Register /
Pawel Zarembski	0:01f31e923fe2	897	#define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	898	#define DMA_DSR_BCR_BCR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	899	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
Pawel Zarembski	0:01f31e923fe2	900	#define DMA_DSR_BCR_DONE_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	901	#define DMA_DSR_BCR_DONE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	902	#define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
Pawel Zarembski	0:01f31e923fe2	903	#define DMA_DSR_BCR_BSY_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	904	#define DMA_DSR_BCR_BSY_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	905	#define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
Pawel Zarembski	0:01f31e923fe2	906	#define DMA_DSR_BCR_REQ_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	907	#define DMA_DSR_BCR_REQ_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	908	#define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
Pawel Zarembski	0:01f31e923fe2	909	#define DMA_DSR_BCR_BED_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	910	#define DMA_DSR_BCR_BED_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	911	#define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
Pawel Zarembski	0:01f31e923fe2	912	#define DMA_DSR_BCR_BES_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	913	#define DMA_DSR_BCR_BES_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	914	#define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
Pawel Zarembski	0:01f31e923fe2	915	#define DMA_DSR_BCR_CE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	916	#define DMA_DSR_BCR_CE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	917	#define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
Pawel Zarembski	0:01f31e923fe2	918
Pawel Zarembski	0:01f31e923fe2	919	/* The count of DMA_DSR_BCR */
Pawel Zarembski	0:01f31e923fe2	920	#define DMA_DSR_BCR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	921
Pawel Zarembski	0:01f31e923fe2	922	/* The count of DMA_DSR */
Pawel Zarembski	0:01f31e923fe2	923	#define DMA_DSR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	924
Pawel Zarembski	0:01f31e923fe2	925	/! @name DCR - DMA Control Register /
Pawel Zarembski	0:01f31e923fe2	926	#define DMA_DCR_LCH2_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	927	#define DMA_DCR_LCH2_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	928	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
Pawel Zarembski	0:01f31e923fe2	929	#define DMA_DCR_LCH1_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	930	#define DMA_DCR_LCH1_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	931	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
Pawel Zarembski	0:01f31e923fe2	932	#define DMA_DCR_LINKCC_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	933	#define DMA_DCR_LINKCC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	934	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
Pawel Zarembski	0:01f31e923fe2	935	#define DMA_DCR_D_REQ_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	936	#define DMA_DCR_D_REQ_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	937	#define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
Pawel Zarembski	0:01f31e923fe2	938	#define DMA_DCR_DMOD_MASK (0xF00U)
Pawel Zarembski	0:01f31e923fe2	939	#define DMA_DCR_DMOD_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	940	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	941	#define DMA_DCR_SMOD_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	942	#define DMA_DCR_SMOD_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	943	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	944	#define DMA_DCR_START_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	945	#define DMA_DCR_START_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	946	#define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
Pawel Zarembski	0:01f31e923fe2	947	#define DMA_DCR_DSIZE_MASK (0x60000U)
Pawel Zarembski	0:01f31e923fe2	948	#define DMA_DCR_DSIZE_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	949	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	950	#define DMA_DCR_DINC_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	951	#define DMA_DCR_DINC_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	952	#define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
Pawel Zarembski	0:01f31e923fe2	953	#define DMA_DCR_SSIZE_MASK (0x300000U)
Pawel Zarembski	0:01f31e923fe2	954	#define DMA_DCR_SSIZE_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	955	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	956	#define DMA_DCR_SINC_MASK (0x400000U)
Pawel Zarembski	0:01f31e923fe2	957	#define DMA_DCR_SINC_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	958	#define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
Pawel Zarembski	0:01f31e923fe2	959	#define DMA_DCR_EADREQ_MASK (0x800000U)
Pawel Zarembski	0:01f31e923fe2	960	#define DMA_DCR_EADREQ_SHIFT (23U)
Pawel Zarembski	0:01f31e923fe2	961	#define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
Pawel Zarembski	0:01f31e923fe2	962	#define DMA_DCR_AA_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	963	#define DMA_DCR_AA_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	964	#define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
Pawel Zarembski	0:01f31e923fe2	965	#define DMA_DCR_CS_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	966	#define DMA_DCR_CS_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	967	#define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
Pawel Zarembski	0:01f31e923fe2	968	#define DMA_DCR_ERQ_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	969	#define DMA_DCR_ERQ_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	970	#define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
Pawel Zarembski	0:01f31e923fe2	971	#define DMA_DCR_EINT_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	972	#define DMA_DCR_EINT_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	973	#define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
Pawel Zarembski	0:01f31e923fe2	974
Pawel Zarembski	0:01f31e923fe2	975	/* The count of DMA_DCR */
Pawel Zarembski	0:01f31e923fe2	976	#define DMA_DCR_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	977
Pawel Zarembski	0:01f31e923fe2	978
Pawel Zarembski	0:01f31e923fe2	979	/*!
Pawel Zarembski	0:01f31e923fe2	980	* @}
Pawel Zarembski	0:01f31e923fe2	981	/ / end of group DMA_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	982
Pawel Zarembski	0:01f31e923fe2	983
Pawel Zarembski	0:01f31e923fe2	984	/* DMA - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	985	/** Peripheral DMA base address */
Pawel Zarembski	0:01f31e923fe2	986	#define DMA_BASE (0x40008000u)
Pawel Zarembski	0:01f31e923fe2	987	/** Peripheral DMA base pointer */
Pawel Zarembski	0:01f31e923fe2	988	#define DMA0 ((DMA_Type *)DMA_BASE)
Pawel Zarembski	0:01f31e923fe2	989	/** Array initializer of DMA peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	990	#define DMA_BASE_ADDRS { DMA_BASE }
Pawel Zarembski	0:01f31e923fe2	991	/** Array initializer of DMA peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	992	#define DMA_BASE_PTRS { DMA0 }
Pawel Zarembski	0:01f31e923fe2	993	/** Interrupt vectors for the DMA peripheral type */
Pawel Zarembski	0:01f31e923fe2	994	#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
Pawel Zarembski	0:01f31e923fe2	995
Pawel Zarembski	0:01f31e923fe2	996	/*!
Pawel Zarembski	0:01f31e923fe2	997	* @}
Pawel Zarembski	0:01f31e923fe2	998	/ / end of group DMA_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	999
Pawel Zarembski	0:01f31e923fe2	1000
Pawel Zarembski	0:01f31e923fe2	1001	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1002	-- DMAMUX Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1003	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1004
Pawel Zarembski	0:01f31e923fe2	1005	/*!
Pawel Zarembski	0:01f31e923fe2	1006	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1007	* @{
Pawel Zarembski	0:01f31e923fe2	1008	*/
Pawel Zarembski	0:01f31e923fe2	1009
Pawel Zarembski	0:01f31e923fe2	1010	/** DMAMUX - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1011	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1012	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
Pawel Zarembski	0:01f31e923fe2	1013	} DMAMUX_Type;
Pawel Zarembski	0:01f31e923fe2	1014
Pawel Zarembski	0:01f31e923fe2	1015	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1016	-- DMAMUX Register Masks
Pawel Zarembski	0:01f31e923fe2	1017	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1018
Pawel Zarembski	0:01f31e923fe2	1019	/*!
Pawel Zarembski	0:01f31e923fe2	1020	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Pawel Zarembski	0:01f31e923fe2	1021	* @{
Pawel Zarembski	0:01f31e923fe2	1022	*/
Pawel Zarembski	0:01f31e923fe2	1023
Pawel Zarembski	0:01f31e923fe2	1024	/! @name CHCFG - Channel Configuration register /
Pawel Zarembski	0:01f31e923fe2	1025	#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	1026	#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1027	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1028	#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1029	#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1030	#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
Pawel Zarembski	0:01f31e923fe2	1031	#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1032	#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1033	#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
Pawel Zarembski	0:01f31e923fe2	1034
Pawel Zarembski	0:01f31e923fe2	1035	/* The count of DMAMUX_CHCFG */
Pawel Zarembski	0:01f31e923fe2	1036	#define DMAMUX_CHCFG_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	1037
Pawel Zarembski	0:01f31e923fe2	1038
Pawel Zarembski	0:01f31e923fe2	1039	/*!
Pawel Zarembski	0:01f31e923fe2	1040	* @}
Pawel Zarembski	0:01f31e923fe2	1041	/ / end of group DMAMUX_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1042
Pawel Zarembski	0:01f31e923fe2	1043
Pawel Zarembski	0:01f31e923fe2	1044	/* DMAMUX - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1045	/** Peripheral DMAMUX0 base address */
Pawel Zarembski	0:01f31e923fe2	1046	#define DMAMUX0_BASE (0x40021000u)
Pawel Zarembski	0:01f31e923fe2	1047	/** Peripheral DMAMUX0 base pointer */
Pawel Zarembski	0:01f31e923fe2	1048	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
Pawel Zarembski	0:01f31e923fe2	1049	/** Array initializer of DMAMUX peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1050	#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
Pawel Zarembski	0:01f31e923fe2	1051	/** Array initializer of DMAMUX peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1052	#define DMAMUX_BASE_PTRS { DMAMUX0 }
Pawel Zarembski	0:01f31e923fe2	1053
Pawel Zarembski	0:01f31e923fe2	1054	/*!
Pawel Zarembski	0:01f31e923fe2	1055	* @}
Pawel Zarembski	0:01f31e923fe2	1056	/ / end of group DMAMUX_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1057
Pawel Zarembski	0:01f31e923fe2	1058
Pawel Zarembski	0:01f31e923fe2	1059	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1060	-- FGPIO Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1061	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1062
Pawel Zarembski	0:01f31e923fe2	1063	/*!
Pawel Zarembski	0:01f31e923fe2	1064	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1065	* @{
Pawel Zarembski	0:01f31e923fe2	1066	*/
Pawel Zarembski	0:01f31e923fe2	1067
Pawel Zarembski	0:01f31e923fe2	1068	/** FGPIO - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1069	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1070	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1071	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1072	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1073	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	1074	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	1075	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	1076	} FGPIO_Type;
Pawel Zarembski	0:01f31e923fe2	1077
Pawel Zarembski	0:01f31e923fe2	1078	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1079	-- FGPIO Register Masks
Pawel Zarembski	0:01f31e923fe2	1080	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1081
Pawel Zarembski	0:01f31e923fe2	1082	/*!
Pawel Zarembski	0:01f31e923fe2	1083	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
Pawel Zarembski	0:01f31e923fe2	1084	* @{
Pawel Zarembski	0:01f31e923fe2	1085	*/
Pawel Zarembski	0:01f31e923fe2	1086
Pawel Zarembski	0:01f31e923fe2	1087	/! @name PDOR - Port Data Output Register /
Pawel Zarembski	0:01f31e923fe2	1088	#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1089	#define FGPIO_PDOR_PDO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1090	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
Pawel Zarembski	0:01f31e923fe2	1091
Pawel Zarembski	0:01f31e923fe2	1092	/! @name PSOR - Port Set Output Register /
Pawel Zarembski	0:01f31e923fe2	1093	#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1094	#define FGPIO_PSOR_PTSO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1095	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
Pawel Zarembski	0:01f31e923fe2	1096
Pawel Zarembski	0:01f31e923fe2	1097	/! @name PCOR - Port Clear Output Register /
Pawel Zarembski	0:01f31e923fe2	1098	#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1099	#define FGPIO_PCOR_PTCO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1100	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
Pawel Zarembski	0:01f31e923fe2	1101
Pawel Zarembski	0:01f31e923fe2	1102	/! @name PTOR - Port Toggle Output Register /
Pawel Zarembski	0:01f31e923fe2	1103	#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1104	#define FGPIO_PTOR_PTTO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1105	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
Pawel Zarembski	0:01f31e923fe2	1106
Pawel Zarembski	0:01f31e923fe2	1107	/! @name PDIR - Port Data Input Register /
Pawel Zarembski	0:01f31e923fe2	1108	#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1109	#define FGPIO_PDIR_PDI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1110	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
Pawel Zarembski	0:01f31e923fe2	1111
Pawel Zarembski	0:01f31e923fe2	1112	/! @name PDDR - Port Data Direction Register /
Pawel Zarembski	0:01f31e923fe2	1113	#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1114	#define FGPIO_PDDR_PDD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1115	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
Pawel Zarembski	0:01f31e923fe2	1116
Pawel Zarembski	0:01f31e923fe2	1117
Pawel Zarembski	0:01f31e923fe2	1118	/*!
Pawel Zarembski	0:01f31e923fe2	1119	* @}
Pawel Zarembski	0:01f31e923fe2	1120	/ / end of group FGPIO_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1121
Pawel Zarembski	0:01f31e923fe2	1122
Pawel Zarembski	0:01f31e923fe2	1123	/* FGPIO - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1124	/** Peripheral FGPIOA base address */
Pawel Zarembski	0:01f31e923fe2	1125	#define FGPIOA_BASE (0xF8000000u)
Pawel Zarembski	0:01f31e923fe2	1126	/** Peripheral FGPIOA base pointer */
Pawel Zarembski	0:01f31e923fe2	1127	#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
Pawel Zarembski	0:01f31e923fe2	1128	/** Peripheral FGPIOB base address */
Pawel Zarembski	0:01f31e923fe2	1129	#define FGPIOB_BASE (0xF8000040u)
Pawel Zarembski	0:01f31e923fe2	1130	/** Peripheral FGPIOB base pointer */
Pawel Zarembski	0:01f31e923fe2	1131	#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
Pawel Zarembski	0:01f31e923fe2	1132	/** Peripheral FGPIOC base address */
Pawel Zarembski	0:01f31e923fe2	1133	#define FGPIOC_BASE (0xF8000080u)
Pawel Zarembski	0:01f31e923fe2	1134	/** Peripheral FGPIOC base pointer */
Pawel Zarembski	0:01f31e923fe2	1135	#define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
Pawel Zarembski	0:01f31e923fe2	1136	/** Peripheral FGPIOD base address */
Pawel Zarembski	0:01f31e923fe2	1137	#define FGPIOD_BASE (0xF80000C0u)
Pawel Zarembski	0:01f31e923fe2	1138	/** Peripheral FGPIOD base pointer */
Pawel Zarembski	0:01f31e923fe2	1139	#define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
Pawel Zarembski	0:01f31e923fe2	1140	/** Peripheral FGPIOE base address */
Pawel Zarembski	0:01f31e923fe2	1141	#define FGPIOE_BASE (0xF8000100u)
Pawel Zarembski	0:01f31e923fe2	1142	/** Peripheral FGPIOE base pointer */
Pawel Zarembski	0:01f31e923fe2	1143	#define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
Pawel Zarembski	0:01f31e923fe2	1144	/** Array initializer of FGPIO peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1145	#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
Pawel Zarembski	0:01f31e923fe2	1146	/** Array initializer of FGPIO peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1147	#define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
Pawel Zarembski	0:01f31e923fe2	1148
Pawel Zarembski	0:01f31e923fe2	1149	/*!
Pawel Zarembski	0:01f31e923fe2	1150	* @}
Pawel Zarembski	0:01f31e923fe2	1151	/ / end of group FGPIO_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1152
Pawel Zarembski	0:01f31e923fe2	1153
Pawel Zarembski	0:01f31e923fe2	1154	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1155	-- FTFA Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1156	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1157
Pawel Zarembski	0:01f31e923fe2	1158	/*!
Pawel Zarembski	0:01f31e923fe2	1159	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1160	* @{
Pawel Zarembski	0:01f31e923fe2	1161	*/
Pawel Zarembski	0:01f31e923fe2	1162
Pawel Zarembski	0:01f31e923fe2	1163	/** FTFA - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1164	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1165	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1166	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	1167	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	1168	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	1169	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1170	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	1171	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	1172	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	1173	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1174	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	1175	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	1176	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	1177	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	1178	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	1179	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
Pawel Zarembski	0:01f31e923fe2	1180	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
Pawel Zarembski	0:01f31e923fe2	1181	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	1182	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
Pawel Zarembski	0:01f31e923fe2	1183	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
Pawel Zarembski	0:01f31e923fe2	1184	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
Pawel Zarembski	0:01f31e923fe2	1185	} FTFA_Type;
Pawel Zarembski	0:01f31e923fe2	1186
Pawel Zarembski	0:01f31e923fe2	1187	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1188	-- FTFA Register Masks
Pawel Zarembski	0:01f31e923fe2	1189	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1190
Pawel Zarembski	0:01f31e923fe2	1191	/*!
Pawel Zarembski	0:01f31e923fe2	1192	* @addtogroup FTFA_Register_Masks FTFA Register Masks
Pawel Zarembski	0:01f31e923fe2	1193	* @{
Pawel Zarembski	0:01f31e923fe2	1194	*/
Pawel Zarembski	0:01f31e923fe2	1195
Pawel Zarembski	0:01f31e923fe2	1196	/! @name FSTAT - Flash Status Register /
Pawel Zarembski	0:01f31e923fe2	1197	#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1198	#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1199	#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
Pawel Zarembski	0:01f31e923fe2	1200	#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1201	#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1202	#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
Pawel Zarembski	0:01f31e923fe2	1203	#define FTFA_FSTAT_ACCERR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1204	#define FTFA_FSTAT_ACCERR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1205	#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
Pawel Zarembski	0:01f31e923fe2	1206	#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1207	#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1208	#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
Pawel Zarembski	0:01f31e923fe2	1209	#define FTFA_FSTAT_CCIF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1210	#define FTFA_FSTAT_CCIF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1211	#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
Pawel Zarembski	0:01f31e923fe2	1212
Pawel Zarembski	0:01f31e923fe2	1213	/! @name FCNFG - Flash Configuration Register /
Pawel Zarembski	0:01f31e923fe2	1214	#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1215	#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1216	#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
Pawel Zarembski	0:01f31e923fe2	1217	#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1218	#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1219	#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
Pawel Zarembski	0:01f31e923fe2	1220	#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1221	#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1222	#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1223	#define FTFA_FCNFG_CCIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1224	#define FTFA_FCNFG_CCIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1225	#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1226
Pawel Zarembski	0:01f31e923fe2	1227	/! @name FSEC - Flash Security Register /
Pawel Zarembski	0:01f31e923fe2	1228	#define FTFA_FSEC_SEC_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	1229	#define FTFA_FSEC_SEC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1230	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
Pawel Zarembski	0:01f31e923fe2	1231	#define FTFA_FSEC_FSLACC_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	1232	#define FTFA_FSEC_FSLACC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1233	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
Pawel Zarembski	0:01f31e923fe2	1234	#define FTFA_FSEC_MEEN_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	1235	#define FTFA_FSEC_MEEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1236	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1237	#define FTFA_FSEC_KEYEN_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	1238	#define FTFA_FSEC_KEYEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1239	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1240
Pawel Zarembski	0:01f31e923fe2	1241	/! @name FOPT - Flash Option Register /
Pawel Zarembski	0:01f31e923fe2	1242	#define FTFA_FOPT_OPT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1243	#define FTFA_FOPT_OPT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1244	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
Pawel Zarembski	0:01f31e923fe2	1245
Pawel Zarembski	0:01f31e923fe2	1246	/! @name FCCOB3 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1247	#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1248	#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1249	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1250
Pawel Zarembski	0:01f31e923fe2	1251	/! @name FCCOB2 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1252	#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1253	#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1254	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1255
Pawel Zarembski	0:01f31e923fe2	1256	/! @name FCCOB1 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1257	#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1258	#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1259	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1260
Pawel Zarembski	0:01f31e923fe2	1261	/! @name FCCOB0 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1262	#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1263	#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1264	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1265
Pawel Zarembski	0:01f31e923fe2	1266	/! @name FCCOB7 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1267	#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1268	#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1269	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1270
Pawel Zarembski	0:01f31e923fe2	1271	/! @name FCCOB6 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1272	#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1273	#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1274	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1275
Pawel Zarembski	0:01f31e923fe2	1276	/! @name FCCOB5 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1277	#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1278	#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1279	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1280
Pawel Zarembski	0:01f31e923fe2	1281	/! @name FCCOB4 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1282	#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1283	#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1284	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1285
Pawel Zarembski	0:01f31e923fe2	1286	/! @name FCCOBB - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1287	#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1288	#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1289	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1290
Pawel Zarembski	0:01f31e923fe2	1291	/! @name FCCOBA - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1292	#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1293	#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1294	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1295
Pawel Zarembski	0:01f31e923fe2	1296	/! @name FCCOB9 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1297	#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1298	#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1299	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1300
Pawel Zarembski	0:01f31e923fe2	1301	/! @name FCCOB8 - Flash Common Command Object Registers /
Pawel Zarembski	0:01f31e923fe2	1302	#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1303	#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1304	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
Pawel Zarembski	0:01f31e923fe2	1305
Pawel Zarembski	0:01f31e923fe2	1306	/! @name FPROT3 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	1307	#define FTFA_FPROT3_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1308	#define FTFA_FPROT3_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1309	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	1310
Pawel Zarembski	0:01f31e923fe2	1311	/! @name FPROT2 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	1312	#define FTFA_FPROT2_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1313	#define FTFA_FPROT2_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1314	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	1315
Pawel Zarembski	0:01f31e923fe2	1316	/! @name FPROT1 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	1317	#define FTFA_FPROT1_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1318	#define FTFA_FPROT1_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1319	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	1320
Pawel Zarembski	0:01f31e923fe2	1321	/! @name FPROT0 - Program Flash Protection Registers /
Pawel Zarembski	0:01f31e923fe2	1322	#define FTFA_FPROT0_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1323	#define FTFA_FPROT0_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1324	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	1325
Pawel Zarembski	0:01f31e923fe2	1326
Pawel Zarembski	0:01f31e923fe2	1327	/*!
Pawel Zarembski	0:01f31e923fe2	1328	* @}
Pawel Zarembski	0:01f31e923fe2	1329	/ / end of group FTFA_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1330
Pawel Zarembski	0:01f31e923fe2	1331
Pawel Zarembski	0:01f31e923fe2	1332	/* FTFA - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1333	/** Peripheral FTFA base address */
Pawel Zarembski	0:01f31e923fe2	1334	#define FTFA_BASE (0x40020000u)
Pawel Zarembski	0:01f31e923fe2	1335	/** Peripheral FTFA base pointer */
Pawel Zarembski	0:01f31e923fe2	1336	#define FTFA ((FTFA_Type *)FTFA_BASE)
Pawel Zarembski	0:01f31e923fe2	1337	/** Array initializer of FTFA peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1338	#define FTFA_BASE_ADDRS { FTFA_BASE }
Pawel Zarembski	0:01f31e923fe2	1339	/** Array initializer of FTFA peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1340	#define FTFA_BASE_PTRS { FTFA }
Pawel Zarembski	0:01f31e923fe2	1341	/** Interrupt vectors for the FTFA peripheral type */
Pawel Zarembski	0:01f31e923fe2	1342	#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
Pawel Zarembski	0:01f31e923fe2	1343
Pawel Zarembski	0:01f31e923fe2	1344	/*!
Pawel Zarembski	0:01f31e923fe2	1345	* @}
Pawel Zarembski	0:01f31e923fe2	1346	/ / end of group FTFA_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1347
Pawel Zarembski	0:01f31e923fe2	1348
Pawel Zarembski	0:01f31e923fe2	1349	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1350	-- GPIO Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1351	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1352
Pawel Zarembski	0:01f31e923fe2	1353	/*!
Pawel Zarembski	0:01f31e923fe2	1354	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1355	* @{
Pawel Zarembski	0:01f31e923fe2	1356	*/
Pawel Zarembski	0:01f31e923fe2	1357
Pawel Zarembski	0:01f31e923fe2	1358	/** GPIO - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1359	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1360	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1361	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1362	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1363	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	1364	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	1365	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	1366	} GPIO_Type;
Pawel Zarembski	0:01f31e923fe2	1367
Pawel Zarembski	0:01f31e923fe2	1368	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1369	-- GPIO Register Masks
Pawel Zarembski	0:01f31e923fe2	1370	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1371
Pawel Zarembski	0:01f31e923fe2	1372	/*!
Pawel Zarembski	0:01f31e923fe2	1373	* @addtogroup GPIO_Register_Masks GPIO Register Masks
Pawel Zarembski	0:01f31e923fe2	1374	* @{
Pawel Zarembski	0:01f31e923fe2	1375	*/
Pawel Zarembski	0:01f31e923fe2	1376
Pawel Zarembski	0:01f31e923fe2	1377	/! @name PDOR - Port Data Output Register /
Pawel Zarembski	0:01f31e923fe2	1378	#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1379	#define GPIO_PDOR_PDO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1380	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
Pawel Zarembski	0:01f31e923fe2	1381
Pawel Zarembski	0:01f31e923fe2	1382	/! @name PSOR - Port Set Output Register /
Pawel Zarembski	0:01f31e923fe2	1383	#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1384	#define GPIO_PSOR_PTSO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1385	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
Pawel Zarembski	0:01f31e923fe2	1386
Pawel Zarembski	0:01f31e923fe2	1387	/! @name PCOR - Port Clear Output Register /
Pawel Zarembski	0:01f31e923fe2	1388	#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1389	#define GPIO_PCOR_PTCO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1390	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
Pawel Zarembski	0:01f31e923fe2	1391
Pawel Zarembski	0:01f31e923fe2	1392	/! @name PTOR - Port Toggle Output Register /
Pawel Zarembski	0:01f31e923fe2	1393	#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1394	#define GPIO_PTOR_PTTO_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1395	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
Pawel Zarembski	0:01f31e923fe2	1396
Pawel Zarembski	0:01f31e923fe2	1397	/! @name PDIR - Port Data Input Register /
Pawel Zarembski	0:01f31e923fe2	1398	#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1399	#define GPIO_PDIR_PDI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1400	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
Pawel Zarembski	0:01f31e923fe2	1401
Pawel Zarembski	0:01f31e923fe2	1402	/! @name PDDR - Port Data Direction Register /
Pawel Zarembski	0:01f31e923fe2	1403	#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1404	#define GPIO_PDDR_PDD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1405	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
Pawel Zarembski	0:01f31e923fe2	1406
Pawel Zarembski	0:01f31e923fe2	1407
Pawel Zarembski	0:01f31e923fe2	1408	/*!
Pawel Zarembski	0:01f31e923fe2	1409	* @}
Pawel Zarembski	0:01f31e923fe2	1410	/ / end of group GPIO_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1411
Pawel Zarembski	0:01f31e923fe2	1412
Pawel Zarembski	0:01f31e923fe2	1413	/* GPIO - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1414	/** Peripheral GPIOA base address */
Pawel Zarembski	0:01f31e923fe2	1415	#define GPIOA_BASE (0x400FF000u)
Pawel Zarembski	0:01f31e923fe2	1416	/** Peripheral GPIOA base pointer */
Pawel Zarembski	0:01f31e923fe2	1417	#define GPIOA ((GPIO_Type *)GPIOA_BASE)
Pawel Zarembski	0:01f31e923fe2	1418	/** Peripheral GPIOB base address */
Pawel Zarembski	0:01f31e923fe2	1419	#define GPIOB_BASE (0x400FF040u)
Pawel Zarembski	0:01f31e923fe2	1420	/** Peripheral GPIOB base pointer */
Pawel Zarembski	0:01f31e923fe2	1421	#define GPIOB ((GPIO_Type *)GPIOB_BASE)
Pawel Zarembski	0:01f31e923fe2	1422	/** Peripheral GPIOC base address */
Pawel Zarembski	0:01f31e923fe2	1423	#define GPIOC_BASE (0x400FF080u)
Pawel Zarembski	0:01f31e923fe2	1424	/** Peripheral GPIOC base pointer */
Pawel Zarembski	0:01f31e923fe2	1425	#define GPIOC ((GPIO_Type *)GPIOC_BASE)
Pawel Zarembski	0:01f31e923fe2	1426	/** Peripheral GPIOD base address */
Pawel Zarembski	0:01f31e923fe2	1427	#define GPIOD_BASE (0x400FF0C0u)
Pawel Zarembski	0:01f31e923fe2	1428	/** Peripheral GPIOD base pointer */
Pawel Zarembski	0:01f31e923fe2	1429	#define GPIOD ((GPIO_Type *)GPIOD_BASE)
Pawel Zarembski	0:01f31e923fe2	1430	/** Peripheral GPIOE base address */
Pawel Zarembski	0:01f31e923fe2	1431	#define GPIOE_BASE (0x400FF100u)
Pawel Zarembski	0:01f31e923fe2	1432	/** Peripheral GPIOE base pointer */
Pawel Zarembski	0:01f31e923fe2	1433	#define GPIOE ((GPIO_Type *)GPIOE_BASE)
Pawel Zarembski	0:01f31e923fe2	1434	/** Array initializer of GPIO peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1435	#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
Pawel Zarembski	0:01f31e923fe2	1436	/** Array initializer of GPIO peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1437	#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
Pawel Zarembski	0:01f31e923fe2	1438
Pawel Zarembski	0:01f31e923fe2	1439	/*!
Pawel Zarembski	0:01f31e923fe2	1440	* @}
Pawel Zarembski	0:01f31e923fe2	1441	/ / end of group GPIO_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1442
Pawel Zarembski	0:01f31e923fe2	1443
Pawel Zarembski	0:01f31e923fe2	1444	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1445	-- I2C Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1446	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1447
Pawel Zarembski	0:01f31e923fe2	1448	/*!
Pawel Zarembski	0:01f31e923fe2	1449	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1450	* @{
Pawel Zarembski	0:01f31e923fe2	1451	*/
Pawel Zarembski	0:01f31e923fe2	1452
Pawel Zarembski	0:01f31e923fe2	1453	/** I2C - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1454	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1455	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1456	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	1457	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	1458	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	1459	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1460	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	1461	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	1462	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	1463	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1464	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	1465	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	1466	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	1467	} I2C_Type;
Pawel Zarembski	0:01f31e923fe2	1468
Pawel Zarembski	0:01f31e923fe2	1469	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1470	-- I2C Register Masks
Pawel Zarembski	0:01f31e923fe2	1471	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1472
Pawel Zarembski	0:01f31e923fe2	1473	/*!
Pawel Zarembski	0:01f31e923fe2	1474	* @addtogroup I2C_Register_Masks I2C Register Masks
Pawel Zarembski	0:01f31e923fe2	1475	* @{
Pawel Zarembski	0:01f31e923fe2	1476	*/
Pawel Zarembski	0:01f31e923fe2	1477
Pawel Zarembski	0:01f31e923fe2	1478	/! @name A1 - I2C Address Register 1 /
Pawel Zarembski	0:01f31e923fe2	1479	#define I2C_A1_AD_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	1480	#define I2C_A1_AD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1481	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
Pawel Zarembski	0:01f31e923fe2	1482
Pawel Zarembski	0:01f31e923fe2	1483	/! @name F - I2C Frequency Divider register /
Pawel Zarembski	0:01f31e923fe2	1484	#define I2C_F_ICR_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	1485	#define I2C_F_ICR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1486	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
Pawel Zarembski	0:01f31e923fe2	1487	#define I2C_F_MULT_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	1488	#define I2C_F_MULT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1489	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
Pawel Zarembski	0:01f31e923fe2	1490
Pawel Zarembski	0:01f31e923fe2	1491	/! @name C1 - I2C Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	1492	#define I2C_C1_DMAEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1493	#define I2C_C1_DMAEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1494	#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1495	#define I2C_C1_WUEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1496	#define I2C_C1_WUEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1497	#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1498	#define I2C_C1_RSTA_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1499	#define I2C_C1_RSTA_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1500	#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
Pawel Zarembski	0:01f31e923fe2	1501	#define I2C_C1_TXAK_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1502	#define I2C_C1_TXAK_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1503	#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
Pawel Zarembski	0:01f31e923fe2	1504	#define I2C_C1_TX_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1505	#define I2C_C1_TX_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1506	#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
Pawel Zarembski	0:01f31e923fe2	1507	#define I2C_C1_MST_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1508	#define I2C_C1_MST_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1509	#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
Pawel Zarembski	0:01f31e923fe2	1510	#define I2C_C1_IICIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1511	#define I2C_C1_IICIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1512	#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1513	#define I2C_C1_IICEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1514	#define I2C_C1_IICEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1515	#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1516
Pawel Zarembski	0:01f31e923fe2	1517	/! @name S - I2C Status register /
Pawel Zarembski	0:01f31e923fe2	1518	#define I2C_S_RXAK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1519	#define I2C_S_RXAK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1520	#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
Pawel Zarembski	0:01f31e923fe2	1521	#define I2C_S_IICIF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1522	#define I2C_S_IICIF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1523	#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
Pawel Zarembski	0:01f31e923fe2	1524	#define I2C_S_SRW_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1525	#define I2C_S_SRW_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1526	#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
Pawel Zarembski	0:01f31e923fe2	1527	#define I2C_S_RAM_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1528	#define I2C_S_RAM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1529	#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
Pawel Zarembski	0:01f31e923fe2	1530	#define I2C_S_ARBL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1531	#define I2C_S_ARBL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1532	#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
Pawel Zarembski	0:01f31e923fe2	1533	#define I2C_S_BUSY_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1534	#define I2C_S_BUSY_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1535	#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
Pawel Zarembski	0:01f31e923fe2	1536	#define I2C_S_IAAS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1537	#define I2C_S_IAAS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1538	#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
Pawel Zarembski	0:01f31e923fe2	1539	#define I2C_S_TCF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1540	#define I2C_S_TCF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1541	#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
Pawel Zarembski	0:01f31e923fe2	1542
Pawel Zarembski	0:01f31e923fe2	1543	/! @name D - I2C Data I/O register /
Pawel Zarembski	0:01f31e923fe2	1544	#define I2C_D_DATA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1545	#define I2C_D_DATA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1546	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
Pawel Zarembski	0:01f31e923fe2	1547
Pawel Zarembski	0:01f31e923fe2	1548	/! @name C2 - I2C Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	1549	#define I2C_C2_AD_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	1550	#define I2C_C2_AD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1551	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
Pawel Zarembski	0:01f31e923fe2	1552	#define I2C_C2_RMEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1553	#define I2C_C2_RMEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1554	#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1555	#define I2C_C2_SBRC_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1556	#define I2C_C2_SBRC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1557	#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
Pawel Zarembski	0:01f31e923fe2	1558	#define I2C_C2_HDRS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1559	#define I2C_C2_HDRS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1560	#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
Pawel Zarembski	0:01f31e923fe2	1561	#define I2C_C2_ADEXT_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1562	#define I2C_C2_ADEXT_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1563	#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
Pawel Zarembski	0:01f31e923fe2	1564	#define I2C_C2_GCAEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1565	#define I2C_C2_GCAEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1566	#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1567
Pawel Zarembski	0:01f31e923fe2	1568	/! @name FLT - I2C Programmable Input Glitch Filter register /
Pawel Zarembski	0:01f31e923fe2	1569	#define I2C_FLT_FLT_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	1570	#define I2C_FLT_FLT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1571	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
Pawel Zarembski	0:01f31e923fe2	1572	#define I2C_FLT_STARTF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1573	#define I2C_FLT_STARTF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1574	#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
Pawel Zarembski	0:01f31e923fe2	1575	#define I2C_FLT_SSIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1576	#define I2C_FLT_SSIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1577	#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1578	#define I2C_FLT_STOPF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1579	#define I2C_FLT_STOPF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1580	#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
Pawel Zarembski	0:01f31e923fe2	1581	#define I2C_FLT_SHEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1582	#define I2C_FLT_SHEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1583	#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1584
Pawel Zarembski	0:01f31e923fe2	1585	/! @name RA - I2C Range Address register /
Pawel Zarembski	0:01f31e923fe2	1586	#define I2C_RA_RAD_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	1587	#define I2C_RA_RAD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1588	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
Pawel Zarembski	0:01f31e923fe2	1589
Pawel Zarembski	0:01f31e923fe2	1590	/! @name SMB - I2C SMBus Control and Status register /
Pawel Zarembski	0:01f31e923fe2	1591	#define I2C_SMB_SHTF2IE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1592	#define I2C_SMB_SHTF2IE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1593	#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
Pawel Zarembski	0:01f31e923fe2	1594	#define I2C_SMB_SHTF2_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1595	#define I2C_SMB_SHTF2_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1596	#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
Pawel Zarembski	0:01f31e923fe2	1597	#define I2C_SMB_SHTF1_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	1598	#define I2C_SMB_SHTF1_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	1599	#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
Pawel Zarembski	0:01f31e923fe2	1600	#define I2C_SMB_SLTF_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1601	#define I2C_SMB_SLTF_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1602	#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
Pawel Zarembski	0:01f31e923fe2	1603	#define I2C_SMB_TCKSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1604	#define I2C_SMB_TCKSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1605	#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	1606	#define I2C_SMB_SIICAEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	1607	#define I2C_SMB_SIICAEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	1608	#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1609	#define I2C_SMB_ALERTEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	1610	#define I2C_SMB_ALERTEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	1611	#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	1612	#define I2C_SMB_FACK_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	1613	#define I2C_SMB_FACK_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	1614	#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
Pawel Zarembski	0:01f31e923fe2	1615
Pawel Zarembski	0:01f31e923fe2	1616	/! @name A2 - I2C Address Register 2 /
Pawel Zarembski	0:01f31e923fe2	1617	#define I2C_A2_SAD_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	1618	#define I2C_A2_SAD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1619	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
Pawel Zarembski	0:01f31e923fe2	1620
Pawel Zarembski	0:01f31e923fe2	1621	/! @name SLTH - I2C SCL Low Timeout Register High /
Pawel Zarembski	0:01f31e923fe2	1622	#define I2C_SLTH_SSLT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1623	#define I2C_SLTH_SSLT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1624	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
Pawel Zarembski	0:01f31e923fe2	1625
Pawel Zarembski	0:01f31e923fe2	1626	/! @name SLTL - I2C SCL Low Timeout Register Low /
Pawel Zarembski	0:01f31e923fe2	1627	#define I2C_SLTL_SSLT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1628	#define I2C_SLTL_SSLT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1629	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
Pawel Zarembski	0:01f31e923fe2	1630
Pawel Zarembski	0:01f31e923fe2	1631
Pawel Zarembski	0:01f31e923fe2	1632	/*!
Pawel Zarembski	0:01f31e923fe2	1633	* @}
Pawel Zarembski	0:01f31e923fe2	1634	/ / end of group I2C_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1635
Pawel Zarembski	0:01f31e923fe2	1636
Pawel Zarembski	0:01f31e923fe2	1637	/* I2C - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1638	/** Peripheral I2C0 base address */
Pawel Zarembski	0:01f31e923fe2	1639	#define I2C0_BASE (0x40066000u)
Pawel Zarembski	0:01f31e923fe2	1640	/** Peripheral I2C0 base pointer */
Pawel Zarembski	0:01f31e923fe2	1641	#define I2C0 ((I2C_Type *)I2C0_BASE)
Pawel Zarembski	0:01f31e923fe2	1642	/** Peripheral I2C1 base address */
Pawel Zarembski	0:01f31e923fe2	1643	#define I2C1_BASE (0x40067000u)
Pawel Zarembski	0:01f31e923fe2	1644	/** Peripheral I2C1 base pointer */
Pawel Zarembski	0:01f31e923fe2	1645	#define I2C1 ((I2C_Type *)I2C1_BASE)
Pawel Zarembski	0:01f31e923fe2	1646	/** Array initializer of I2C peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1647	#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
Pawel Zarembski	0:01f31e923fe2	1648	/** Array initializer of I2C peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1649	#define I2C_BASE_PTRS { I2C0, I2C1 }
Pawel Zarembski	0:01f31e923fe2	1650	/** Interrupt vectors for the I2C peripheral type */
Pawel Zarembski	0:01f31e923fe2	1651	#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
Pawel Zarembski	0:01f31e923fe2	1652
Pawel Zarembski	0:01f31e923fe2	1653	/*!
Pawel Zarembski	0:01f31e923fe2	1654	* @}
Pawel Zarembski	0:01f31e923fe2	1655	/ / end of group I2C_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1656
Pawel Zarembski	0:01f31e923fe2	1657
Pawel Zarembski	0:01f31e923fe2	1658	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1659	-- I2S Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1660	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1661
Pawel Zarembski	0:01f31e923fe2	1662	/*!
Pawel Zarembski	0:01f31e923fe2	1663	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1664	* @{
Pawel Zarembski	0:01f31e923fe2	1665	*/
Pawel Zarembski	0:01f31e923fe2	1666
Pawel Zarembski	0:01f31e923fe2	1667	/** I2S - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	1668	typedef struct {
Pawel Zarembski	0:01f31e923fe2	1669	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	1670	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	1671	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	1672	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	1673	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	1674	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	1675	uint8_t RESERVED_1[8];
Pawel Zarembski	0:01f31e923fe2	1676	__O uint32_t TDR[1]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1677	uint8_t RESERVED_2[60];
Pawel Zarembski	0:01f31e923fe2	1678	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
Pawel Zarembski	0:01f31e923fe2	1679	uint8_t RESERVED_3[28];
Pawel Zarembski	0:01f31e923fe2	1680	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	1681	uint8_t RESERVED_4[4];
Pawel Zarembski	0:01f31e923fe2	1682	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
Pawel Zarembski	0:01f31e923fe2	1683	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
Pawel Zarembski	0:01f31e923fe2	1684	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
Pawel Zarembski	0:01f31e923fe2	1685	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
Pawel Zarembski	0:01f31e923fe2	1686	uint8_t RESERVED_5[8];
Pawel Zarembski	0:01f31e923fe2	1687	__I uint32_t RDR[1]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	1688	uint8_t RESERVED_6[60];
Pawel Zarembski	0:01f31e923fe2	1689	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
Pawel Zarembski	0:01f31e923fe2	1690	uint8_t RESERVED_7[28];
Pawel Zarembski	0:01f31e923fe2	1691	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
Pawel Zarembski	0:01f31e923fe2	1692	__IO uint32_t MDR; /*< SAI MCLK Divide Register, offset: 0x104 /
Pawel Zarembski	0:01f31e923fe2	1693	} I2S_Type;
Pawel Zarembski	0:01f31e923fe2	1694
Pawel Zarembski	0:01f31e923fe2	1695	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1696	-- I2S Register Masks
Pawel Zarembski	0:01f31e923fe2	1697	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1698
Pawel Zarembski	0:01f31e923fe2	1699	/*!
Pawel Zarembski	0:01f31e923fe2	1700	* @addtogroup I2S_Register_Masks I2S Register Masks
Pawel Zarembski	0:01f31e923fe2	1701	* @{
Pawel Zarembski	0:01f31e923fe2	1702	*/
Pawel Zarembski	0:01f31e923fe2	1703
Pawel Zarembski	0:01f31e923fe2	1704	/! @name TCSR - SAI Transmit Control Register /
Pawel Zarembski	0:01f31e923fe2	1705	#define I2S_TCSR_FWDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1706	#define I2S_TCSR_FWDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1707	#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
Pawel Zarembski	0:01f31e923fe2	1708	#define I2S_TCSR_FWIE_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	1709	#define I2S_TCSR_FWIE_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	1710	#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1711	#define I2S_TCSR_FEIE_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	1712	#define I2S_TCSR_FEIE_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	1713	#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1714	#define I2S_TCSR_SEIE_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	1715	#define I2S_TCSR_SEIE_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	1716	#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1717	#define I2S_TCSR_WSIE_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	1718	#define I2S_TCSR_WSIE_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	1719	#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1720	#define I2S_TCSR_FWF_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	1721	#define I2S_TCSR_FWF_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	1722	#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
Pawel Zarembski	0:01f31e923fe2	1723	#define I2S_TCSR_FEF_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	1724	#define I2S_TCSR_FEF_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	1725	#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
Pawel Zarembski	0:01f31e923fe2	1726	#define I2S_TCSR_SEF_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	1727	#define I2S_TCSR_SEF_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	1728	#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
Pawel Zarembski	0:01f31e923fe2	1729	#define I2S_TCSR_WSF_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	1730	#define I2S_TCSR_WSF_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	1731	#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
Pawel Zarembski	0:01f31e923fe2	1732	#define I2S_TCSR_SR_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	1733	#define I2S_TCSR_SR_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1734	#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
Pawel Zarembski	0:01f31e923fe2	1735	#define I2S_TCSR_FR_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	1736	#define I2S_TCSR_FR_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	1737	#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
Pawel Zarembski	0:01f31e923fe2	1738	#define I2S_TCSR_BCE_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	1739	#define I2S_TCSR_BCE_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	1740	#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1741	#define I2S_TCSR_DBGE_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	1742	#define I2S_TCSR_DBGE_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	1743	#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
Pawel Zarembski	0:01f31e923fe2	1744	#define I2S_TCSR_STOPE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	1745	#define I2S_TCSR_STOPE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1746	#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
Pawel Zarembski	0:01f31e923fe2	1747	#define I2S_TCSR_TE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	1748	#define I2S_TCSR_TE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	1749	#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
Pawel Zarembski	0:01f31e923fe2	1750
Pawel Zarembski	0:01f31e923fe2	1751	/! @name TCR2 - SAI Transmit Configuration 2 Register /
Pawel Zarembski	0:01f31e923fe2	1752	#define I2S_TCR2_DIV_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1753	#define I2S_TCR2_DIV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1754	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
Pawel Zarembski	0:01f31e923fe2	1755	#define I2S_TCR2_BCD_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	1756	#define I2S_TCR2_BCD_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1757	#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
Pawel Zarembski	0:01f31e923fe2	1758	#define I2S_TCR2_BCP_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	1759	#define I2S_TCR2_BCP_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	1760	#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
Pawel Zarembski	0:01f31e923fe2	1761	#define I2S_TCR2_MSEL_MASK (0xC000000U)
Pawel Zarembski	0:01f31e923fe2	1762	#define I2S_TCR2_MSEL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	1763	#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	1764	#define I2S_TCR2_BCI_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	1765	#define I2S_TCR2_BCI_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	1766	#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
Pawel Zarembski	0:01f31e923fe2	1767	#define I2S_TCR2_BCS_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	1768	#define I2S_TCR2_BCS_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	1769	#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
Pawel Zarembski	0:01f31e923fe2	1770	#define I2S_TCR2_SYNC_MASK (0xC0000000U)
Pawel Zarembski	0:01f31e923fe2	1771	#define I2S_TCR2_SYNC_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1772	#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
Pawel Zarembski	0:01f31e923fe2	1773
Pawel Zarembski	0:01f31e923fe2	1774	/! @name TCR3 - SAI Transmit Configuration 3 Register /
Pawel Zarembski	0:01f31e923fe2	1775	#define I2S_TCR3_WDFL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1776	#define I2S_TCR3_WDFL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1777	#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
Pawel Zarembski	0:01f31e923fe2	1778	#define I2S_TCR3_TCE_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1779	#define I2S_TCR3_TCE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1780	#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1781
Pawel Zarembski	0:01f31e923fe2	1782	/! @name TCR4 - SAI Transmit Configuration 4 Register /
Pawel Zarembski	0:01f31e923fe2	1783	#define I2S_TCR4_FSD_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1784	#define I2S_TCR4_FSD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1785	#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
Pawel Zarembski	0:01f31e923fe2	1786	#define I2S_TCR4_FSP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1787	#define I2S_TCR4_FSP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1788	#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
Pawel Zarembski	0:01f31e923fe2	1789	#define I2S_TCR4_FSE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1790	#define I2S_TCR4_FSE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1791	#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
Pawel Zarembski	0:01f31e923fe2	1792	#define I2S_TCR4_MF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1793	#define I2S_TCR4_MF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1794	#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
Pawel Zarembski	0:01f31e923fe2	1795	#define I2S_TCR4_SYWD_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	1796	#define I2S_TCR4_SYWD_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1797	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
Pawel Zarembski	0:01f31e923fe2	1798	#define I2S_TCR4_FRSZ_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1799	#define I2S_TCR4_FRSZ_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1800	#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
Pawel Zarembski	0:01f31e923fe2	1801
Pawel Zarembski	0:01f31e923fe2	1802	/! @name TCR5 - SAI Transmit Configuration 5 Register /
Pawel Zarembski	0:01f31e923fe2	1803	#define I2S_TCR5_FBT_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	1804	#define I2S_TCR5_FBT_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1805	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
Pawel Zarembski	0:01f31e923fe2	1806	#define I2S_TCR5_W0W_MASK (0x1F0000U)
Pawel Zarembski	0:01f31e923fe2	1807	#define I2S_TCR5_W0W_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1808	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
Pawel Zarembski	0:01f31e923fe2	1809	#define I2S_TCR5_WNW_MASK (0x1F000000U)
Pawel Zarembski	0:01f31e923fe2	1810	#define I2S_TCR5_WNW_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1811	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
Pawel Zarembski	0:01f31e923fe2	1812
Pawel Zarembski	0:01f31e923fe2	1813	/! @name TDR - SAI Transmit Data Register /
Pawel Zarembski	0:01f31e923fe2	1814	#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1815	#define I2S_TDR_TDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1816	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
Pawel Zarembski	0:01f31e923fe2	1817
Pawel Zarembski	0:01f31e923fe2	1818	/* The count of I2S_TDR */
Pawel Zarembski	0:01f31e923fe2	1819	#define I2S_TDR_COUNT (1U)
Pawel Zarembski	0:01f31e923fe2	1820
Pawel Zarembski	0:01f31e923fe2	1821	/! @name TMR - SAI Transmit Mask Register /
Pawel Zarembski	0:01f31e923fe2	1822	#define I2S_TMR_TWM_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	1823	#define I2S_TMR_TWM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1824	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
Pawel Zarembski	0:01f31e923fe2	1825
Pawel Zarembski	0:01f31e923fe2	1826	/! @name RCSR - SAI Receive Control Register /
Pawel Zarembski	0:01f31e923fe2	1827	#define I2S_RCSR_FWDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1828	#define I2S_RCSR_FWDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1829	#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
Pawel Zarembski	0:01f31e923fe2	1830	#define I2S_RCSR_FWIE_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	1831	#define I2S_RCSR_FWIE_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	1832	#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1833	#define I2S_RCSR_FEIE_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	1834	#define I2S_RCSR_FEIE_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	1835	#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1836	#define I2S_RCSR_SEIE_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	1837	#define I2S_RCSR_SEIE_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	1838	#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1839	#define I2S_RCSR_WSIE_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	1840	#define I2S_RCSR_WSIE_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	1841	#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	1842	#define I2S_RCSR_FWF_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	1843	#define I2S_RCSR_FWF_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	1844	#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
Pawel Zarembski	0:01f31e923fe2	1845	#define I2S_RCSR_FEF_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	1846	#define I2S_RCSR_FEF_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	1847	#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
Pawel Zarembski	0:01f31e923fe2	1848	#define I2S_RCSR_SEF_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	1849	#define I2S_RCSR_SEF_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	1850	#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
Pawel Zarembski	0:01f31e923fe2	1851	#define I2S_RCSR_WSF_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	1852	#define I2S_RCSR_WSF_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	1853	#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
Pawel Zarembski	0:01f31e923fe2	1854	#define I2S_RCSR_SR_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	1855	#define I2S_RCSR_SR_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1856	#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
Pawel Zarembski	0:01f31e923fe2	1857	#define I2S_RCSR_FR_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	1858	#define I2S_RCSR_FR_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	1859	#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
Pawel Zarembski	0:01f31e923fe2	1860	#define I2S_RCSR_BCE_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	1861	#define I2S_RCSR_BCE_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	1862	#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1863	#define I2S_RCSR_DBGE_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	1864	#define I2S_RCSR_DBGE_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	1865	#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
Pawel Zarembski	0:01f31e923fe2	1866	#define I2S_RCSR_STOPE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	1867	#define I2S_RCSR_STOPE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1868	#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
Pawel Zarembski	0:01f31e923fe2	1869	#define I2S_RCSR_RE_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	1870	#define I2S_RCSR_RE_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	1871	#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	1872
Pawel Zarembski	0:01f31e923fe2	1873	/! @name RCR2 - SAI Receive Configuration 2 Register /
Pawel Zarembski	0:01f31e923fe2	1874	#define I2S_RCR2_DIV_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	1875	#define I2S_RCR2_DIV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1876	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
Pawel Zarembski	0:01f31e923fe2	1877	#define I2S_RCR2_BCD_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	1878	#define I2S_RCR2_BCD_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1879	#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
Pawel Zarembski	0:01f31e923fe2	1880	#define I2S_RCR2_BCP_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	1881	#define I2S_RCR2_BCP_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	1882	#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
Pawel Zarembski	0:01f31e923fe2	1883	#define I2S_RCR2_MSEL_MASK (0xC000000U)
Pawel Zarembski	0:01f31e923fe2	1884	#define I2S_RCR2_MSEL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	1885	#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	1886	#define I2S_RCR2_BCI_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	1887	#define I2S_RCR2_BCI_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	1888	#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
Pawel Zarembski	0:01f31e923fe2	1889	#define I2S_RCR2_BCS_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	1890	#define I2S_RCR2_BCS_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	1891	#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
Pawel Zarembski	0:01f31e923fe2	1892	#define I2S_RCR2_SYNC_MASK (0xC0000000U)
Pawel Zarembski	0:01f31e923fe2	1893	#define I2S_RCR2_SYNC_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1894	#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
Pawel Zarembski	0:01f31e923fe2	1895
Pawel Zarembski	0:01f31e923fe2	1896	/! @name RCR3 - SAI Receive Configuration 3 Register /
Pawel Zarembski	0:01f31e923fe2	1897	#define I2S_RCR3_WDFL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1898	#define I2S_RCR3_WDFL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1899	#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
Pawel Zarembski	0:01f31e923fe2	1900	#define I2S_RCR3_RCE_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1901	#define I2S_RCR3_RCE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1902	#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
Pawel Zarembski	0:01f31e923fe2	1903
Pawel Zarembski	0:01f31e923fe2	1904	/! @name RCR4 - SAI Receive Configuration 4 Register /
Pawel Zarembski	0:01f31e923fe2	1905	#define I2S_RCR4_FSD_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	1906	#define I2S_RCR4_FSD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1907	#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
Pawel Zarembski	0:01f31e923fe2	1908	#define I2S_RCR4_FSP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	1909	#define I2S_RCR4_FSP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	1910	#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
Pawel Zarembski	0:01f31e923fe2	1911	#define I2S_RCR4_FSE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	1912	#define I2S_RCR4_FSE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	1913	#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
Pawel Zarembski	0:01f31e923fe2	1914	#define I2S_RCR4_MF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	1915	#define I2S_RCR4_MF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	1916	#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
Pawel Zarembski	0:01f31e923fe2	1917	#define I2S_RCR4_SYWD_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	1918	#define I2S_RCR4_SYWD_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1919	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
Pawel Zarembski	0:01f31e923fe2	1920	#define I2S_RCR4_FRSZ_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	1921	#define I2S_RCR4_FRSZ_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1922	#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
Pawel Zarembski	0:01f31e923fe2	1923
Pawel Zarembski	0:01f31e923fe2	1924	/! @name RCR5 - SAI Receive Configuration 5 Register /
Pawel Zarembski	0:01f31e923fe2	1925	#define I2S_RCR5_FBT_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	1926	#define I2S_RCR5_FBT_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	1927	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
Pawel Zarembski	0:01f31e923fe2	1928	#define I2S_RCR5_W0W_MASK (0x1F0000U)
Pawel Zarembski	0:01f31e923fe2	1929	#define I2S_RCR5_W0W_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	1930	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
Pawel Zarembski	0:01f31e923fe2	1931	#define I2S_RCR5_WNW_MASK (0x1F000000U)
Pawel Zarembski	0:01f31e923fe2	1932	#define I2S_RCR5_WNW_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1933	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
Pawel Zarembski	0:01f31e923fe2	1934
Pawel Zarembski	0:01f31e923fe2	1935	/! @name RDR - SAI Receive Data Register /
Pawel Zarembski	0:01f31e923fe2	1936	#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	1937	#define I2S_RDR_RDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1938	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
Pawel Zarembski	0:01f31e923fe2	1939
Pawel Zarembski	0:01f31e923fe2	1940	/* The count of I2S_RDR */
Pawel Zarembski	0:01f31e923fe2	1941	#define I2S_RDR_COUNT (1U)
Pawel Zarembski	0:01f31e923fe2	1942
Pawel Zarembski	0:01f31e923fe2	1943	/! @name RMR - SAI Receive Mask Register /
Pawel Zarembski	0:01f31e923fe2	1944	#define I2S_RMR_RWM_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	1945	#define I2S_RMR_RWM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1946	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
Pawel Zarembski	0:01f31e923fe2	1947
Pawel Zarembski	0:01f31e923fe2	1948	/! @name MCR - SAI MCLK Control Register /
Pawel Zarembski	0:01f31e923fe2	1949	#define I2S_MCR_MICS_MASK (0x3000000U)
Pawel Zarembski	0:01f31e923fe2	1950	#define I2S_MCR_MICS_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	1951	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
Pawel Zarembski	0:01f31e923fe2	1952	#define I2S_MCR_MOE_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	1953	#define I2S_MCR_MOE_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	1954	#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
Pawel Zarembski	0:01f31e923fe2	1955	#define I2S_MCR_DUF_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	1956	#define I2S_MCR_DUF_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	1957	#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
Pawel Zarembski	0:01f31e923fe2	1958
Pawel Zarembski	0:01f31e923fe2	1959	/! @name MDR - SAI MCLK Divide Register /
Pawel Zarembski	0:01f31e923fe2	1960	#define I2S_MDR_DIVIDE_MASK (0xFFFU)
Pawel Zarembski	0:01f31e923fe2	1961	#define I2S_MDR_DIVIDE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	1962	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
Pawel Zarembski	0:01f31e923fe2	1963	#define I2S_MDR_FRACT_MASK (0xFF000U)
Pawel Zarembski	0:01f31e923fe2	1964	#define I2S_MDR_FRACT_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	1965	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
Pawel Zarembski	0:01f31e923fe2	1966
Pawel Zarembski	0:01f31e923fe2	1967
Pawel Zarembski	0:01f31e923fe2	1968	/*!
Pawel Zarembski	0:01f31e923fe2	1969	* @}
Pawel Zarembski	0:01f31e923fe2	1970	/ / end of group I2S_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	1971
Pawel Zarembski	0:01f31e923fe2	1972
Pawel Zarembski	0:01f31e923fe2	1973	/* I2S - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	1974	/** Peripheral I2S0 base address */
Pawel Zarembski	0:01f31e923fe2	1975	#define I2S0_BASE (0x4002F000u)
Pawel Zarembski	0:01f31e923fe2	1976	/** Peripheral I2S0 base pointer */
Pawel Zarembski	0:01f31e923fe2	1977	#define I2S0 ((I2S_Type *)I2S0_BASE)
Pawel Zarembski	0:01f31e923fe2	1978	/** Array initializer of I2S peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	1979	#define I2S_BASE_ADDRS { I2S0_BASE }
Pawel Zarembski	0:01f31e923fe2	1980	/** Array initializer of I2S peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	1981	#define I2S_BASE_PTRS { I2S0 }
Pawel Zarembski	0:01f31e923fe2	1982	/** Interrupt vectors for the I2S peripheral type */
Pawel Zarembski	0:01f31e923fe2	1983	#define I2S_RX_IRQS { I2S0_IRQn }
Pawel Zarembski	0:01f31e923fe2	1984	#define I2S_TX_IRQS { I2S0_IRQn }
Pawel Zarembski	0:01f31e923fe2	1985
Pawel Zarembski	0:01f31e923fe2	1986	/*!
Pawel Zarembski	0:01f31e923fe2	1987	* @}
Pawel Zarembski	0:01f31e923fe2	1988	/ / end of group I2S_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	1989
Pawel Zarembski	0:01f31e923fe2	1990
Pawel Zarembski	0:01f31e923fe2	1991	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	1992	-- LLWU Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1993	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	1994
Pawel Zarembski	0:01f31e923fe2	1995	/*!
Pawel Zarembski	0:01f31e923fe2	1996	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	1997	* @{
Pawel Zarembski	0:01f31e923fe2	1998	*/
Pawel Zarembski	0:01f31e923fe2	1999
Pawel Zarembski	0:01f31e923fe2	2000	/** LLWU - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2001	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2002	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2003	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	2004	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	2005	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	2006	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2007	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	2008	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	2009	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	2010	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2011	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	2012	} LLWU_Type;
Pawel Zarembski	0:01f31e923fe2	2013
Pawel Zarembski	0:01f31e923fe2	2014	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2015	-- LLWU Register Masks
Pawel Zarembski	0:01f31e923fe2	2016	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2017
Pawel Zarembski	0:01f31e923fe2	2018	/*!
Pawel Zarembski	0:01f31e923fe2	2019	* @addtogroup LLWU_Register_Masks LLWU Register Masks
Pawel Zarembski	0:01f31e923fe2	2020	* @{
Pawel Zarembski	0:01f31e923fe2	2021	*/
Pawel Zarembski	0:01f31e923fe2	2022
Pawel Zarembski	0:01f31e923fe2	2023	/! @name PE1 - LLWU Pin Enable 1 register /
Pawel Zarembski	0:01f31e923fe2	2024	#define LLWU_PE1_WUPE0_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	2025	#define LLWU_PE1_WUPE0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2026	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
Pawel Zarembski	0:01f31e923fe2	2027	#define LLWU_PE1_WUPE1_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	2028	#define LLWU_PE1_WUPE1_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2029	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
Pawel Zarembski	0:01f31e923fe2	2030	#define LLWU_PE1_WUPE2_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2031	#define LLWU_PE1_WUPE2_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2032	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
Pawel Zarembski	0:01f31e923fe2	2033	#define LLWU_PE1_WUPE3_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2034	#define LLWU_PE1_WUPE3_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2035	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
Pawel Zarembski	0:01f31e923fe2	2036
Pawel Zarembski	0:01f31e923fe2	2037	/! @name PE2 - LLWU Pin Enable 2 register /
Pawel Zarembski	0:01f31e923fe2	2038	#define LLWU_PE2_WUPE4_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	2039	#define LLWU_PE2_WUPE4_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2040	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
Pawel Zarembski	0:01f31e923fe2	2041	#define LLWU_PE2_WUPE5_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	2042	#define LLWU_PE2_WUPE5_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2043	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
Pawel Zarembski	0:01f31e923fe2	2044	#define LLWU_PE2_WUPE6_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2045	#define LLWU_PE2_WUPE6_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2046	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
Pawel Zarembski	0:01f31e923fe2	2047	#define LLWU_PE2_WUPE7_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2048	#define LLWU_PE2_WUPE7_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2049	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
Pawel Zarembski	0:01f31e923fe2	2050
Pawel Zarembski	0:01f31e923fe2	2051	/! @name PE3 - LLWU Pin Enable 3 register /
Pawel Zarembski	0:01f31e923fe2	2052	#define LLWU_PE3_WUPE8_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	2053	#define LLWU_PE3_WUPE8_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2054	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
Pawel Zarembski	0:01f31e923fe2	2055	#define LLWU_PE3_WUPE9_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	2056	#define LLWU_PE3_WUPE9_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2057	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
Pawel Zarembski	0:01f31e923fe2	2058	#define LLWU_PE3_WUPE10_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2059	#define LLWU_PE3_WUPE10_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2060	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
Pawel Zarembski	0:01f31e923fe2	2061	#define LLWU_PE3_WUPE11_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2062	#define LLWU_PE3_WUPE11_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2063	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
Pawel Zarembski	0:01f31e923fe2	2064
Pawel Zarembski	0:01f31e923fe2	2065	/! @name PE4 - LLWU Pin Enable 4 register /
Pawel Zarembski	0:01f31e923fe2	2066	#define LLWU_PE4_WUPE12_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	2067	#define LLWU_PE4_WUPE12_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2068	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
Pawel Zarembski	0:01f31e923fe2	2069	#define LLWU_PE4_WUPE13_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	2070	#define LLWU_PE4_WUPE13_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2071	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
Pawel Zarembski	0:01f31e923fe2	2072	#define LLWU_PE4_WUPE14_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2073	#define LLWU_PE4_WUPE14_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2074	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
Pawel Zarembski	0:01f31e923fe2	2075	#define LLWU_PE4_WUPE15_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2076	#define LLWU_PE4_WUPE15_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2077	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
Pawel Zarembski	0:01f31e923fe2	2078
Pawel Zarembski	0:01f31e923fe2	2079	/! @name ME - LLWU Module Enable register /
Pawel Zarembski	0:01f31e923fe2	2080	#define LLWU_ME_WUME0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2081	#define LLWU_ME_WUME0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2082	#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
Pawel Zarembski	0:01f31e923fe2	2083	#define LLWU_ME_WUME1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2084	#define LLWU_ME_WUME1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2085	#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
Pawel Zarembski	0:01f31e923fe2	2086	#define LLWU_ME_WUME2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2087	#define LLWU_ME_WUME2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2088	#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
Pawel Zarembski	0:01f31e923fe2	2089	#define LLWU_ME_WUME3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2090	#define LLWU_ME_WUME3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2091	#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
Pawel Zarembski	0:01f31e923fe2	2092	#define LLWU_ME_WUME4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2093	#define LLWU_ME_WUME4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2094	#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
Pawel Zarembski	0:01f31e923fe2	2095	#define LLWU_ME_WUME5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2096	#define LLWU_ME_WUME5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2097	#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
Pawel Zarembski	0:01f31e923fe2	2098	#define LLWU_ME_WUME6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2099	#define LLWU_ME_WUME6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2100	#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
Pawel Zarembski	0:01f31e923fe2	2101	#define LLWU_ME_WUME7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2102	#define LLWU_ME_WUME7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2103	#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
Pawel Zarembski	0:01f31e923fe2	2104
Pawel Zarembski	0:01f31e923fe2	2105	/! @name F1 - LLWU Flag 1 register /
Pawel Zarembski	0:01f31e923fe2	2106	#define LLWU_F1_WUF0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2107	#define LLWU_F1_WUF0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2108	#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
Pawel Zarembski	0:01f31e923fe2	2109	#define LLWU_F1_WUF1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2110	#define LLWU_F1_WUF1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2111	#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
Pawel Zarembski	0:01f31e923fe2	2112	#define LLWU_F1_WUF2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2113	#define LLWU_F1_WUF2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2114	#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
Pawel Zarembski	0:01f31e923fe2	2115	#define LLWU_F1_WUF3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2116	#define LLWU_F1_WUF3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2117	#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
Pawel Zarembski	0:01f31e923fe2	2118	#define LLWU_F1_WUF4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2119	#define LLWU_F1_WUF4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2120	#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
Pawel Zarembski	0:01f31e923fe2	2121	#define LLWU_F1_WUF5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2122	#define LLWU_F1_WUF5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2123	#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
Pawel Zarembski	0:01f31e923fe2	2124	#define LLWU_F1_WUF6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2125	#define LLWU_F1_WUF6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2126	#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
Pawel Zarembski	0:01f31e923fe2	2127	#define LLWU_F1_WUF7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2128	#define LLWU_F1_WUF7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2129	#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
Pawel Zarembski	0:01f31e923fe2	2130
Pawel Zarembski	0:01f31e923fe2	2131	/! @name F2 - LLWU Flag 2 register /
Pawel Zarembski	0:01f31e923fe2	2132	#define LLWU_F2_WUF8_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2133	#define LLWU_F2_WUF8_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2134	#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
Pawel Zarembski	0:01f31e923fe2	2135	#define LLWU_F2_WUF9_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2136	#define LLWU_F2_WUF9_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2137	#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
Pawel Zarembski	0:01f31e923fe2	2138	#define LLWU_F2_WUF10_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2139	#define LLWU_F2_WUF10_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2140	#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
Pawel Zarembski	0:01f31e923fe2	2141	#define LLWU_F2_WUF11_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2142	#define LLWU_F2_WUF11_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2143	#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
Pawel Zarembski	0:01f31e923fe2	2144	#define LLWU_F2_WUF12_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2145	#define LLWU_F2_WUF12_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2146	#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
Pawel Zarembski	0:01f31e923fe2	2147	#define LLWU_F2_WUF13_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2148	#define LLWU_F2_WUF13_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2149	#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
Pawel Zarembski	0:01f31e923fe2	2150	#define LLWU_F2_WUF14_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2151	#define LLWU_F2_WUF14_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2152	#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
Pawel Zarembski	0:01f31e923fe2	2153	#define LLWU_F2_WUF15_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2154	#define LLWU_F2_WUF15_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2155	#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
Pawel Zarembski	0:01f31e923fe2	2156
Pawel Zarembski	0:01f31e923fe2	2157	/! @name F3 - LLWU Flag 3 register /
Pawel Zarembski	0:01f31e923fe2	2158	#define LLWU_F3_MWUF0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2159	#define LLWU_F3_MWUF0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2160	#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
Pawel Zarembski	0:01f31e923fe2	2161	#define LLWU_F3_MWUF1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2162	#define LLWU_F3_MWUF1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2163	#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
Pawel Zarembski	0:01f31e923fe2	2164	#define LLWU_F3_MWUF2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2165	#define LLWU_F3_MWUF2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2166	#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
Pawel Zarembski	0:01f31e923fe2	2167	#define LLWU_F3_MWUF3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2168	#define LLWU_F3_MWUF3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2169	#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
Pawel Zarembski	0:01f31e923fe2	2170	#define LLWU_F3_MWUF4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2171	#define LLWU_F3_MWUF4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2172	#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
Pawel Zarembski	0:01f31e923fe2	2173	#define LLWU_F3_MWUF5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2174	#define LLWU_F3_MWUF5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2175	#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
Pawel Zarembski	0:01f31e923fe2	2176	#define LLWU_F3_MWUF6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2177	#define LLWU_F3_MWUF6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2178	#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
Pawel Zarembski	0:01f31e923fe2	2179	#define LLWU_F3_MWUF7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2180	#define LLWU_F3_MWUF7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2181	#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
Pawel Zarembski	0:01f31e923fe2	2182
Pawel Zarembski	0:01f31e923fe2	2183	/! @name FILT1 - LLWU Pin Filter 1 register /
Pawel Zarembski	0:01f31e923fe2	2184	#define LLWU_FILT1_FILTSEL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	2185	#define LLWU_FILT1_FILTSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2186	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2187	#define LLWU_FILT1_FILTE_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	2188	#define LLWU_FILT1_FILTE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2189	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
Pawel Zarembski	0:01f31e923fe2	2190	#define LLWU_FILT1_FILTF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2191	#define LLWU_FILT1_FILTF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2192	#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
Pawel Zarembski	0:01f31e923fe2	2193
Pawel Zarembski	0:01f31e923fe2	2194	/! @name FILT2 - LLWU Pin Filter 2 register /
Pawel Zarembski	0:01f31e923fe2	2195	#define LLWU_FILT2_FILTSEL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	2196	#define LLWU_FILT2_FILTSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2197	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2198	#define LLWU_FILT2_FILTE_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	2199	#define LLWU_FILT2_FILTE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2200	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
Pawel Zarembski	0:01f31e923fe2	2201	#define LLWU_FILT2_FILTF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2202	#define LLWU_FILT2_FILTF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2203	#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
Pawel Zarembski	0:01f31e923fe2	2204
Pawel Zarembski	0:01f31e923fe2	2205
Pawel Zarembski	0:01f31e923fe2	2206	/*!
Pawel Zarembski	0:01f31e923fe2	2207	* @}
Pawel Zarembski	0:01f31e923fe2	2208	/ / end of group LLWU_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2209
Pawel Zarembski	0:01f31e923fe2	2210
Pawel Zarembski	0:01f31e923fe2	2211	/* LLWU - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2212	/** Peripheral LLWU base address */
Pawel Zarembski	0:01f31e923fe2	2213	#define LLWU_BASE (0x4007C000u)
Pawel Zarembski	0:01f31e923fe2	2214	/** Peripheral LLWU base pointer */
Pawel Zarembski	0:01f31e923fe2	2215	#define LLWU ((LLWU_Type *)LLWU_BASE)
Pawel Zarembski	0:01f31e923fe2	2216	/** Array initializer of LLWU peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2217	#define LLWU_BASE_ADDRS { LLWU_BASE }
Pawel Zarembski	0:01f31e923fe2	2218	/** Array initializer of LLWU peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2219	#define LLWU_BASE_PTRS { LLWU }
Pawel Zarembski	0:01f31e923fe2	2220	/** Interrupt vectors for the LLWU peripheral type */
Pawel Zarembski	0:01f31e923fe2	2221	#define LLWU_IRQS { LLWU_IRQn }
Pawel Zarembski	0:01f31e923fe2	2222
Pawel Zarembski	0:01f31e923fe2	2223	/*!
Pawel Zarembski	0:01f31e923fe2	2224	* @}
Pawel Zarembski	0:01f31e923fe2	2225	/ / end of group LLWU_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2226
Pawel Zarembski	0:01f31e923fe2	2227
Pawel Zarembski	0:01f31e923fe2	2228	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2229	-- LPTMR Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2230	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2231
Pawel Zarembski	0:01f31e923fe2	2232	/*!
Pawel Zarembski	0:01f31e923fe2	2233	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2234	* @{
Pawel Zarembski	0:01f31e923fe2	2235	*/
Pawel Zarembski	0:01f31e923fe2	2236
Pawel Zarembski	0:01f31e923fe2	2237	/** LPTMR - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2238	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2239	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2240	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2241	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2242	__IO uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	2243	} LPTMR_Type;
Pawel Zarembski	0:01f31e923fe2	2244
Pawel Zarembski	0:01f31e923fe2	2245	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2246	-- LPTMR Register Masks
Pawel Zarembski	0:01f31e923fe2	2247	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2248
Pawel Zarembski	0:01f31e923fe2	2249	/*!
Pawel Zarembski	0:01f31e923fe2	2250	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Pawel Zarembski	0:01f31e923fe2	2251	* @{
Pawel Zarembski	0:01f31e923fe2	2252	*/
Pawel Zarembski	0:01f31e923fe2	2253
Pawel Zarembski	0:01f31e923fe2	2254	/! @name CSR - Low Power Timer Control Status Register /
Pawel Zarembski	0:01f31e923fe2	2255	#define LPTMR_CSR_TEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2256	#define LPTMR_CSR_TEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2257	#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2258	#define LPTMR_CSR_TMS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2259	#define LPTMR_CSR_TMS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2260	#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
Pawel Zarembski	0:01f31e923fe2	2261	#define LPTMR_CSR_TFC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2262	#define LPTMR_CSR_TFC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2263	#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
Pawel Zarembski	0:01f31e923fe2	2264	#define LPTMR_CSR_TPP_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2265	#define LPTMR_CSR_TPP_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2266	#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
Pawel Zarembski	0:01f31e923fe2	2267	#define LPTMR_CSR_TPS_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2268	#define LPTMR_CSR_TPS_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2269	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
Pawel Zarembski	0:01f31e923fe2	2270	#define LPTMR_CSR_TIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2271	#define LPTMR_CSR_TIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2272	#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	2273	#define LPTMR_CSR_TCF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2274	#define LPTMR_CSR_TCF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2275	#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
Pawel Zarembski	0:01f31e923fe2	2276
Pawel Zarembski	0:01f31e923fe2	2277	/! @name PSR - Low Power Timer Prescale Register /
Pawel Zarembski	0:01f31e923fe2	2278	#define LPTMR_PSR_PCS_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	2279	#define LPTMR_PSR_PCS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2280	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
Pawel Zarembski	0:01f31e923fe2	2281	#define LPTMR_PSR_PBYP_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2282	#define LPTMR_PSR_PBYP_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2283	#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
Pawel Zarembski	0:01f31e923fe2	2284	#define LPTMR_PSR_PRESCALE_MASK (0x78U)
Pawel Zarembski	0:01f31e923fe2	2285	#define LPTMR_PSR_PRESCALE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2286	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
Pawel Zarembski	0:01f31e923fe2	2287
Pawel Zarembski	0:01f31e923fe2	2288	/! @name CMR - Low Power Timer Compare Register /
Pawel Zarembski	0:01f31e923fe2	2289	#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	2290	#define LPTMR_CMR_COMPARE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2291	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
Pawel Zarembski	0:01f31e923fe2	2292
Pawel Zarembski	0:01f31e923fe2	2293	/! @name CNR - Low Power Timer Counter Register /
Pawel Zarembski	0:01f31e923fe2	2294	#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	2295	#define LPTMR_CNR_COUNTER_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2296	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
Pawel Zarembski	0:01f31e923fe2	2297
Pawel Zarembski	0:01f31e923fe2	2298
Pawel Zarembski	0:01f31e923fe2	2299	/*!
Pawel Zarembski	0:01f31e923fe2	2300	* @}
Pawel Zarembski	0:01f31e923fe2	2301	/ / end of group LPTMR_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2302
Pawel Zarembski	0:01f31e923fe2	2303
Pawel Zarembski	0:01f31e923fe2	2304	/* LPTMR - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2305	/** Peripheral LPTMR0 base address */
Pawel Zarembski	0:01f31e923fe2	2306	#define LPTMR0_BASE (0x40040000u)
Pawel Zarembski	0:01f31e923fe2	2307	/** Peripheral LPTMR0 base pointer */
Pawel Zarembski	0:01f31e923fe2	2308	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
Pawel Zarembski	0:01f31e923fe2	2309	/** Array initializer of LPTMR peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2310	#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
Pawel Zarembski	0:01f31e923fe2	2311	/** Array initializer of LPTMR peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2312	#define LPTMR_BASE_PTRS { LPTMR0 }
Pawel Zarembski	0:01f31e923fe2	2313	/** Interrupt vectors for the LPTMR peripheral type */
Pawel Zarembski	0:01f31e923fe2	2314	#define LPTMR_IRQS { LPTMR0_IRQn }
Pawel Zarembski	0:01f31e923fe2	2315
Pawel Zarembski	0:01f31e923fe2	2316	/*!
Pawel Zarembski	0:01f31e923fe2	2317	* @}
Pawel Zarembski	0:01f31e923fe2	2318	/ / end of group LPTMR_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2319
Pawel Zarembski	0:01f31e923fe2	2320
Pawel Zarembski	0:01f31e923fe2	2321	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2322	-- MCG Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2323	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2324
Pawel Zarembski	0:01f31e923fe2	2325	/*!
Pawel Zarembski	0:01f31e923fe2	2326	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2327	* @{
Pawel Zarembski	0:01f31e923fe2	2328	*/
Pawel Zarembski	0:01f31e923fe2	2329
Pawel Zarembski	0:01f31e923fe2	2330	/** MCG - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2331	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2332	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2333	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	2334	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	2335	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	2336	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2337	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	2338	__IO uint8_t S; /*< MCG Status Register, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	2339	uint8_t RESERVED_0[1];
Pawel Zarembski	0:01f31e923fe2	2340	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2341	uint8_t RESERVED_1[1];
Pawel Zarembski	0:01f31e923fe2	2342	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	2343	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	2344	__IO uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	2345	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	2346	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
Pawel Zarembski	0:01f31e923fe2	2347	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
Pawel Zarembski	0:01f31e923fe2	2348	} MCG_Type;
Pawel Zarembski	0:01f31e923fe2	2349
Pawel Zarembski	0:01f31e923fe2	2350	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2351	-- MCG Register Masks
Pawel Zarembski	0:01f31e923fe2	2352	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2353
Pawel Zarembski	0:01f31e923fe2	2354	/*!
Pawel Zarembski	0:01f31e923fe2	2355	* @addtogroup MCG_Register_Masks MCG Register Masks
Pawel Zarembski	0:01f31e923fe2	2356	* @{
Pawel Zarembski	0:01f31e923fe2	2357	*/
Pawel Zarembski	0:01f31e923fe2	2358
Pawel Zarembski	0:01f31e923fe2	2359	/! @name C1 - MCG Control 1 Register /
Pawel Zarembski	0:01f31e923fe2	2360	#define MCG_C1_IREFSTEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2361	#define MCG_C1_IREFSTEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2362	#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2363	#define MCG_C1_IRCLKEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2364	#define MCG_C1_IRCLKEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2365	#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2366	#define MCG_C1_IREFS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2367	#define MCG_C1_IREFS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2368	#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
Pawel Zarembski	0:01f31e923fe2	2369	#define MCG_C1_FRDIV_MASK (0x38U)
Pawel Zarembski	0:01f31e923fe2	2370	#define MCG_C1_FRDIV_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2371	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	2372	#define MCG_C1_CLKS_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	2373	#define MCG_C1_CLKS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2374	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
Pawel Zarembski	0:01f31e923fe2	2375
Pawel Zarembski	0:01f31e923fe2	2376	/! @name C2 - MCG Control 2 Register /
Pawel Zarembski	0:01f31e923fe2	2377	#define MCG_C2_IRCS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2378	#define MCG_C2_IRCS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2379	#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
Pawel Zarembski	0:01f31e923fe2	2380	#define MCG_C2_LP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2381	#define MCG_C2_LP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2382	#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
Pawel Zarembski	0:01f31e923fe2	2383	#define MCG_C2_EREFS0_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2384	#define MCG_C2_EREFS0_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2385	#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
Pawel Zarembski	0:01f31e923fe2	2386	#define MCG_C2_HGO0_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2387	#define MCG_C2_HGO0_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2388	#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
Pawel Zarembski	0:01f31e923fe2	2389	#define MCG_C2_RANGE0_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	2390	#define MCG_C2_RANGE0_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2391	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
Pawel Zarembski	0:01f31e923fe2	2392	#define MCG_C2_FCFTRIM_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2393	#define MCG_C2_FCFTRIM_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2394	#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	2395	#define MCG_C2_LOCRE0_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2396	#define MCG_C2_LOCRE0_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2397	#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
Pawel Zarembski	0:01f31e923fe2	2398
Pawel Zarembski	0:01f31e923fe2	2399	/! @name C3 - MCG Control 3 Register /
Pawel Zarembski	0:01f31e923fe2	2400	#define MCG_C3_SCTRIM_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2401	#define MCG_C3_SCTRIM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2402	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	2403
Pawel Zarembski	0:01f31e923fe2	2404	/! @name C4 - MCG Control 4 Register /
Pawel Zarembski	0:01f31e923fe2	2405	#define MCG_C4_SCFTRIM_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2406	#define MCG_C4_SCFTRIM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2407	#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	2408	#define MCG_C4_FCTRIM_MASK (0x1EU)
Pawel Zarembski	0:01f31e923fe2	2409	#define MCG_C4_FCTRIM_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2410	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
Pawel Zarembski	0:01f31e923fe2	2411	#define MCG_C4_DRST_DRS_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	2412	#define MCG_C4_DRST_DRS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2413	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
Pawel Zarembski	0:01f31e923fe2	2414	#define MCG_C4_DMX32_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2415	#define MCG_C4_DMX32_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2416	#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
Pawel Zarembski	0:01f31e923fe2	2417
Pawel Zarembski	0:01f31e923fe2	2418	/! @name C5 - MCG Control 5 Register /
Pawel Zarembski	0:01f31e923fe2	2419	#define MCG_C5_PRDIV0_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	2420	#define MCG_C5_PRDIV0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2421	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
Pawel Zarembski	0:01f31e923fe2	2422	#define MCG_C5_PLLSTEN0_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2423	#define MCG_C5_PLLSTEN0_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2424	#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	2425	#define MCG_C5_PLLCLKEN0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2426	#define MCG_C5_PLLCLKEN0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2427	#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
Pawel Zarembski	0:01f31e923fe2	2428
Pawel Zarembski	0:01f31e923fe2	2429	/! @name C6 - MCG Control 6 Register /
Pawel Zarembski	0:01f31e923fe2	2430	#define MCG_C6_VDIV0_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	2431	#define MCG_C6_VDIV0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2432	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
Pawel Zarembski	0:01f31e923fe2	2433	#define MCG_C6_CME0_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2434	#define MCG_C6_CME0_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2435	#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
Pawel Zarembski	0:01f31e923fe2	2436	#define MCG_C6_PLLS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2437	#define MCG_C6_PLLS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2438	#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
Pawel Zarembski	0:01f31e923fe2	2439	#define MCG_C6_LOLIE0_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2440	#define MCG_C6_LOLIE0_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2441	#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
Pawel Zarembski	0:01f31e923fe2	2442
Pawel Zarembski	0:01f31e923fe2	2443	/! @name S - MCG Status Register /
Pawel Zarembski	0:01f31e923fe2	2444	#define MCG_S_IRCST_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2445	#define MCG_S_IRCST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2446	#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
Pawel Zarembski	0:01f31e923fe2	2447	#define MCG_S_OSCINIT0_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2448	#define MCG_S_OSCINIT0_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2449	#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
Pawel Zarembski	0:01f31e923fe2	2450	#define MCG_S_CLKST_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	2451	#define MCG_S_CLKST_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2452	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
Pawel Zarembski	0:01f31e923fe2	2453	#define MCG_S_IREFST_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2454	#define MCG_S_IREFST_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2455	#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
Pawel Zarembski	0:01f31e923fe2	2456	#define MCG_S_PLLST_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2457	#define MCG_S_PLLST_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2458	#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
Pawel Zarembski	0:01f31e923fe2	2459	#define MCG_S_LOCK0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2460	#define MCG_S_LOCK0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2461	#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
Pawel Zarembski	0:01f31e923fe2	2462	#define MCG_S_LOLS0_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2463	#define MCG_S_LOLS0_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2464	#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
Pawel Zarembski	0:01f31e923fe2	2465
Pawel Zarembski	0:01f31e923fe2	2466	/! @name SC - MCG Status and Control Register /
Pawel Zarembski	0:01f31e923fe2	2467	#define MCG_SC_LOCS0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2468	#define MCG_SC_LOCS0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2469	#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
Pawel Zarembski	0:01f31e923fe2	2470	#define MCG_SC_FCRDIV_MASK (0xEU)
Pawel Zarembski	0:01f31e923fe2	2471	#define MCG_SC_FCRDIV_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2472	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
Pawel Zarembski	0:01f31e923fe2	2473	#define MCG_SC_FLTPRSRV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	2474	#define MCG_SC_FLTPRSRV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	2475	#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
Pawel Zarembski	0:01f31e923fe2	2476	#define MCG_SC_ATMF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2477	#define MCG_SC_ATMF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2478	#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
Pawel Zarembski	0:01f31e923fe2	2479	#define MCG_SC_ATMS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2480	#define MCG_SC_ATMS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2481	#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
Pawel Zarembski	0:01f31e923fe2	2482	#define MCG_SC_ATME_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2483	#define MCG_SC_ATME_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2484	#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
Pawel Zarembski	0:01f31e923fe2	2485
Pawel Zarembski	0:01f31e923fe2	2486	/! @name ATCVH - MCG Auto Trim Compare Value High Register /
Pawel Zarembski	0:01f31e923fe2	2487	#define MCG_ATCVH_ATCVH_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2488	#define MCG_ATCVH_ATCVH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2489	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
Pawel Zarembski	0:01f31e923fe2	2490
Pawel Zarembski	0:01f31e923fe2	2491	/! @name ATCVL - MCG Auto Trim Compare Value Low Register /
Pawel Zarembski	0:01f31e923fe2	2492	#define MCG_ATCVL_ATCVL_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2493	#define MCG_ATCVL_ATCVL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2494	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
Pawel Zarembski	0:01f31e923fe2	2495
Pawel Zarembski	0:01f31e923fe2	2496	/! @name C7 - MCG Control 7 Register /
Pawel Zarembski	0:01f31e923fe2	2497	#define MCG_C7_OSCSEL_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2498	#define MCG_C7_OSCSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2499	#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	2500
Pawel Zarembski	0:01f31e923fe2	2501	/! @name C8 - MCG Control 8 Register /
Pawel Zarembski	0:01f31e923fe2	2502	#define MCG_C8_LOLRE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2503	#define MCG_C8_LOLRE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2504	#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
Pawel Zarembski	0:01f31e923fe2	2505
Pawel Zarembski	0:01f31e923fe2	2506
Pawel Zarembski	0:01f31e923fe2	2507	/*!
Pawel Zarembski	0:01f31e923fe2	2508	* @}
Pawel Zarembski	0:01f31e923fe2	2509	/ / end of group MCG_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2510
Pawel Zarembski	0:01f31e923fe2	2511
Pawel Zarembski	0:01f31e923fe2	2512	/* MCG - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2513	/** Peripheral MCG base address */
Pawel Zarembski	0:01f31e923fe2	2514	#define MCG_BASE (0x40064000u)
Pawel Zarembski	0:01f31e923fe2	2515	/** Peripheral MCG base pointer */
Pawel Zarembski	0:01f31e923fe2	2516	#define MCG ((MCG_Type *)MCG_BASE)
Pawel Zarembski	0:01f31e923fe2	2517	/** Array initializer of MCG peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2518	#define MCG_BASE_ADDRS { MCG_BASE }
Pawel Zarembski	0:01f31e923fe2	2519	/** Array initializer of MCG peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2520	#define MCG_BASE_PTRS { MCG }
Pawel Zarembski	0:01f31e923fe2	2521	/** Interrupt vectors for the MCG peripheral type */
Pawel Zarembski	0:01f31e923fe2	2522	#define MCG_IRQS { MCG_IRQn }
Pawel Zarembski	0:01f31e923fe2	2523	/* MCG C2[EREFS] backward compatibility */
Pawel Zarembski	0:01f31e923fe2	2524	#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
Pawel Zarembski	0:01f31e923fe2	2525	#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
Pawel Zarembski	0:01f31e923fe2	2526	#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
Pawel Zarembski	0:01f31e923fe2	2527	#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
Pawel Zarembski	0:01f31e923fe2	2528
Pawel Zarembski	0:01f31e923fe2	2529	/* MCG C2[HGO] backward compatibility */
Pawel Zarembski	0:01f31e923fe2	2530	#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
Pawel Zarembski	0:01f31e923fe2	2531	#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
Pawel Zarembski	0:01f31e923fe2	2532	#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
Pawel Zarembski	0:01f31e923fe2	2533	#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
Pawel Zarembski	0:01f31e923fe2	2534
Pawel Zarembski	0:01f31e923fe2	2535	/* MCG C2[RANGE] backward compatibility */
Pawel Zarembski	0:01f31e923fe2	2536	#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
Pawel Zarembski	0:01f31e923fe2	2537	#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
Pawel Zarembski	0:01f31e923fe2	2538	#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
Pawel Zarembski	0:01f31e923fe2	2539	#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
Pawel Zarembski	0:01f31e923fe2	2540
Pawel Zarembski	0:01f31e923fe2	2541
Pawel Zarembski	0:01f31e923fe2	2542	/*!
Pawel Zarembski	0:01f31e923fe2	2543	* @}
Pawel Zarembski	0:01f31e923fe2	2544	/ / end of group MCG_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2545
Pawel Zarembski	0:01f31e923fe2	2546
Pawel Zarembski	0:01f31e923fe2	2547	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2548	-- MCM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2549	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2550
Pawel Zarembski	0:01f31e923fe2	2551	/*!
Pawel Zarembski	0:01f31e923fe2	2552	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2553	* @{
Pawel Zarembski	0:01f31e923fe2	2554	*/
Pawel Zarembski	0:01f31e923fe2	2555
Pawel Zarembski	0:01f31e923fe2	2556	/** MCM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2557	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2558	uint8_t RESERVED_0[8];
Pawel Zarembski	0:01f31e923fe2	2559	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2560	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	2561	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	2562	uint8_t RESERVED_1[48];
Pawel Zarembski	0:01f31e923fe2	2563	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
Pawel Zarembski	0:01f31e923fe2	2564	} MCM_Type;
Pawel Zarembski	0:01f31e923fe2	2565
Pawel Zarembski	0:01f31e923fe2	2566	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2567	-- MCM Register Masks
Pawel Zarembski	0:01f31e923fe2	2568	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2569
Pawel Zarembski	0:01f31e923fe2	2570	/*!
Pawel Zarembski	0:01f31e923fe2	2571	* @addtogroup MCM_Register_Masks MCM Register Masks
Pawel Zarembski	0:01f31e923fe2	2572	* @{
Pawel Zarembski	0:01f31e923fe2	2573	*/
Pawel Zarembski	0:01f31e923fe2	2574
Pawel Zarembski	0:01f31e923fe2	2575	/! @name PLASC - Crossbar Switch (AXBS) Slave Configuration /
Pawel Zarembski	0:01f31e923fe2	2576	#define MCM_PLASC_ASC_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2577	#define MCM_PLASC_ASC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2578	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
Pawel Zarembski	0:01f31e923fe2	2579
Pawel Zarembski	0:01f31e923fe2	2580	/! @name PLAMC - Crossbar Switch (AXBS) Master Configuration /
Pawel Zarembski	0:01f31e923fe2	2581	#define MCM_PLAMC_AMC_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	2582	#define MCM_PLAMC_AMC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2583	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
Pawel Zarembski	0:01f31e923fe2	2584
Pawel Zarembski	0:01f31e923fe2	2585	/! @name PLACR - Platform Control Register /
Pawel Zarembski	0:01f31e923fe2	2586	#define MCM_PLACR_ARB_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2587	#define MCM_PLACR_ARB_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2588	#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
Pawel Zarembski	0:01f31e923fe2	2589	#define MCM_PLACR_CFCC_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	2590	#define MCM_PLACR_CFCC_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	2591	#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
Pawel Zarembski	0:01f31e923fe2	2592	#define MCM_PLACR_DFCDA_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	2593	#define MCM_PLACR_DFCDA_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	2594	#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
Pawel Zarembski	0:01f31e923fe2	2595	#define MCM_PLACR_DFCIC_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	2596	#define MCM_PLACR_DFCIC_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	2597	#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
Pawel Zarembski	0:01f31e923fe2	2598	#define MCM_PLACR_DFCC_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	2599	#define MCM_PLACR_DFCC_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	2600	#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
Pawel Zarembski	0:01f31e923fe2	2601	#define MCM_PLACR_EFDS_MASK (0x4000U)
Pawel Zarembski	0:01f31e923fe2	2602	#define MCM_PLACR_EFDS_SHIFT (14U)
Pawel Zarembski	0:01f31e923fe2	2603	#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
Pawel Zarembski	0:01f31e923fe2	2604	#define MCM_PLACR_DFCS_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	2605	#define MCM_PLACR_DFCS_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	2606	#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
Pawel Zarembski	0:01f31e923fe2	2607	#define MCM_PLACR_ESFC_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	2608	#define MCM_PLACR_ESFC_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	2609	#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
Pawel Zarembski	0:01f31e923fe2	2610
Pawel Zarembski	0:01f31e923fe2	2611	/! @name CPO - Compute Operation Control Register /
Pawel Zarembski	0:01f31e923fe2	2612	#define MCM_CPO_CPOREQ_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2613	#define MCM_CPO_CPOREQ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2614	#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
Pawel Zarembski	0:01f31e923fe2	2615	#define MCM_CPO_CPOACK_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2616	#define MCM_CPO_CPOACK_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2617	#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
Pawel Zarembski	0:01f31e923fe2	2618	#define MCM_CPO_CPOWOI_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2619	#define MCM_CPO_CPOWOI_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2620	#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
Pawel Zarembski	0:01f31e923fe2	2621
Pawel Zarembski	0:01f31e923fe2	2622
Pawel Zarembski	0:01f31e923fe2	2623	/*!
Pawel Zarembski	0:01f31e923fe2	2624	* @}
Pawel Zarembski	0:01f31e923fe2	2625	/ / end of group MCM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2626
Pawel Zarembski	0:01f31e923fe2	2627
Pawel Zarembski	0:01f31e923fe2	2628	/* MCM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2629	/** Peripheral MCM base address */
Pawel Zarembski	0:01f31e923fe2	2630	#define MCM_BASE (0xF0003000u)
Pawel Zarembski	0:01f31e923fe2	2631	/** Peripheral MCM base pointer */
Pawel Zarembski	0:01f31e923fe2	2632	#define MCM ((MCM_Type *)MCM_BASE)
Pawel Zarembski	0:01f31e923fe2	2633	/** Array initializer of MCM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2634	#define MCM_BASE_ADDRS { MCM_BASE }
Pawel Zarembski	0:01f31e923fe2	2635	/** Array initializer of MCM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2636	#define MCM_BASE_PTRS { MCM }
Pawel Zarembski	0:01f31e923fe2	2637
Pawel Zarembski	0:01f31e923fe2	2638	/*!
Pawel Zarembski	0:01f31e923fe2	2639	* @}
Pawel Zarembski	0:01f31e923fe2	2640	/ / end of group MCM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2641
Pawel Zarembski	0:01f31e923fe2	2642
Pawel Zarembski	0:01f31e923fe2	2643	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2644	-- MTB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2645	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2646
Pawel Zarembski	0:01f31e923fe2	2647	/*!
Pawel Zarembski	0:01f31e923fe2	2648	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2649	* @{
Pawel Zarembski	0:01f31e923fe2	2650	*/
Pawel Zarembski	0:01f31e923fe2	2651
Pawel Zarembski	0:01f31e923fe2	2652	/** MTB - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2653	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2654	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2655	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2656	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	2657	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	2658	uint8_t RESERVED_0[3824];
Pawel Zarembski	0:01f31e923fe2	2659	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
Pawel Zarembski	0:01f31e923fe2	2660	uint8_t RESERVED_1[156];
Pawel Zarembski	0:01f31e923fe2	2661	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
Pawel Zarembski	0:01f31e923fe2	2662	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
Pawel Zarembski	0:01f31e923fe2	2663	uint8_t RESERVED_2[8];
Pawel Zarembski	0:01f31e923fe2	2664	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
Pawel Zarembski	0:01f31e923fe2	2665	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
Pawel Zarembski	0:01f31e923fe2	2666	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
Pawel Zarembski	0:01f31e923fe2	2667	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
Pawel Zarembski	0:01f31e923fe2	2668	uint8_t RESERVED_3[8];
Pawel Zarembski	0:01f31e923fe2	2669	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
Pawel Zarembski	0:01f31e923fe2	2670	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
Pawel Zarembski	0:01f31e923fe2	2671	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
Pawel Zarembski	0:01f31e923fe2	2672	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
Pawel Zarembski	0:01f31e923fe2	2673	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
Pawel Zarembski	0:01f31e923fe2	2674	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
Pawel Zarembski	0:01f31e923fe2	2675	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
Pawel Zarembski	0:01f31e923fe2	2676	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
Pawel Zarembski	0:01f31e923fe2	2677	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
Pawel Zarembski	0:01f31e923fe2	2678	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
Pawel Zarembski	0:01f31e923fe2	2679	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2680	} MTB_Type;
Pawel Zarembski	0:01f31e923fe2	2681
Pawel Zarembski	0:01f31e923fe2	2682	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2683	-- MTB Register Masks
Pawel Zarembski	0:01f31e923fe2	2684	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2685
Pawel Zarembski	0:01f31e923fe2	2686	/*!
Pawel Zarembski	0:01f31e923fe2	2687	* @addtogroup MTB_Register_Masks MTB Register Masks
Pawel Zarembski	0:01f31e923fe2	2688	* @{
Pawel Zarembski	0:01f31e923fe2	2689	*/
Pawel Zarembski	0:01f31e923fe2	2690
Pawel Zarembski	0:01f31e923fe2	2691	/! @name POSITION - MTB Position Register /
Pawel Zarembski	0:01f31e923fe2	2692	#define MTB_POSITION_WRAP_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2693	#define MTB_POSITION_WRAP_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2694	#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
Pawel Zarembski	0:01f31e923fe2	2695	#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
Pawel Zarembski	0:01f31e923fe2	2696	#define MTB_POSITION_POINTER_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2697	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
Pawel Zarembski	0:01f31e923fe2	2698
Pawel Zarembski	0:01f31e923fe2	2699	/! @name MASTER - MTB Master Register /
Pawel Zarembski	0:01f31e923fe2	2700	#define MTB_MASTER_MASK_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	2701	#define MTB_MASTER_MASK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2702	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
Pawel Zarembski	0:01f31e923fe2	2703	#define MTB_MASTER_TSTARTEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	2704	#define MTB_MASTER_TSTARTEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	2705	#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2706	#define MTB_MASTER_TSTOPEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	2707	#define MTB_MASTER_TSTOPEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	2708	#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	2709	#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	2710	#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	2711	#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
Pawel Zarembski	0:01f31e923fe2	2712	#define MTB_MASTER_RAMPRIV_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	2713	#define MTB_MASTER_RAMPRIV_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2714	#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
Pawel Zarembski	0:01f31e923fe2	2715	#define MTB_MASTER_HALTREQ_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	2716	#define MTB_MASTER_HALTREQ_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	2717	#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
Pawel Zarembski	0:01f31e923fe2	2718	#define MTB_MASTER_EN_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	2719	#define MTB_MASTER_EN_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	2720	#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
Pawel Zarembski	0:01f31e923fe2	2721
Pawel Zarembski	0:01f31e923fe2	2722	/! @name FLOW - MTB Flow Register /
Pawel Zarembski	0:01f31e923fe2	2723	#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2724	#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2725	#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
Pawel Zarembski	0:01f31e923fe2	2726	#define MTB_FLOW_AUTOHALT_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2727	#define MTB_FLOW_AUTOHALT_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2728	#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
Pawel Zarembski	0:01f31e923fe2	2729	#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
Pawel Zarembski	0:01f31e923fe2	2730	#define MTB_FLOW_WATERMARK_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2731	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
Pawel Zarembski	0:01f31e923fe2	2732
Pawel Zarembski	0:01f31e923fe2	2733	/! @name BASE - MTB Base Register /
Pawel Zarembski	0:01f31e923fe2	2734	#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2735	#define MTB_BASE_BASEADDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2736	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
Pawel Zarembski	0:01f31e923fe2	2737
Pawel Zarembski	0:01f31e923fe2	2738	/! @name MODECTRL - Integration Mode Control Register /
Pawel Zarembski	0:01f31e923fe2	2739	#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2740	#define MTB_MODECTRL_MODECTRL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2741	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
Pawel Zarembski	0:01f31e923fe2	2742
Pawel Zarembski	0:01f31e923fe2	2743	/! @name TAGSET - Claim TAG Set Register /
Pawel Zarembski	0:01f31e923fe2	2744	#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2745	#define MTB_TAGSET_TAGSET_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2746	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
Pawel Zarembski	0:01f31e923fe2	2747
Pawel Zarembski	0:01f31e923fe2	2748	/! @name TAGCLEAR - Claim TAG Clear Register /
Pawel Zarembski	0:01f31e923fe2	2749	#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2750	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2751	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
Pawel Zarembski	0:01f31e923fe2	2752
Pawel Zarembski	0:01f31e923fe2	2753	/! @name LOCKACCESS - Lock Access Register /
Pawel Zarembski	0:01f31e923fe2	2754	#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2755	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2756	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
Pawel Zarembski	0:01f31e923fe2	2757
Pawel Zarembski	0:01f31e923fe2	2758	/! @name LOCKSTAT - Lock Status Register /
Pawel Zarembski	0:01f31e923fe2	2759	#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2760	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2761	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
Pawel Zarembski	0:01f31e923fe2	2762
Pawel Zarembski	0:01f31e923fe2	2763	/! @name AUTHSTAT - Authentication Status Register /
Pawel Zarembski	0:01f31e923fe2	2764	#define MTB_AUTHSTAT_BIT0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2765	#define MTB_AUTHSTAT_BIT0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2766	#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
Pawel Zarembski	0:01f31e923fe2	2767	#define MTB_AUTHSTAT_BIT1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2768	#define MTB_AUTHSTAT_BIT1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2769	#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
Pawel Zarembski	0:01f31e923fe2	2770	#define MTB_AUTHSTAT_BIT2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	2771	#define MTB_AUTHSTAT_BIT2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	2772	#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
Pawel Zarembski	0:01f31e923fe2	2773	#define MTB_AUTHSTAT_BIT3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	2774	#define MTB_AUTHSTAT_BIT3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	2775	#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
Pawel Zarembski	0:01f31e923fe2	2776
Pawel Zarembski	0:01f31e923fe2	2777	/! @name DEVICEARCH - Device Architecture Register /
Pawel Zarembski	0:01f31e923fe2	2778	#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2779	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2780	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
Pawel Zarembski	0:01f31e923fe2	2781
Pawel Zarembski	0:01f31e923fe2	2782	/! @name DEVICECFG - Device Configuration Register /
Pawel Zarembski	0:01f31e923fe2	2783	#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2784	#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2785	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
Pawel Zarembski	0:01f31e923fe2	2786
Pawel Zarembski	0:01f31e923fe2	2787	/! @name DEVICETYPID - Device Type Identifier Register /
Pawel Zarembski	0:01f31e923fe2	2788	#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2789	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2790	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
Pawel Zarembski	0:01f31e923fe2	2791
Pawel Zarembski	0:01f31e923fe2	2792	/! @name PERIPHID4 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2793	#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2794	#define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2795	#define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2796
Pawel Zarembski	0:01f31e923fe2	2797	/! @name PERIPHID5 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2798	#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2799	#define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2800	#define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2801
Pawel Zarembski	0:01f31e923fe2	2802	/! @name PERIPHID6 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2803	#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2804	#define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2805	#define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2806
Pawel Zarembski	0:01f31e923fe2	2807	/! @name PERIPHID7 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2808	#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2809	#define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2810	#define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2811
Pawel Zarembski	0:01f31e923fe2	2812	/! @name PERIPHID0 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2813	#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2814	#define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2815	#define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2816
Pawel Zarembski	0:01f31e923fe2	2817	/! @name PERIPHID1 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2818	#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2819	#define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2820	#define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2821
Pawel Zarembski	0:01f31e923fe2	2822	/! @name PERIPHID2 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2823	#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2824	#define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2825	#define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2826
Pawel Zarembski	0:01f31e923fe2	2827	/! @name PERIPHID3 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2828	#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2829	#define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2830	#define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2831
Pawel Zarembski	0:01f31e923fe2	2832	/! @name COMPID - Component ID Register /
Pawel Zarembski	0:01f31e923fe2	2833	#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2834	#define MTB_COMPID_COMPID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2835	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
Pawel Zarembski	0:01f31e923fe2	2836
Pawel Zarembski	0:01f31e923fe2	2837	/* The count of MTB_COMPID */
Pawel Zarembski	0:01f31e923fe2	2838	#define MTB_COMPID_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	2839
Pawel Zarembski	0:01f31e923fe2	2840
Pawel Zarembski	0:01f31e923fe2	2841	/*!
Pawel Zarembski	0:01f31e923fe2	2842	* @}
Pawel Zarembski	0:01f31e923fe2	2843	/ / end of group MTB_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	2844
Pawel Zarembski	0:01f31e923fe2	2845
Pawel Zarembski	0:01f31e923fe2	2846	/* MTB - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	2847	/** Peripheral MTB base address */
Pawel Zarembski	0:01f31e923fe2	2848	#define MTB_BASE (0xF0000000u)
Pawel Zarembski	0:01f31e923fe2	2849	/** Peripheral MTB base pointer */
Pawel Zarembski	0:01f31e923fe2	2850	#define MTB ((MTB_Type *)MTB_BASE)
Pawel Zarembski	0:01f31e923fe2	2851	/** Array initializer of MTB peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	2852	#define MTB_BASE_ADDRS { MTB_BASE }
Pawel Zarembski	0:01f31e923fe2	2853	/** Array initializer of MTB peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	2854	#define MTB_BASE_PTRS { MTB }
Pawel Zarembski	0:01f31e923fe2	2855
Pawel Zarembski	0:01f31e923fe2	2856	/*!
Pawel Zarembski	0:01f31e923fe2	2857	* @}
Pawel Zarembski	0:01f31e923fe2	2858	/ / end of group MTB_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	2859
Pawel Zarembski	0:01f31e923fe2	2860
Pawel Zarembski	0:01f31e923fe2	2861	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2862	-- MTBDWT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2863	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2864
Pawel Zarembski	0:01f31e923fe2	2865	/*!
Pawel Zarembski	0:01f31e923fe2	2866	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	2867	* @{
Pawel Zarembski	0:01f31e923fe2	2868	*/
Pawel Zarembski	0:01f31e923fe2	2869
Pawel Zarembski	0:01f31e923fe2	2870	/** MTBDWT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	2871	typedef struct {
Pawel Zarembski	0:01f31e923fe2	2872	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	2873	uint8_t RESERVED_0[28];
Pawel Zarembski	0:01f31e923fe2	2874	struct { /* offset: 0x20, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	2875	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	2876	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	2877	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	2878	uint8_t RESERVED_0[4];
Pawel Zarembski	0:01f31e923fe2	2879	} COMPARATOR[2];
Pawel Zarembski	0:01f31e923fe2	2880	uint8_t RESERVED_1[448];
Pawel Zarembski	0:01f31e923fe2	2881	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
Pawel Zarembski	0:01f31e923fe2	2882	uint8_t RESERVED_2[3524];
Pawel Zarembski	0:01f31e923fe2	2883	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
Pawel Zarembski	0:01f31e923fe2	2884	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
Pawel Zarembski	0:01f31e923fe2	2885	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
Pawel Zarembski	0:01f31e923fe2	2886	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
Pawel Zarembski	0:01f31e923fe2	2887	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
Pawel Zarembski	0:01f31e923fe2	2888	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
Pawel Zarembski	0:01f31e923fe2	2889	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
Pawel Zarembski	0:01f31e923fe2	2890	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
Pawel Zarembski	0:01f31e923fe2	2891	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
Pawel Zarembski	0:01f31e923fe2	2892	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
Pawel Zarembski	0:01f31e923fe2	2893	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	2894	} MTBDWT_Type;
Pawel Zarembski	0:01f31e923fe2	2895
Pawel Zarembski	0:01f31e923fe2	2896	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	2897	-- MTBDWT Register Masks
Pawel Zarembski	0:01f31e923fe2	2898	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	2899
Pawel Zarembski	0:01f31e923fe2	2900	/*!
Pawel Zarembski	0:01f31e923fe2	2901	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
Pawel Zarembski	0:01f31e923fe2	2902	* @{
Pawel Zarembski	0:01f31e923fe2	2903	*/
Pawel Zarembski	0:01f31e923fe2	2904
Pawel Zarembski	0:01f31e923fe2	2905	/! @name CTRL - MTB DWT Control Register /
Pawel Zarembski	0:01f31e923fe2	2906	#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2907	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2908	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
Pawel Zarembski	0:01f31e923fe2	2909	#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	2910	#define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	2911	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
Pawel Zarembski	0:01f31e923fe2	2912
Pawel Zarembski	0:01f31e923fe2	2913	/! @name COMP - MTB_DWT Comparator Register /
Pawel Zarembski	0:01f31e923fe2	2914	#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2915	#define MTBDWT_COMP_COMP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2916	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
Pawel Zarembski	0:01f31e923fe2	2917
Pawel Zarembski	0:01f31e923fe2	2918	/* The count of MTBDWT_COMP */
Pawel Zarembski	0:01f31e923fe2	2919	#define MTBDWT_COMP_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	2920
Pawel Zarembski	0:01f31e923fe2	2921	/! @name MASK - MTB_DWT Comparator Mask Register /
Pawel Zarembski	0:01f31e923fe2	2922	#define MTBDWT_MASK_MASK_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	2923	#define MTBDWT_MASK_MASK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2924	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
Pawel Zarembski	0:01f31e923fe2	2925
Pawel Zarembski	0:01f31e923fe2	2926	/* The count of MTBDWT_MASK */
Pawel Zarembski	0:01f31e923fe2	2927	#define MTBDWT_MASK_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	2928
Pawel Zarembski	0:01f31e923fe2	2929	/! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 /
Pawel Zarembski	0:01f31e923fe2	2930	#define MTBDWT_FCT_FUNCTION_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	2931	#define MTBDWT_FCT_FUNCTION_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2932	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
Pawel Zarembski	0:01f31e923fe2	2933	#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	2934	#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	2935	#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
Pawel Zarembski	0:01f31e923fe2	2936	#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
Pawel Zarembski	0:01f31e923fe2	2937	#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	2938	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	2939	#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	2940	#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	2941	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
Pawel Zarembski	0:01f31e923fe2	2942	#define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	2943	#define MTBDWT_FCT_MATCHED_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	2944	#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
Pawel Zarembski	0:01f31e923fe2	2945
Pawel Zarembski	0:01f31e923fe2	2946	/* The count of MTBDWT_FCT */
Pawel Zarembski	0:01f31e923fe2	2947	#define MTBDWT_FCT_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	2948
Pawel Zarembski	0:01f31e923fe2	2949	/! @name TBCTRL - MTB_DWT Trace Buffer Control Register /
Pawel Zarembski	0:01f31e923fe2	2950	#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	2951	#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2952	#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
Pawel Zarembski	0:01f31e923fe2	2953	#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	2954	#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	2955	#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
Pawel Zarembski	0:01f31e923fe2	2956	#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	2957	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	2958	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
Pawel Zarembski	0:01f31e923fe2	2959
Pawel Zarembski	0:01f31e923fe2	2960	/! @name DEVICECFG - Device Configuration Register /
Pawel Zarembski	0:01f31e923fe2	2961	#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2962	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2963	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
Pawel Zarembski	0:01f31e923fe2	2964
Pawel Zarembski	0:01f31e923fe2	2965	/! @name DEVICETYPID - Device Type Identifier Register /
Pawel Zarembski	0:01f31e923fe2	2966	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2967	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2968	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
Pawel Zarembski	0:01f31e923fe2	2969
Pawel Zarembski	0:01f31e923fe2	2970	/! @name PERIPHID4 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2971	#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2972	#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2973	#define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2974
Pawel Zarembski	0:01f31e923fe2	2975	/! @name PERIPHID5 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2976	#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2977	#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2978	#define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2979
Pawel Zarembski	0:01f31e923fe2	2980	/! @name PERIPHID6 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2981	#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2982	#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2983	#define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2984
Pawel Zarembski	0:01f31e923fe2	2985	/! @name PERIPHID7 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2986	#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2987	#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2988	#define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2989
Pawel Zarembski	0:01f31e923fe2	2990	/! @name PERIPHID0 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2991	#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2992	#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2993	#define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2994
Pawel Zarembski	0:01f31e923fe2	2995	/! @name PERIPHID1 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	2996	#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	2997	#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	2998	#define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	2999
Pawel Zarembski	0:01f31e923fe2	3000	/! @name PERIPHID2 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3001	#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3002	#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3003	#define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3004
Pawel Zarembski	0:01f31e923fe2	3005	/! @name PERIPHID3 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3006	#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3007	#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3008	#define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3009
Pawel Zarembski	0:01f31e923fe2	3010	/! @name COMPID - Component ID Register /
Pawel Zarembski	0:01f31e923fe2	3011	#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3012	#define MTBDWT_COMPID_COMPID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3013	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
Pawel Zarembski	0:01f31e923fe2	3014
Pawel Zarembski	0:01f31e923fe2	3015	/* The count of MTBDWT_COMPID */
Pawel Zarembski	0:01f31e923fe2	3016	#define MTBDWT_COMPID_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	3017
Pawel Zarembski	0:01f31e923fe2	3018
Pawel Zarembski	0:01f31e923fe2	3019	/*!
Pawel Zarembski	0:01f31e923fe2	3020	* @}
Pawel Zarembski	0:01f31e923fe2	3021	/ / end of group MTBDWT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3022
Pawel Zarembski	0:01f31e923fe2	3023
Pawel Zarembski	0:01f31e923fe2	3024	/* MTBDWT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3025	/** Peripheral MTBDWT base address */
Pawel Zarembski	0:01f31e923fe2	3026	#define MTBDWT_BASE (0xF0001000u)
Pawel Zarembski	0:01f31e923fe2	3027	/** Peripheral MTBDWT base pointer */
Pawel Zarembski	0:01f31e923fe2	3028	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
Pawel Zarembski	0:01f31e923fe2	3029	/** Array initializer of MTBDWT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3030	#define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
Pawel Zarembski	0:01f31e923fe2	3031	/** Array initializer of MTBDWT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3032	#define MTBDWT_BASE_PTRS { MTBDWT }
Pawel Zarembski	0:01f31e923fe2	3033
Pawel Zarembski	0:01f31e923fe2	3034	/*!
Pawel Zarembski	0:01f31e923fe2	3035	* @}
Pawel Zarembski	0:01f31e923fe2	3036	/ / end of group MTBDWT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3037
Pawel Zarembski	0:01f31e923fe2	3038
Pawel Zarembski	0:01f31e923fe2	3039	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3040	-- NV Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3041	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3042
Pawel Zarembski	0:01f31e923fe2	3043	/*!
Pawel Zarembski	0:01f31e923fe2	3044	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3045	* @{
Pawel Zarembski	0:01f31e923fe2	3046	*/
Pawel Zarembski	0:01f31e923fe2	3047
Pawel Zarembski	0:01f31e923fe2	3048	/** NV - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3049	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3050	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3051	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	3052	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	3053	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	3054	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3055	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	3056	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	3057	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	3058	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	3059	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	3060	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	3061	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	3062	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	3063	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
Pawel Zarembski	0:01f31e923fe2	3064	} NV_Type;
Pawel Zarembski	0:01f31e923fe2	3065
Pawel Zarembski	0:01f31e923fe2	3066	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3067	-- NV Register Masks
Pawel Zarembski	0:01f31e923fe2	3068	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3069
Pawel Zarembski	0:01f31e923fe2	3070	/*!
Pawel Zarembski	0:01f31e923fe2	3071	* @addtogroup NV_Register_Masks NV Register Masks
Pawel Zarembski	0:01f31e923fe2	3072	* @{
Pawel Zarembski	0:01f31e923fe2	3073	*/
Pawel Zarembski	0:01f31e923fe2	3074
Pawel Zarembski	0:01f31e923fe2	3075	/! @name BACKKEY3 - Backdoor Comparison Key 3. /
Pawel Zarembski	0:01f31e923fe2	3076	#define NV_BACKKEY3_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3077	#define NV_BACKKEY3_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3078	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3079
Pawel Zarembski	0:01f31e923fe2	3080	/! @name BACKKEY2 - Backdoor Comparison Key 2. /
Pawel Zarembski	0:01f31e923fe2	3081	#define NV_BACKKEY2_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3082	#define NV_BACKKEY2_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3083	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3084
Pawel Zarembski	0:01f31e923fe2	3085	/! @name BACKKEY1 - Backdoor Comparison Key 1. /
Pawel Zarembski	0:01f31e923fe2	3086	#define NV_BACKKEY1_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3087	#define NV_BACKKEY1_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3088	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3089
Pawel Zarembski	0:01f31e923fe2	3090	/! @name BACKKEY0 - Backdoor Comparison Key 0. /
Pawel Zarembski	0:01f31e923fe2	3091	#define NV_BACKKEY0_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3092	#define NV_BACKKEY0_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3093	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3094
Pawel Zarembski	0:01f31e923fe2	3095	/! @name BACKKEY7 - Backdoor Comparison Key 7. /
Pawel Zarembski	0:01f31e923fe2	3096	#define NV_BACKKEY7_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3097	#define NV_BACKKEY7_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3098	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3099
Pawel Zarembski	0:01f31e923fe2	3100	/! @name BACKKEY6 - Backdoor Comparison Key 6. /
Pawel Zarembski	0:01f31e923fe2	3101	#define NV_BACKKEY6_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3102	#define NV_BACKKEY6_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3103	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3104
Pawel Zarembski	0:01f31e923fe2	3105	/! @name BACKKEY5 - Backdoor Comparison Key 5. /
Pawel Zarembski	0:01f31e923fe2	3106	#define NV_BACKKEY5_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3107	#define NV_BACKKEY5_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3108	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3109
Pawel Zarembski	0:01f31e923fe2	3110	/! @name BACKKEY4 - Backdoor Comparison Key 4. /
Pawel Zarembski	0:01f31e923fe2	3111	#define NV_BACKKEY4_KEY_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3112	#define NV_BACKKEY4_KEY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3113	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
Pawel Zarembski	0:01f31e923fe2	3114
Pawel Zarembski	0:01f31e923fe2	3115	/! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register /
Pawel Zarembski	0:01f31e923fe2	3116	#define NV_FPROT3_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3117	#define NV_FPROT3_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3118	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	3119
Pawel Zarembski	0:01f31e923fe2	3120	/! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register /
Pawel Zarembski	0:01f31e923fe2	3121	#define NV_FPROT2_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3122	#define NV_FPROT2_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3123	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	3124
Pawel Zarembski	0:01f31e923fe2	3125	/! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register /
Pawel Zarembski	0:01f31e923fe2	3126	#define NV_FPROT1_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3127	#define NV_FPROT1_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3128	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	3129
Pawel Zarembski	0:01f31e923fe2	3130	/! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register /
Pawel Zarembski	0:01f31e923fe2	3131	#define NV_FPROT0_PROT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3132	#define NV_FPROT0_PROT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3133	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
Pawel Zarembski	0:01f31e923fe2	3134
Pawel Zarembski	0:01f31e923fe2	3135	/! @name FSEC - Non-volatile Flash Security Register /
Pawel Zarembski	0:01f31e923fe2	3136	#define NV_FSEC_SEC_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3137	#define NV_FSEC_SEC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3138	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
Pawel Zarembski	0:01f31e923fe2	3139	#define NV_FSEC_FSLACC_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	3140	#define NV_FSEC_FSLACC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3141	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
Pawel Zarembski	0:01f31e923fe2	3142	#define NV_FSEC_MEEN_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	3143	#define NV_FSEC_MEEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3144	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3145	#define NV_FSEC_KEYEN_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	3146	#define NV_FSEC_KEYEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3147	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3148
Pawel Zarembski	0:01f31e923fe2	3149	/! @name FOPT - Non-volatile Flash Option Register /
Pawel Zarembski	0:01f31e923fe2	3150	#define NV_FOPT_LPBOOT0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3151	#define NV_FOPT_LPBOOT0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3152	#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
Pawel Zarembski	0:01f31e923fe2	3153	#define NV_FOPT_NMI_DIS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3154	#define NV_FOPT_NMI_DIS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3155	#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
Pawel Zarembski	0:01f31e923fe2	3156	#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3157	#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3158	#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
Pawel Zarembski	0:01f31e923fe2	3159	#define NV_FOPT_LPBOOT1_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3160	#define NV_FOPT_LPBOOT1_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3161	#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
Pawel Zarembski	0:01f31e923fe2	3162	#define NV_FOPT_FAST_INIT_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3163	#define NV_FOPT_FAST_INIT_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3164	#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
Pawel Zarembski	0:01f31e923fe2	3165
Pawel Zarembski	0:01f31e923fe2	3166
Pawel Zarembski	0:01f31e923fe2	3167	/*!
Pawel Zarembski	0:01f31e923fe2	3168	* @}
Pawel Zarembski	0:01f31e923fe2	3169	/ / end of group NV_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3170
Pawel Zarembski	0:01f31e923fe2	3171
Pawel Zarembski	0:01f31e923fe2	3172	/* NV - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3173	/** Peripheral FTFA_FlashConfig base address */
Pawel Zarembski	0:01f31e923fe2	3174	#define FTFA_FlashConfig_BASE (0x400u)
Pawel Zarembski	0:01f31e923fe2	3175	/** Peripheral FTFA_FlashConfig base pointer */
Pawel Zarembski	0:01f31e923fe2	3176	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
Pawel Zarembski	0:01f31e923fe2	3177	/** Array initializer of NV peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3178	#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
Pawel Zarembski	0:01f31e923fe2	3179	/** Array initializer of NV peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3180	#define NV_BASE_PTRS { FTFA_FlashConfig }
Pawel Zarembski	0:01f31e923fe2	3181
Pawel Zarembski	0:01f31e923fe2	3182	/*!
Pawel Zarembski	0:01f31e923fe2	3183	* @}
Pawel Zarembski	0:01f31e923fe2	3184	/ / end of group NV_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3185
Pawel Zarembski	0:01f31e923fe2	3186
Pawel Zarembski	0:01f31e923fe2	3187	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3188	-- OSC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3189	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3190
Pawel Zarembski	0:01f31e923fe2	3191	/*!
Pawel Zarembski	0:01f31e923fe2	3192	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3193	* @{
Pawel Zarembski	0:01f31e923fe2	3194	*/
Pawel Zarembski	0:01f31e923fe2	3195
Pawel Zarembski	0:01f31e923fe2	3196	/** OSC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3197	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3198	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3199	} OSC_Type;
Pawel Zarembski	0:01f31e923fe2	3200
Pawel Zarembski	0:01f31e923fe2	3201	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3202	-- OSC Register Masks
Pawel Zarembski	0:01f31e923fe2	3203	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3204
Pawel Zarembski	0:01f31e923fe2	3205	/*!
Pawel Zarembski	0:01f31e923fe2	3206	* @addtogroup OSC_Register_Masks OSC Register Masks
Pawel Zarembski	0:01f31e923fe2	3207	* @{
Pawel Zarembski	0:01f31e923fe2	3208	*/
Pawel Zarembski	0:01f31e923fe2	3209
Pawel Zarembski	0:01f31e923fe2	3210	/! @name CR - OSC Control Register /
Pawel Zarembski	0:01f31e923fe2	3211	#define OSC_CR_SC16P_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3212	#define OSC_CR_SC16P_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3213	#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
Pawel Zarembski	0:01f31e923fe2	3214	#define OSC_CR_SC8P_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3215	#define OSC_CR_SC8P_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3216	#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
Pawel Zarembski	0:01f31e923fe2	3217	#define OSC_CR_SC4P_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3218	#define OSC_CR_SC4P_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3219	#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
Pawel Zarembski	0:01f31e923fe2	3220	#define OSC_CR_SC2P_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3221	#define OSC_CR_SC2P_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3222	#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
Pawel Zarembski	0:01f31e923fe2	3223	#define OSC_CR_EREFSTEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3224	#define OSC_CR_EREFSTEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3225	#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3226	#define OSC_CR_ERCLKEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3227	#define OSC_CR_ERCLKEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3228	#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3229
Pawel Zarembski	0:01f31e923fe2	3230
Pawel Zarembski	0:01f31e923fe2	3231	/*!
Pawel Zarembski	0:01f31e923fe2	3232	* @}
Pawel Zarembski	0:01f31e923fe2	3233	/ / end of group OSC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3234
Pawel Zarembski	0:01f31e923fe2	3235
Pawel Zarembski	0:01f31e923fe2	3236	/* OSC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3237	/** Peripheral OSC0 base address */
Pawel Zarembski	0:01f31e923fe2	3238	#define OSC0_BASE (0x40065000u)
Pawel Zarembski	0:01f31e923fe2	3239	/** Peripheral OSC0 base pointer */
Pawel Zarembski	0:01f31e923fe2	3240	#define OSC0 ((OSC_Type *)OSC0_BASE)
Pawel Zarembski	0:01f31e923fe2	3241	/** Array initializer of OSC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3242	#define OSC_BASE_ADDRS { OSC0_BASE }
Pawel Zarembski	0:01f31e923fe2	3243	/** Array initializer of OSC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3244	#define OSC_BASE_PTRS { OSC0 }
Pawel Zarembski	0:01f31e923fe2	3245
Pawel Zarembski	0:01f31e923fe2	3246	/*!
Pawel Zarembski	0:01f31e923fe2	3247	* @}
Pawel Zarembski	0:01f31e923fe2	3248	/ / end of group OSC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3249
Pawel Zarembski	0:01f31e923fe2	3250
Pawel Zarembski	0:01f31e923fe2	3251	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3252	-- PIT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3253	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3254
Pawel Zarembski	0:01f31e923fe2	3255	/*!
Pawel Zarembski	0:01f31e923fe2	3256	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3257	* @{
Pawel Zarembski	0:01f31e923fe2	3258	*/
Pawel Zarembski	0:01f31e923fe2	3259
Pawel Zarembski	0:01f31e923fe2	3260	/** PIT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3261	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3262	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3263	uint8_t RESERVED_0[220];
Pawel Zarembski	0:01f31e923fe2	3264	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
Pawel Zarembski	0:01f31e923fe2	3265	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
Pawel Zarembski	0:01f31e923fe2	3266	uint8_t RESERVED_1[24];
Pawel Zarembski	0:01f31e923fe2	3267	struct { /* offset: 0x100, array step: 0x10 */
Pawel Zarembski	0:01f31e923fe2	3268	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	3269	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	3270	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	3271	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
Pawel Zarembski	0:01f31e923fe2	3272	} CHANNEL[2];
Pawel Zarembski	0:01f31e923fe2	3273	} PIT_Type;
Pawel Zarembski	0:01f31e923fe2	3274
Pawel Zarembski	0:01f31e923fe2	3275	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3276	-- PIT Register Masks
Pawel Zarembski	0:01f31e923fe2	3277	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3278
Pawel Zarembski	0:01f31e923fe2	3279	/*!
Pawel Zarembski	0:01f31e923fe2	3280	* @addtogroup PIT_Register_Masks PIT Register Masks
Pawel Zarembski	0:01f31e923fe2	3281	* @{
Pawel Zarembski	0:01f31e923fe2	3282	*/
Pawel Zarembski	0:01f31e923fe2	3283
Pawel Zarembski	0:01f31e923fe2	3284	/! @name MCR - PIT Module Control Register /
Pawel Zarembski	0:01f31e923fe2	3285	#define PIT_MCR_FRZ_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3286	#define PIT_MCR_FRZ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3287	#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
Pawel Zarembski	0:01f31e923fe2	3288	#define PIT_MCR_MDIS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3289	#define PIT_MCR_MDIS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3290	#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	3291
Pawel Zarembski	0:01f31e923fe2	3292	/! @name LTMR64H - PIT Upper Lifetime Timer Register /
Pawel Zarembski	0:01f31e923fe2	3293	#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3294	#define PIT_LTMR64H_LTH_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3295	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
Pawel Zarembski	0:01f31e923fe2	3296
Pawel Zarembski	0:01f31e923fe2	3297	/! @name LTMR64L - PIT Lower Lifetime Timer Register /
Pawel Zarembski	0:01f31e923fe2	3298	#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3299	#define PIT_LTMR64L_LTL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3300	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
Pawel Zarembski	0:01f31e923fe2	3301
Pawel Zarembski	0:01f31e923fe2	3302	/! @name LDVAL - Timer Load Value Register /
Pawel Zarembski	0:01f31e923fe2	3303	#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3304	#define PIT_LDVAL_TSV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3305	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
Pawel Zarembski	0:01f31e923fe2	3306
Pawel Zarembski	0:01f31e923fe2	3307	/* The count of PIT_LDVAL */
Pawel Zarembski	0:01f31e923fe2	3308	#define PIT_LDVAL_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3309
Pawel Zarembski	0:01f31e923fe2	3310	/! @name CVAL - Current Timer Value Register /
Pawel Zarembski	0:01f31e923fe2	3311	#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3312	#define PIT_CVAL_TVL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3313	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
Pawel Zarembski	0:01f31e923fe2	3314
Pawel Zarembski	0:01f31e923fe2	3315	/* The count of PIT_CVAL */
Pawel Zarembski	0:01f31e923fe2	3316	#define PIT_CVAL_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3317
Pawel Zarembski	0:01f31e923fe2	3318	/! @name TCTRL - Timer Control Register /
Pawel Zarembski	0:01f31e923fe2	3319	#define PIT_TCTRL_TEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3320	#define PIT_TCTRL_TEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3321	#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3322	#define PIT_TCTRL_TIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3323	#define PIT_TCTRL_TIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3324	#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3325	#define PIT_TCTRL_CHN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3326	#define PIT_TCTRL_CHN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3327	#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
Pawel Zarembski	0:01f31e923fe2	3328
Pawel Zarembski	0:01f31e923fe2	3329	/* The count of PIT_TCTRL */
Pawel Zarembski	0:01f31e923fe2	3330	#define PIT_TCTRL_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3331
Pawel Zarembski	0:01f31e923fe2	3332	/! @name TFLG - Timer Flag Register /
Pawel Zarembski	0:01f31e923fe2	3333	#define PIT_TFLG_TIF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3334	#define PIT_TFLG_TIF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3335	#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
Pawel Zarembski	0:01f31e923fe2	3336
Pawel Zarembski	0:01f31e923fe2	3337	/* The count of PIT_TFLG */
Pawel Zarembski	0:01f31e923fe2	3338	#define PIT_TFLG_COUNT (2U)
Pawel Zarembski	0:01f31e923fe2	3339
Pawel Zarembski	0:01f31e923fe2	3340
Pawel Zarembski	0:01f31e923fe2	3341	/*!
Pawel Zarembski	0:01f31e923fe2	3342	* @}
Pawel Zarembski	0:01f31e923fe2	3343	/ / end of group PIT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3344
Pawel Zarembski	0:01f31e923fe2	3345
Pawel Zarembski	0:01f31e923fe2	3346	/* PIT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3347	/** Peripheral PIT base address */
Pawel Zarembski	0:01f31e923fe2	3348	#define PIT_BASE (0x40037000u)
Pawel Zarembski	0:01f31e923fe2	3349	/** Peripheral PIT base pointer */
Pawel Zarembski	0:01f31e923fe2	3350	#define PIT ((PIT_Type *)PIT_BASE)
Pawel Zarembski	0:01f31e923fe2	3351	/** Array initializer of PIT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3352	#define PIT_BASE_ADDRS { PIT_BASE }
Pawel Zarembski	0:01f31e923fe2	3353	/** Array initializer of PIT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3354	#define PIT_BASE_PTRS { PIT }
Pawel Zarembski	0:01f31e923fe2	3355	/** Interrupt vectors for the PIT peripheral type */
Pawel Zarembski	0:01f31e923fe2	3356	#define PIT_IRQS { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn }
Pawel Zarembski	0:01f31e923fe2	3357
Pawel Zarembski	0:01f31e923fe2	3358	/*!
Pawel Zarembski	0:01f31e923fe2	3359	* @}
Pawel Zarembski	0:01f31e923fe2	3360	/ / end of group PIT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3361
Pawel Zarembski	0:01f31e923fe2	3362
Pawel Zarembski	0:01f31e923fe2	3363	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3364	-- PMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3365	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3366
Pawel Zarembski	0:01f31e923fe2	3367	/*!
Pawel Zarembski	0:01f31e923fe2	3368	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3369	* @{
Pawel Zarembski	0:01f31e923fe2	3370	*/
Pawel Zarembski	0:01f31e923fe2	3371
Pawel Zarembski	0:01f31e923fe2	3372	/** PMC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3373	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3374	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3375	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	3376	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	3377	} PMC_Type;
Pawel Zarembski	0:01f31e923fe2	3378
Pawel Zarembski	0:01f31e923fe2	3379	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3380	-- PMC Register Masks
Pawel Zarembski	0:01f31e923fe2	3381	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3382
Pawel Zarembski	0:01f31e923fe2	3383	/*!
Pawel Zarembski	0:01f31e923fe2	3384	* @addtogroup PMC_Register_Masks PMC Register Masks
Pawel Zarembski	0:01f31e923fe2	3385	* @{
Pawel Zarembski	0:01f31e923fe2	3386	*/
Pawel Zarembski	0:01f31e923fe2	3387
Pawel Zarembski	0:01f31e923fe2	3388	/! @name LVDSC1 - Low Voltage Detect Status And Control 1 register /
Pawel Zarembski	0:01f31e923fe2	3389	#define PMC_LVDSC1_LVDV_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3390	#define PMC_LVDSC1_LVDV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3391	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
Pawel Zarembski	0:01f31e923fe2	3392	#define PMC_LVDSC1_LVDRE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3393	#define PMC_LVDSC1_LVDRE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3394	#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
Pawel Zarembski	0:01f31e923fe2	3395	#define PMC_LVDSC1_LVDIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3396	#define PMC_LVDSC1_LVDIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3397	#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3398	#define PMC_LVDSC1_LVDACK_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3399	#define PMC_LVDSC1_LVDACK_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3400	#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
Pawel Zarembski	0:01f31e923fe2	3401	#define PMC_LVDSC1_LVDF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3402	#define PMC_LVDSC1_LVDF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3403	#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
Pawel Zarembski	0:01f31e923fe2	3404
Pawel Zarembski	0:01f31e923fe2	3405	/! @name LVDSC2 - Low Voltage Detect Status And Control 2 register /
Pawel Zarembski	0:01f31e923fe2	3406	#define PMC_LVDSC2_LVWV_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3407	#define PMC_LVDSC2_LVWV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3408	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
Pawel Zarembski	0:01f31e923fe2	3409	#define PMC_LVDSC2_LVWIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3410	#define PMC_LVDSC2_LVWIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3411	#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3412	#define PMC_LVDSC2_LVWACK_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3413	#define PMC_LVDSC2_LVWACK_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3414	#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
Pawel Zarembski	0:01f31e923fe2	3415	#define PMC_LVDSC2_LVWF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3416	#define PMC_LVDSC2_LVWF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3417	#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
Pawel Zarembski	0:01f31e923fe2	3418
Pawel Zarembski	0:01f31e923fe2	3419	/! @name REGSC - Regulator Status And Control register /
Pawel Zarembski	0:01f31e923fe2	3420	#define PMC_REGSC_BGBE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3421	#define PMC_REGSC_BGBE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3422	#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
Pawel Zarembski	0:01f31e923fe2	3423	#define PMC_REGSC_REGONS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3424	#define PMC_REGSC_REGONS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3425	#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
Pawel Zarembski	0:01f31e923fe2	3426	#define PMC_REGSC_ACKISO_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3427	#define PMC_REGSC_ACKISO_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3428	#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
Pawel Zarembski	0:01f31e923fe2	3429	#define PMC_REGSC_BGEN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3430	#define PMC_REGSC_BGEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3431	#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	3432
Pawel Zarembski	0:01f31e923fe2	3433
Pawel Zarembski	0:01f31e923fe2	3434	/*!
Pawel Zarembski	0:01f31e923fe2	3435	* @}
Pawel Zarembski	0:01f31e923fe2	3436	/ / end of group PMC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3437
Pawel Zarembski	0:01f31e923fe2	3438
Pawel Zarembski	0:01f31e923fe2	3439	/* PMC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3440	/** Peripheral PMC base address */
Pawel Zarembski	0:01f31e923fe2	3441	#define PMC_BASE (0x4007D000u)
Pawel Zarembski	0:01f31e923fe2	3442	/** Peripheral PMC base pointer */
Pawel Zarembski	0:01f31e923fe2	3443	#define PMC ((PMC_Type *)PMC_BASE)
Pawel Zarembski	0:01f31e923fe2	3444	/** Array initializer of PMC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3445	#define PMC_BASE_ADDRS { PMC_BASE }
Pawel Zarembski	0:01f31e923fe2	3446	/** Array initializer of PMC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3447	#define PMC_BASE_PTRS { PMC }
Pawel Zarembski	0:01f31e923fe2	3448	/** Interrupt vectors for the PMC peripheral type */
Pawel Zarembski	0:01f31e923fe2	3449	#define PMC_IRQS { LVD_LVW_IRQn }
Pawel Zarembski	0:01f31e923fe2	3450
Pawel Zarembski	0:01f31e923fe2	3451	/*!
Pawel Zarembski	0:01f31e923fe2	3452	* @}
Pawel Zarembski	0:01f31e923fe2	3453	/ / end of group PMC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3454
Pawel Zarembski	0:01f31e923fe2	3455
Pawel Zarembski	0:01f31e923fe2	3456	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3457	-- PORT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3458	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3459
Pawel Zarembski	0:01f31e923fe2	3460	/*!
Pawel Zarembski	0:01f31e923fe2	3461	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3462	* @{
Pawel Zarembski	0:01f31e923fe2	3463	*/
Pawel Zarembski	0:01f31e923fe2	3464
Pawel Zarembski	0:01f31e923fe2	3465	/** PORT - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3466	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3467	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3468	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	3469	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	3470	uint8_t RESERVED_0[24];
Pawel Zarembski	0:01f31e923fe2	3471	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
Pawel Zarembski	0:01f31e923fe2	3472	} PORT_Type;
Pawel Zarembski	0:01f31e923fe2	3473
Pawel Zarembski	0:01f31e923fe2	3474	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3475	-- PORT Register Masks
Pawel Zarembski	0:01f31e923fe2	3476	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3477
Pawel Zarembski	0:01f31e923fe2	3478	/*!
Pawel Zarembski	0:01f31e923fe2	3479	* @addtogroup PORT_Register_Masks PORT Register Masks
Pawel Zarembski	0:01f31e923fe2	3480	* @{
Pawel Zarembski	0:01f31e923fe2	3481	*/
Pawel Zarembski	0:01f31e923fe2	3482
Pawel Zarembski	0:01f31e923fe2	3483	/! @name PCR - Pin Control Register n /
Pawel Zarembski	0:01f31e923fe2	3484	#define PORT_PCR_PS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3485	#define PORT_PCR_PS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3486	#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
Pawel Zarembski	0:01f31e923fe2	3487	#define PORT_PCR_PE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3488	#define PORT_PCR_PE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3489	#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
Pawel Zarembski	0:01f31e923fe2	3490	#define PORT_PCR_SRE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3491	#define PORT_PCR_SRE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3492	#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
Pawel Zarembski	0:01f31e923fe2	3493	#define PORT_PCR_PFE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3494	#define PORT_PCR_PFE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3495	#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
Pawel Zarembski	0:01f31e923fe2	3496	#define PORT_PCR_DSE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3497	#define PORT_PCR_DSE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3498	#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
Pawel Zarembski	0:01f31e923fe2	3499	#define PORT_PCR_MUX_MASK (0x700U)
Pawel Zarembski	0:01f31e923fe2	3500	#define PORT_PCR_MUX_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3501	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
Pawel Zarembski	0:01f31e923fe2	3502	#define PORT_PCR_IRQC_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	3503	#define PORT_PCR_IRQC_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3504	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
Pawel Zarembski	0:01f31e923fe2	3505	#define PORT_PCR_ISF_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	3506	#define PORT_PCR_ISF_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3507	#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
Pawel Zarembski	0:01f31e923fe2	3508
Pawel Zarembski	0:01f31e923fe2	3509	/* The count of PORT_PCR */
Pawel Zarembski	0:01f31e923fe2	3510	#define PORT_PCR_COUNT (32U)
Pawel Zarembski	0:01f31e923fe2	3511
Pawel Zarembski	0:01f31e923fe2	3512	/! @name GPCLR - Global Pin Control Low Register /
Pawel Zarembski	0:01f31e923fe2	3513	#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	3514	#define PORT_GPCLR_GPWD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3515	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
Pawel Zarembski	0:01f31e923fe2	3516	#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	3517	#define PORT_GPCLR_GPWE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3518	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
Pawel Zarembski	0:01f31e923fe2	3519
Pawel Zarembski	0:01f31e923fe2	3520	/! @name GPCHR - Global Pin Control High Register /
Pawel Zarembski	0:01f31e923fe2	3521	#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	3522	#define PORT_GPCHR_GPWD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3523	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
Pawel Zarembski	0:01f31e923fe2	3524	#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	3525	#define PORT_GPCHR_GPWE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3526	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
Pawel Zarembski	0:01f31e923fe2	3527
Pawel Zarembski	0:01f31e923fe2	3528	/! @name ISFR - Interrupt Status Flag Register /
Pawel Zarembski	0:01f31e923fe2	3529	#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3530	#define PORT_ISFR_ISF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3531	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
Pawel Zarembski	0:01f31e923fe2	3532
Pawel Zarembski	0:01f31e923fe2	3533
Pawel Zarembski	0:01f31e923fe2	3534	/*!
Pawel Zarembski	0:01f31e923fe2	3535	* @}
Pawel Zarembski	0:01f31e923fe2	3536	/ / end of group PORT_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3537
Pawel Zarembski	0:01f31e923fe2	3538
Pawel Zarembski	0:01f31e923fe2	3539	/* PORT - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3540	/** Peripheral PORTA base address */
Pawel Zarembski	0:01f31e923fe2	3541	#define PORTA_BASE (0x40049000u)
Pawel Zarembski	0:01f31e923fe2	3542	/** Peripheral PORTA base pointer */
Pawel Zarembski	0:01f31e923fe2	3543	#define PORTA ((PORT_Type *)PORTA_BASE)
Pawel Zarembski	0:01f31e923fe2	3544	/** Peripheral PORTB base address */
Pawel Zarembski	0:01f31e923fe2	3545	#define PORTB_BASE (0x4004A000u)
Pawel Zarembski	0:01f31e923fe2	3546	/** Peripheral PORTB base pointer */
Pawel Zarembski	0:01f31e923fe2	3547	#define PORTB ((PORT_Type *)PORTB_BASE)
Pawel Zarembski	0:01f31e923fe2	3548	/** Peripheral PORTC base address */
Pawel Zarembski	0:01f31e923fe2	3549	#define PORTC_BASE (0x4004B000u)
Pawel Zarembski	0:01f31e923fe2	3550	/** Peripheral PORTC base pointer */
Pawel Zarembski	0:01f31e923fe2	3551	#define PORTC ((PORT_Type *)PORTC_BASE)
Pawel Zarembski	0:01f31e923fe2	3552	/** Peripheral PORTD base address */
Pawel Zarembski	0:01f31e923fe2	3553	#define PORTD_BASE (0x4004C000u)
Pawel Zarembski	0:01f31e923fe2	3554	/** Peripheral PORTD base pointer */
Pawel Zarembski	0:01f31e923fe2	3555	#define PORTD ((PORT_Type *)PORTD_BASE)
Pawel Zarembski	0:01f31e923fe2	3556	/** Peripheral PORTE base address */
Pawel Zarembski	0:01f31e923fe2	3557	#define PORTE_BASE (0x4004D000u)
Pawel Zarembski	0:01f31e923fe2	3558	/** Peripheral PORTE base pointer */
Pawel Zarembski	0:01f31e923fe2	3559	#define PORTE ((PORT_Type *)PORTE_BASE)
Pawel Zarembski	0:01f31e923fe2	3560	/** Array initializer of PORT peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3561	#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
Pawel Zarembski	0:01f31e923fe2	3562	/** Array initializer of PORT peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3563	#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
Pawel Zarembski	0:01f31e923fe2	3564	/** Interrupt vectors for the PORT peripheral type */
Pawel Zarembski	0:01f31e923fe2	3565	#define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn }
Pawel Zarembski	0:01f31e923fe2	3566
Pawel Zarembski	0:01f31e923fe2	3567	/*!
Pawel Zarembski	0:01f31e923fe2	3568	* @}
Pawel Zarembski	0:01f31e923fe2	3569	/ / end of group PORT_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3570
Pawel Zarembski	0:01f31e923fe2	3571
Pawel Zarembski	0:01f31e923fe2	3572	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3573	-- RCM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3574	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3575
Pawel Zarembski	0:01f31e923fe2	3576	/*!
Pawel Zarembski	0:01f31e923fe2	3577	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3578	* @{
Pawel Zarembski	0:01f31e923fe2	3579	*/
Pawel Zarembski	0:01f31e923fe2	3580
Pawel Zarembski	0:01f31e923fe2	3581	/** RCM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3582	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3583	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3584	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	3585	uint8_t RESERVED_0[2];
Pawel Zarembski	0:01f31e923fe2	3586	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3587	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	3588	} RCM_Type;
Pawel Zarembski	0:01f31e923fe2	3589
Pawel Zarembski	0:01f31e923fe2	3590	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3591	-- RCM Register Masks
Pawel Zarembski	0:01f31e923fe2	3592	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3593
Pawel Zarembski	0:01f31e923fe2	3594	/*!
Pawel Zarembski	0:01f31e923fe2	3595	* @addtogroup RCM_Register_Masks RCM Register Masks
Pawel Zarembski	0:01f31e923fe2	3596	* @{
Pawel Zarembski	0:01f31e923fe2	3597	*/
Pawel Zarembski	0:01f31e923fe2	3598
Pawel Zarembski	0:01f31e923fe2	3599	/! @name SRS0 - System Reset Status Register 0 /
Pawel Zarembski	0:01f31e923fe2	3600	#define RCM_SRS0_WAKEUP_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3601	#define RCM_SRS0_WAKEUP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3602	#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
Pawel Zarembski	0:01f31e923fe2	3603	#define RCM_SRS0_LVD_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3604	#define RCM_SRS0_LVD_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3605	#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
Pawel Zarembski	0:01f31e923fe2	3606	#define RCM_SRS0_LOC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3607	#define RCM_SRS0_LOC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3608	#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
Pawel Zarembski	0:01f31e923fe2	3609	#define RCM_SRS0_LOL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3610	#define RCM_SRS0_LOL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3611	#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
Pawel Zarembski	0:01f31e923fe2	3612	#define RCM_SRS0_WDOG_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3613	#define RCM_SRS0_WDOG_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3614	#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
Pawel Zarembski	0:01f31e923fe2	3615	#define RCM_SRS0_PIN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3616	#define RCM_SRS0_PIN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3617	#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
Pawel Zarembski	0:01f31e923fe2	3618	#define RCM_SRS0_POR_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3619	#define RCM_SRS0_POR_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3620	#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
Pawel Zarembski	0:01f31e923fe2	3621
Pawel Zarembski	0:01f31e923fe2	3622	/! @name SRS1 - System Reset Status Register 1 /
Pawel Zarembski	0:01f31e923fe2	3623	#define RCM_SRS1_LOCKUP_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3624	#define RCM_SRS1_LOCKUP_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3625	#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
Pawel Zarembski	0:01f31e923fe2	3626	#define RCM_SRS1_SW_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3627	#define RCM_SRS1_SW_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3628	#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
Pawel Zarembski	0:01f31e923fe2	3629	#define RCM_SRS1_MDM_AP_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3630	#define RCM_SRS1_MDM_AP_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3631	#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
Pawel Zarembski	0:01f31e923fe2	3632	#define RCM_SRS1_SACKERR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3633	#define RCM_SRS1_SACKERR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3634	#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
Pawel Zarembski	0:01f31e923fe2	3635
Pawel Zarembski	0:01f31e923fe2	3636	/! @name RPFC - Reset Pin Filter Control register /
Pawel Zarembski	0:01f31e923fe2	3637	#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	3638	#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3639	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
Pawel Zarembski	0:01f31e923fe2	3640	#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3641	#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3642	#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
Pawel Zarembski	0:01f31e923fe2	3643
Pawel Zarembski	0:01f31e923fe2	3644	/! @name RPFW - Reset Pin Filter Width register /
Pawel Zarembski	0:01f31e923fe2	3645	#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	3646	#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3647	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	3648
Pawel Zarembski	0:01f31e923fe2	3649
Pawel Zarembski	0:01f31e923fe2	3650	/*!
Pawel Zarembski	0:01f31e923fe2	3651	* @}
Pawel Zarembski	0:01f31e923fe2	3652	/ / end of group RCM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3653
Pawel Zarembski	0:01f31e923fe2	3654
Pawel Zarembski	0:01f31e923fe2	3655	/* RCM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3656	/** Peripheral RCM base address */
Pawel Zarembski	0:01f31e923fe2	3657	#define RCM_BASE (0x4007F000u)
Pawel Zarembski	0:01f31e923fe2	3658	/** Peripheral RCM base pointer */
Pawel Zarembski	0:01f31e923fe2	3659	#define RCM ((RCM_Type *)RCM_BASE)
Pawel Zarembski	0:01f31e923fe2	3660	/** Array initializer of RCM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3661	#define RCM_BASE_ADDRS { RCM_BASE }
Pawel Zarembski	0:01f31e923fe2	3662	/** Array initializer of RCM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3663	#define RCM_BASE_PTRS { RCM }
Pawel Zarembski	0:01f31e923fe2	3664
Pawel Zarembski	0:01f31e923fe2	3665	/*!
Pawel Zarembski	0:01f31e923fe2	3666	* @}
Pawel Zarembski	0:01f31e923fe2	3667	/ / end of group RCM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3668
Pawel Zarembski	0:01f31e923fe2	3669
Pawel Zarembski	0:01f31e923fe2	3670	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3671	-- ROM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3672	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3673
Pawel Zarembski	0:01f31e923fe2	3674	/*!
Pawel Zarembski	0:01f31e923fe2	3675	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3676	* @{
Pawel Zarembski	0:01f31e923fe2	3677	*/
Pawel Zarembski	0:01f31e923fe2	3678
Pawel Zarembski	0:01f31e923fe2	3679	/** ROM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3680	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3681	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3682	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	3683	uint8_t RESERVED_0[4028];
Pawel Zarembski	0:01f31e923fe2	3684	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
Pawel Zarembski	0:01f31e923fe2	3685	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
Pawel Zarembski	0:01f31e923fe2	3686	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
Pawel Zarembski	0:01f31e923fe2	3687	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
Pawel Zarembski	0:01f31e923fe2	3688	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
Pawel Zarembski	0:01f31e923fe2	3689	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
Pawel Zarembski	0:01f31e923fe2	3690	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
Pawel Zarembski	0:01f31e923fe2	3691	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
Pawel Zarembski	0:01f31e923fe2	3692	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
Pawel Zarembski	0:01f31e923fe2	3693	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3694	} ROM_Type;
Pawel Zarembski	0:01f31e923fe2	3695
Pawel Zarembski	0:01f31e923fe2	3696	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3697	-- ROM Register Masks
Pawel Zarembski	0:01f31e923fe2	3698	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3699
Pawel Zarembski	0:01f31e923fe2	3700	/*!
Pawel Zarembski	0:01f31e923fe2	3701	* @addtogroup ROM_Register_Masks ROM Register Masks
Pawel Zarembski	0:01f31e923fe2	3702	* @{
Pawel Zarembski	0:01f31e923fe2	3703	*/
Pawel Zarembski	0:01f31e923fe2	3704
Pawel Zarembski	0:01f31e923fe2	3705	/! @name ENTRY - Entry /
Pawel Zarembski	0:01f31e923fe2	3706	#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3707	#define ROM_ENTRY_ENTRY_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3708	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
Pawel Zarembski	0:01f31e923fe2	3709
Pawel Zarembski	0:01f31e923fe2	3710	/* The count of ROM_ENTRY */
Pawel Zarembski	0:01f31e923fe2	3711	#define ROM_ENTRY_COUNT (3U)
Pawel Zarembski	0:01f31e923fe2	3712
Pawel Zarembski	0:01f31e923fe2	3713	/! @name TABLEMARK - End of Table Marker Register /
Pawel Zarembski	0:01f31e923fe2	3714	#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3715	#define ROM_TABLEMARK_MARK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3716	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
Pawel Zarembski	0:01f31e923fe2	3717
Pawel Zarembski	0:01f31e923fe2	3718	/! @name SYSACCESS - System Access Register /
Pawel Zarembski	0:01f31e923fe2	3719	#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3720	#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3721	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
Pawel Zarembski	0:01f31e923fe2	3722
Pawel Zarembski	0:01f31e923fe2	3723	/! @name PERIPHID4 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3724	#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3725	#define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3726	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3727
Pawel Zarembski	0:01f31e923fe2	3728	/! @name PERIPHID5 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3729	#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3730	#define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3731	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3732
Pawel Zarembski	0:01f31e923fe2	3733	/! @name PERIPHID6 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3734	#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3735	#define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3736	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3737
Pawel Zarembski	0:01f31e923fe2	3738	/! @name PERIPHID7 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3739	#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3740	#define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3741	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3742
Pawel Zarembski	0:01f31e923fe2	3743	/! @name PERIPHID0 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3744	#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3745	#define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3746	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3747
Pawel Zarembski	0:01f31e923fe2	3748	/! @name PERIPHID1 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3749	#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3750	#define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3751	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3752
Pawel Zarembski	0:01f31e923fe2	3753	/! @name PERIPHID2 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3754	#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3755	#define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3756	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3757
Pawel Zarembski	0:01f31e923fe2	3758	/! @name PERIPHID3 - Peripheral ID Register /
Pawel Zarembski	0:01f31e923fe2	3759	#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3760	#define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3761	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
Pawel Zarembski	0:01f31e923fe2	3762
Pawel Zarembski	0:01f31e923fe2	3763	/! @name COMPID - Component ID Register /
Pawel Zarembski	0:01f31e923fe2	3764	#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3765	#define ROM_COMPID_COMPID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3766	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
Pawel Zarembski	0:01f31e923fe2	3767
Pawel Zarembski	0:01f31e923fe2	3768	/* The count of ROM_COMPID */
Pawel Zarembski	0:01f31e923fe2	3769	#define ROM_COMPID_COUNT (4U)
Pawel Zarembski	0:01f31e923fe2	3770
Pawel Zarembski	0:01f31e923fe2	3771
Pawel Zarembski	0:01f31e923fe2	3772	/*!
Pawel Zarembski	0:01f31e923fe2	3773	* @}
Pawel Zarembski	0:01f31e923fe2	3774	/ / end of group ROM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3775
Pawel Zarembski	0:01f31e923fe2	3776
Pawel Zarembski	0:01f31e923fe2	3777	/* ROM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3778	/** Peripheral ROM base address */
Pawel Zarembski	0:01f31e923fe2	3779	#define ROM_BASE (0xF0002000u)
Pawel Zarembski	0:01f31e923fe2	3780	/** Peripheral ROM base pointer */
Pawel Zarembski	0:01f31e923fe2	3781	#define ROM ((ROM_Type *)ROM_BASE)
Pawel Zarembski	0:01f31e923fe2	3782	/** Array initializer of ROM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3783	#define ROM_BASE_ADDRS { ROM_BASE }
Pawel Zarembski	0:01f31e923fe2	3784	/** Array initializer of ROM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3785	#define ROM_BASE_PTRS { ROM }
Pawel Zarembski	0:01f31e923fe2	3786
Pawel Zarembski	0:01f31e923fe2	3787	/*!
Pawel Zarembski	0:01f31e923fe2	3788	* @}
Pawel Zarembski	0:01f31e923fe2	3789	/ / end of group ROM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3790
Pawel Zarembski	0:01f31e923fe2	3791
Pawel Zarembski	0:01f31e923fe2	3792	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3793	-- RTC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3794	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3795
Pawel Zarembski	0:01f31e923fe2	3796	/*!
Pawel Zarembski	0:01f31e923fe2	3797	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3798	* @{
Pawel Zarembski	0:01f31e923fe2	3799	*/
Pawel Zarembski	0:01f31e923fe2	3800
Pawel Zarembski	0:01f31e923fe2	3801	/** RTC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3802	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3803	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3804	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3805	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	3806	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	3807	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	3808	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	3809	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	3810	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	3811	} RTC_Type;
Pawel Zarembski	0:01f31e923fe2	3812
Pawel Zarembski	0:01f31e923fe2	3813	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3814	-- RTC Register Masks
Pawel Zarembski	0:01f31e923fe2	3815	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3816
Pawel Zarembski	0:01f31e923fe2	3817	/*!
Pawel Zarembski	0:01f31e923fe2	3818	* @addtogroup RTC_Register_Masks RTC Register Masks
Pawel Zarembski	0:01f31e923fe2	3819	* @{
Pawel Zarembski	0:01f31e923fe2	3820	*/
Pawel Zarembski	0:01f31e923fe2	3821
Pawel Zarembski	0:01f31e923fe2	3822	/! @name TSR - RTC Time Seconds Register /
Pawel Zarembski	0:01f31e923fe2	3823	#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3824	#define RTC_TSR_TSR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3825	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
Pawel Zarembski	0:01f31e923fe2	3826
Pawel Zarembski	0:01f31e923fe2	3827	/! @name TPR - RTC Time Prescaler Register /
Pawel Zarembski	0:01f31e923fe2	3828	#define RTC_TPR_TPR_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	3829	#define RTC_TPR_TPR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3830	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
Pawel Zarembski	0:01f31e923fe2	3831
Pawel Zarembski	0:01f31e923fe2	3832	/! @name TAR - RTC Time Alarm Register /
Pawel Zarembski	0:01f31e923fe2	3833	#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	3834	#define RTC_TAR_TAR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3835	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
Pawel Zarembski	0:01f31e923fe2	3836
Pawel Zarembski	0:01f31e923fe2	3837	/! @name TCR - RTC Time Compensation Register /
Pawel Zarembski	0:01f31e923fe2	3838	#define RTC_TCR_TCR_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	3839	#define RTC_TCR_TCR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3840	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
Pawel Zarembski	0:01f31e923fe2	3841	#define RTC_TCR_CIR_MASK (0xFF00U)
Pawel Zarembski	0:01f31e923fe2	3842	#define RTC_TCR_CIR_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3843	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
Pawel Zarembski	0:01f31e923fe2	3844	#define RTC_TCR_TCV_MASK (0xFF0000U)
Pawel Zarembski	0:01f31e923fe2	3845	#define RTC_TCR_TCV_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	3846	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
Pawel Zarembski	0:01f31e923fe2	3847	#define RTC_TCR_CIC_MASK (0xFF000000U)
Pawel Zarembski	0:01f31e923fe2	3848	#define RTC_TCR_CIC_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	3849	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
Pawel Zarembski	0:01f31e923fe2	3850
Pawel Zarembski	0:01f31e923fe2	3851	/! @name CR - RTC Control Register /
Pawel Zarembski	0:01f31e923fe2	3852	#define RTC_CR_SWR_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3853	#define RTC_CR_SWR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3854	#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
Pawel Zarembski	0:01f31e923fe2	3855	#define RTC_CR_WPE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3856	#define RTC_CR_WPE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3857	#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
Pawel Zarembski	0:01f31e923fe2	3858	#define RTC_CR_SUP_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3859	#define RTC_CR_SUP_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3860	#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
Pawel Zarembski	0:01f31e923fe2	3861	#define RTC_CR_UM_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3862	#define RTC_CR_UM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3863	#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
Pawel Zarembski	0:01f31e923fe2	3864	#define RTC_CR_WPS_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3865	#define RTC_CR_WPS_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3866	#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
Pawel Zarembski	0:01f31e923fe2	3867	#define RTC_CR_OSCE_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	3868	#define RTC_CR_OSCE_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	3869	#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
Pawel Zarembski	0:01f31e923fe2	3870	#define RTC_CR_CLKO_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	3871	#define RTC_CR_CLKO_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	3872	#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
Pawel Zarembski	0:01f31e923fe2	3873	#define RTC_CR_SC16P_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	3874	#define RTC_CR_SC16P_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	3875	#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
Pawel Zarembski	0:01f31e923fe2	3876	#define RTC_CR_SC8P_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	3877	#define RTC_CR_SC8P_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	3878	#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
Pawel Zarembski	0:01f31e923fe2	3879	#define RTC_CR_SC4P_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	3880	#define RTC_CR_SC4P_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	3881	#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
Pawel Zarembski	0:01f31e923fe2	3882	#define RTC_CR_SC2P_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	3883	#define RTC_CR_SC2P_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	3884	#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
Pawel Zarembski	0:01f31e923fe2	3885
Pawel Zarembski	0:01f31e923fe2	3886	/! @name SR - RTC Status Register /
Pawel Zarembski	0:01f31e923fe2	3887	#define RTC_SR_TIF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3888	#define RTC_SR_TIF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3889	#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
Pawel Zarembski	0:01f31e923fe2	3890	#define RTC_SR_TOF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3891	#define RTC_SR_TOF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3892	#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
Pawel Zarembski	0:01f31e923fe2	3893	#define RTC_SR_TAF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3894	#define RTC_SR_TAF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3895	#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
Pawel Zarembski	0:01f31e923fe2	3896	#define RTC_SR_TCE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3897	#define RTC_SR_TCE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3898	#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
Pawel Zarembski	0:01f31e923fe2	3899
Pawel Zarembski	0:01f31e923fe2	3900	/! @name LR - RTC Lock Register /
Pawel Zarembski	0:01f31e923fe2	3901	#define RTC_LR_TCL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	3902	#define RTC_LR_TCL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	3903	#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
Pawel Zarembski	0:01f31e923fe2	3904	#define RTC_LR_CRL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3905	#define RTC_LR_CRL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3906	#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
Pawel Zarembski	0:01f31e923fe2	3907	#define RTC_LR_SRL_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	3908	#define RTC_LR_SRL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	3909	#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
Pawel Zarembski	0:01f31e923fe2	3910	#define RTC_LR_LRL_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	3911	#define RTC_LR_LRL_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	3912	#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
Pawel Zarembski	0:01f31e923fe2	3913
Pawel Zarembski	0:01f31e923fe2	3914	/! @name IER - RTC Interrupt Enable Register /
Pawel Zarembski	0:01f31e923fe2	3915	#define RTC_IER_TIIE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	3916	#define RTC_IER_TIIE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	3917	#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3918	#define RTC_IER_TOIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	3919	#define RTC_IER_TOIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	3920	#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3921	#define RTC_IER_TAIE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	3922	#define RTC_IER_TAIE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	3923	#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3924	#define RTC_IER_TSIE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	3925	#define RTC_IER_TSIE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	3926	#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
Pawel Zarembski	0:01f31e923fe2	3927	#define RTC_IER_WPON_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	3928	#define RTC_IER_WPON_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	3929	#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
Pawel Zarembski	0:01f31e923fe2	3930
Pawel Zarembski	0:01f31e923fe2	3931
Pawel Zarembski	0:01f31e923fe2	3932	/*!
Pawel Zarembski	0:01f31e923fe2	3933	* @}
Pawel Zarembski	0:01f31e923fe2	3934	/ / end of group RTC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	3935
Pawel Zarembski	0:01f31e923fe2	3936
Pawel Zarembski	0:01f31e923fe2	3937	/* RTC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	3938	/** Peripheral RTC base address */
Pawel Zarembski	0:01f31e923fe2	3939	#define RTC_BASE (0x4003D000u)
Pawel Zarembski	0:01f31e923fe2	3940	/** Peripheral RTC base pointer */
Pawel Zarembski	0:01f31e923fe2	3941	#define RTC ((RTC_Type *)RTC_BASE)
Pawel Zarembski	0:01f31e923fe2	3942	/** Array initializer of RTC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	3943	#define RTC_BASE_ADDRS { RTC_BASE }
Pawel Zarembski	0:01f31e923fe2	3944	/** Array initializer of RTC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	3945	#define RTC_BASE_PTRS { RTC }
Pawel Zarembski	0:01f31e923fe2	3946	/** Interrupt vectors for the RTC peripheral type */
Pawel Zarembski	0:01f31e923fe2	3947	#define RTC_IRQS { RTC_IRQn }
Pawel Zarembski	0:01f31e923fe2	3948	#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
Pawel Zarembski	0:01f31e923fe2	3949
Pawel Zarembski	0:01f31e923fe2	3950	/*!
Pawel Zarembski	0:01f31e923fe2	3951	* @}
Pawel Zarembski	0:01f31e923fe2	3952	/ / end of group RTC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	3953
Pawel Zarembski	0:01f31e923fe2	3954
Pawel Zarembski	0:01f31e923fe2	3955	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3956	-- SIM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3957	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3958
Pawel Zarembski	0:01f31e923fe2	3959	/*!
Pawel Zarembski	0:01f31e923fe2	3960	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	3961	* @{
Pawel Zarembski	0:01f31e923fe2	3962	*/
Pawel Zarembski	0:01f31e923fe2	3963
Pawel Zarembski	0:01f31e923fe2	3964	/** SIM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	3965	typedef struct {
Pawel Zarembski	0:01f31e923fe2	3966	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	3967	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	3968	uint8_t RESERVED_0[4092];
Pawel Zarembski	0:01f31e923fe2	3969	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
Pawel Zarembski	0:01f31e923fe2	3970	uint8_t RESERVED_1[4];
Pawel Zarembski	0:01f31e923fe2	3971	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
Pawel Zarembski	0:01f31e923fe2	3972	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
Pawel Zarembski	0:01f31e923fe2	3973	uint8_t RESERVED_2[4];
Pawel Zarembski	0:01f31e923fe2	3974	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
Pawel Zarembski	0:01f31e923fe2	3975	uint8_t RESERVED_3[8];
Pawel Zarembski	0:01f31e923fe2	3976	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
Pawel Zarembski	0:01f31e923fe2	3977	uint8_t RESERVED_4[12];
Pawel Zarembski	0:01f31e923fe2	3978	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
Pawel Zarembski	0:01f31e923fe2	3979	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
Pawel Zarembski	0:01f31e923fe2	3980	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
Pawel Zarembski	0:01f31e923fe2	3981	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
Pawel Zarembski	0:01f31e923fe2	3982	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
Pawel Zarembski	0:01f31e923fe2	3983	uint8_t RESERVED_5[4];
Pawel Zarembski	0:01f31e923fe2	3984	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
Pawel Zarembski	0:01f31e923fe2	3985	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
Pawel Zarembski	0:01f31e923fe2	3986	uint8_t RESERVED_6[4];
Pawel Zarembski	0:01f31e923fe2	3987	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
Pawel Zarembski	0:01f31e923fe2	3988	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
Pawel Zarembski	0:01f31e923fe2	3989	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
Pawel Zarembski	0:01f31e923fe2	3990	uint8_t RESERVED_7[156];
Pawel Zarembski	0:01f31e923fe2	3991	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
Pawel Zarembski	0:01f31e923fe2	3992	__O uint32_t SRVCOP; /*< Service COP, offset: 0x1104 /
Pawel Zarembski	0:01f31e923fe2	3993	} SIM_Type;
Pawel Zarembski	0:01f31e923fe2	3994
Pawel Zarembski	0:01f31e923fe2	3995	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	3996	-- SIM Register Masks
Pawel Zarembski	0:01f31e923fe2	3997	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	3998
Pawel Zarembski	0:01f31e923fe2	3999	/*!
Pawel Zarembski	0:01f31e923fe2	4000	* @addtogroup SIM_Register_Masks SIM Register Masks
Pawel Zarembski	0:01f31e923fe2	4001	* @{
Pawel Zarembski	0:01f31e923fe2	4002	*/
Pawel Zarembski	0:01f31e923fe2	4003
Pawel Zarembski	0:01f31e923fe2	4004	/! @name SOPT1 - System Options Register 1 /
Pawel Zarembski	0:01f31e923fe2	4005	#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	4006	#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4007	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4008	#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	4009	#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	4010	#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
Pawel Zarembski	0:01f31e923fe2	4011	#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
Pawel Zarembski	0:01f31e923fe2	4012	#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
Pawel Zarembski	0:01f31e923fe2	4013	#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
Pawel Zarembski	0:01f31e923fe2	4014	#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	4015	#define SIM_SOPT1_USBREGEN_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	4016	#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4017
Pawel Zarembski	0:01f31e923fe2	4018	/! @name SOPT1CFG - SOPT1 Configuration Register /
Pawel Zarembski	0:01f31e923fe2	4019	#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	4020	#define SIM_SOPT1CFG_URWE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4021	#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
Pawel Zarembski	0:01f31e923fe2	4022	#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	4023	#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	4024	#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
Pawel Zarembski	0:01f31e923fe2	4025	#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	4026	#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	4027	#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
Pawel Zarembski	0:01f31e923fe2	4028
Pawel Zarembski	0:01f31e923fe2	4029	/! @name SOPT2 - System Options Register 2 /
Pawel Zarembski	0:01f31e923fe2	4030	#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4031	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4032	#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4033	#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
Pawel Zarembski	0:01f31e923fe2	4034	#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4035	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4036	#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	4037	#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4038	#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4039	#define SIM_SOPT2_USBSRC_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	4040	#define SIM_SOPT2_USBSRC_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4041	#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4042	#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
Pawel Zarembski	0:01f31e923fe2	4043	#define SIM_SOPT2_TPMSRC_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4044	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4045	#define SIM_SOPT2_UART0SRC_MASK (0xC000000U)
Pawel Zarembski	0:01f31e923fe2	4046	#define SIM_SOPT2_UART0SRC_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	4047	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4048
Pawel Zarembski	0:01f31e923fe2	4049	/! @name SOPT4 - System Options Register 4 /
Pawel Zarembski	0:01f31e923fe2	4050	#define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U)
Pawel Zarembski	0:01f31e923fe2	4051	#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4052	#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4053	#define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
Pawel Zarembski	0:01f31e923fe2	4054	#define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	4055	#define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4056	#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	4057	#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4058	#define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4059	#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	4060	#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	4061	#define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4062	#define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	4063	#define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	4064	#define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4065
Pawel Zarembski	0:01f31e923fe2	4066	/! @name SOPT5 - System Options Register 5 /
Pawel Zarembski	0:01f31e923fe2	4067	#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
Pawel Zarembski	0:01f31e923fe2	4068	#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4069	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4070	#define SIM_SOPT5_UART0RXSRC_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4071	#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4072	#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4073	#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
Pawel Zarembski	0:01f31e923fe2	4074	#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4075	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4076	#define SIM_SOPT5_UART1RXSRC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4077	#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4078	#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4079	#define SIM_SOPT5_UART0ODE_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	4080	#define SIM_SOPT5_UART0ODE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4081	#define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4082	#define SIM_SOPT5_UART1ODE_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	4083	#define SIM_SOPT5_UART1ODE_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	4084	#define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4085	#define SIM_SOPT5_UART2ODE_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	4086	#define SIM_SOPT5_UART2ODE_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4087	#define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4088
Pawel Zarembski	0:01f31e923fe2	4089	/! @name SOPT7 - System Options Register 7 /
Pawel Zarembski	0:01f31e923fe2	4090	#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	4091	#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4092	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4093	#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4094	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4095	#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4096	#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4097	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4098	#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4099
Pawel Zarembski	0:01f31e923fe2	4100	/! @name SDID - System Device Identification Register /
Pawel Zarembski	0:01f31e923fe2	4101	#define SIM_SDID_PINID_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	4102	#define SIM_SDID_PINID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4103	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
Pawel Zarembski	0:01f31e923fe2	4104	#define SIM_SDID_DIEID_MASK (0xF80U)
Pawel Zarembski	0:01f31e923fe2	4105	#define SIM_SDID_DIEID_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4106	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
Pawel Zarembski	0:01f31e923fe2	4107	#define SIM_SDID_REVID_MASK (0xF000U)
Pawel Zarembski	0:01f31e923fe2	4108	#define SIM_SDID_REVID_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	4109	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
Pawel Zarembski	0:01f31e923fe2	4110	#define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
Pawel Zarembski	0:01f31e923fe2	4111	#define SIM_SDID_SRAMSIZE_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4112	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	4113	#define SIM_SDID_SERIESID_MASK (0xF00000U)
Pawel Zarembski	0:01f31e923fe2	4114	#define SIM_SDID_SERIESID_SHIFT (20U)
Pawel Zarembski	0:01f31e923fe2	4115	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
Pawel Zarembski	0:01f31e923fe2	4116	#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	4117	#define SIM_SDID_SUBFAMID_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4118	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
Pawel Zarembski	0:01f31e923fe2	4119	#define SIM_SDID_FAMID_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	4120	#define SIM_SDID_FAMID_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	4121	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
Pawel Zarembski	0:01f31e923fe2	4122
Pawel Zarembski	0:01f31e923fe2	4123	/! @name SCGC4 - System Clock Gating Control Register 4 /
Pawel Zarembski	0:01f31e923fe2	4124	#define SIM_SCGC4_I2C0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4125	#define SIM_SCGC4_I2C0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4126	#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
Pawel Zarembski	0:01f31e923fe2	4127	#define SIM_SCGC4_I2C1_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4128	#define SIM_SCGC4_I2C1_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4129	#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
Pawel Zarembski	0:01f31e923fe2	4130	#define SIM_SCGC4_UART0_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	4131	#define SIM_SCGC4_UART0_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	4132	#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
Pawel Zarembski	0:01f31e923fe2	4133	#define SIM_SCGC4_UART1_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	4134	#define SIM_SCGC4_UART1_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	4135	#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
Pawel Zarembski	0:01f31e923fe2	4136	#define SIM_SCGC4_UART2_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	4137	#define SIM_SCGC4_UART2_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	4138	#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
Pawel Zarembski	0:01f31e923fe2	4139	#define SIM_SCGC4_USBOTG_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	4140	#define SIM_SCGC4_USBOTG_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4141	#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
Pawel Zarembski	0:01f31e923fe2	4142	#define SIM_SCGC4_CMP_MASK (0x80000U)
Pawel Zarembski	0:01f31e923fe2	4143	#define SIM_SCGC4_CMP_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	4144	#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
Pawel Zarembski	0:01f31e923fe2	4145	#define SIM_SCGC4_SPI0_MASK (0x400000U)
Pawel Zarembski	0:01f31e923fe2	4146	#define SIM_SCGC4_SPI0_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	4147	#define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
Pawel Zarembski	0:01f31e923fe2	4148	#define SIM_SCGC4_SPI1_MASK (0x800000U)
Pawel Zarembski	0:01f31e923fe2	4149	#define SIM_SCGC4_SPI1_SHIFT (23U)
Pawel Zarembski	0:01f31e923fe2	4150	#define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
Pawel Zarembski	0:01f31e923fe2	4151
Pawel Zarembski	0:01f31e923fe2	4152	/! @name SCGC5 - System Clock Gating Control Register 5 /
Pawel Zarembski	0:01f31e923fe2	4153	#define SIM_SCGC5_LPTMR_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4154	#define SIM_SCGC5_LPTMR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4155	#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
Pawel Zarembski	0:01f31e923fe2	4156	#define SIM_SCGC5_TSI_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4157	#define SIM_SCGC5_TSI_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4158	#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
Pawel Zarembski	0:01f31e923fe2	4159	#define SIM_SCGC5_PORTA_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	4160	#define SIM_SCGC5_PORTA_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	4161	#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
Pawel Zarembski	0:01f31e923fe2	4162	#define SIM_SCGC5_PORTB_MASK (0x400U)
Pawel Zarembski	0:01f31e923fe2	4163	#define SIM_SCGC5_PORTB_SHIFT (10U)
Pawel Zarembski	0:01f31e923fe2	4164	#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
Pawel Zarembski	0:01f31e923fe2	4165	#define SIM_SCGC5_PORTC_MASK (0x800U)
Pawel Zarembski	0:01f31e923fe2	4166	#define SIM_SCGC5_PORTC_SHIFT (11U)
Pawel Zarembski	0:01f31e923fe2	4167	#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
Pawel Zarembski	0:01f31e923fe2	4168	#define SIM_SCGC5_PORTD_MASK (0x1000U)
Pawel Zarembski	0:01f31e923fe2	4169	#define SIM_SCGC5_PORTD_SHIFT (12U)
Pawel Zarembski	0:01f31e923fe2	4170	#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
Pawel Zarembski	0:01f31e923fe2	4171	#define SIM_SCGC5_PORTE_MASK (0x2000U)
Pawel Zarembski	0:01f31e923fe2	4172	#define SIM_SCGC5_PORTE_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	4173	#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
Pawel Zarembski	0:01f31e923fe2	4174
Pawel Zarembski	0:01f31e923fe2	4175	/! @name SCGC6 - System Clock Gating Control Register 6 /
Pawel Zarembski	0:01f31e923fe2	4176	#define SIM_SCGC6_FTF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4177	#define SIM_SCGC6_FTF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4178	#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
Pawel Zarembski	0:01f31e923fe2	4179	#define SIM_SCGC6_DMAMUX_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4180	#define SIM_SCGC6_DMAMUX_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4181	#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
Pawel Zarembski	0:01f31e923fe2	4182	#define SIM_SCGC6_I2S_MASK (0x8000U)
Pawel Zarembski	0:01f31e923fe2	4183	#define SIM_SCGC6_I2S_SHIFT (15U)
Pawel Zarembski	0:01f31e923fe2	4184	#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
Pawel Zarembski	0:01f31e923fe2	4185	#define SIM_SCGC6_PIT_MASK (0x800000U)
Pawel Zarembski	0:01f31e923fe2	4186	#define SIM_SCGC6_PIT_SHIFT (23U)
Pawel Zarembski	0:01f31e923fe2	4187	#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
Pawel Zarembski	0:01f31e923fe2	4188	#define SIM_SCGC6_TPM0_MASK (0x1000000U)
Pawel Zarembski	0:01f31e923fe2	4189	#define SIM_SCGC6_TPM0_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4190	#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
Pawel Zarembski	0:01f31e923fe2	4191	#define SIM_SCGC6_TPM1_MASK (0x2000000U)
Pawel Zarembski	0:01f31e923fe2	4192	#define SIM_SCGC6_TPM1_SHIFT (25U)
Pawel Zarembski	0:01f31e923fe2	4193	#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
Pawel Zarembski	0:01f31e923fe2	4194	#define SIM_SCGC6_TPM2_MASK (0x4000000U)
Pawel Zarembski	0:01f31e923fe2	4195	#define SIM_SCGC6_TPM2_SHIFT (26U)
Pawel Zarembski	0:01f31e923fe2	4196	#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
Pawel Zarembski	0:01f31e923fe2	4197	#define SIM_SCGC6_ADC0_MASK (0x8000000U)
Pawel Zarembski	0:01f31e923fe2	4198	#define SIM_SCGC6_ADC0_SHIFT (27U)
Pawel Zarembski	0:01f31e923fe2	4199	#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
Pawel Zarembski	0:01f31e923fe2	4200	#define SIM_SCGC6_RTC_MASK (0x20000000U)
Pawel Zarembski	0:01f31e923fe2	4201	#define SIM_SCGC6_RTC_SHIFT (29U)
Pawel Zarembski	0:01f31e923fe2	4202	#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
Pawel Zarembski	0:01f31e923fe2	4203	#define SIM_SCGC6_DAC0_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	4204	#define SIM_SCGC6_DAC0_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	4205	#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
Pawel Zarembski	0:01f31e923fe2	4206
Pawel Zarembski	0:01f31e923fe2	4207	/! @name SCGC7 - System Clock Gating Control Register 7 /
Pawel Zarembski	0:01f31e923fe2	4208	#define SIM_SCGC7_DMA_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	4209	#define SIM_SCGC7_DMA_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4210	#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
Pawel Zarembski	0:01f31e923fe2	4211
Pawel Zarembski	0:01f31e923fe2	4212	/! @name CLKDIV1 - System Clock Divider Register 1 /
Pawel Zarembski	0:01f31e923fe2	4213	#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
Pawel Zarembski	0:01f31e923fe2	4214	#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4215	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
Pawel Zarembski	0:01f31e923fe2	4216	#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	4217	#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	4218	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
Pawel Zarembski	0:01f31e923fe2	4219
Pawel Zarembski	0:01f31e923fe2	4220	/! @name FCFG1 - Flash Configuration Register 1 /
Pawel Zarembski	0:01f31e923fe2	4221	#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4222	#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4223	#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	4224	#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4225	#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4226	#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
Pawel Zarembski	0:01f31e923fe2	4227	#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	4228	#define SIM_FCFG1_PFSIZE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4229	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
Pawel Zarembski	0:01f31e923fe2	4230
Pawel Zarembski	0:01f31e923fe2	4231	/! @name FCFG2 - Flash Configuration Register 2 /
Pawel Zarembski	0:01f31e923fe2	4232	#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
Pawel Zarembski	0:01f31e923fe2	4233	#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4234	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
Pawel Zarembski	0:01f31e923fe2	4235	#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
Pawel Zarembski	0:01f31e923fe2	4236	#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4237	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
Pawel Zarembski	0:01f31e923fe2	4238
Pawel Zarembski	0:01f31e923fe2	4239	/! @name UIDMH - Unique Identification Register Mid-High /
Pawel Zarembski	0:01f31e923fe2	4240	#define SIM_UIDMH_UID_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4241	#define SIM_UIDMH_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4242	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	4243
Pawel Zarembski	0:01f31e923fe2	4244	/! @name UIDML - Unique Identification Register Mid Low /
Pawel Zarembski	0:01f31e923fe2	4245	#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	4246	#define SIM_UIDML_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4247	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	4248
Pawel Zarembski	0:01f31e923fe2	4249	/! @name UIDL - Unique Identification Register Low /
Pawel Zarembski	0:01f31e923fe2	4250	#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
Pawel Zarembski	0:01f31e923fe2	4251	#define SIM_UIDL_UID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4252	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
Pawel Zarembski	0:01f31e923fe2	4253
Pawel Zarembski	0:01f31e923fe2	4254	/! @name COPC - COP Control Register /
Pawel Zarembski	0:01f31e923fe2	4255	#define SIM_COPC_COPW_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4256	#define SIM_COPC_COPW_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4257	#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
Pawel Zarembski	0:01f31e923fe2	4258	#define SIM_COPC_COPCLKS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4259	#define SIM_COPC_COPCLKS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4260	#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
Pawel Zarembski	0:01f31e923fe2	4261	#define SIM_COPC_COPT_MASK (0xCU)
Pawel Zarembski	0:01f31e923fe2	4262	#define SIM_COPC_COPT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4263	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
Pawel Zarembski	0:01f31e923fe2	4264
Pawel Zarembski	0:01f31e923fe2	4265	/! @name SRVCOP - Service COP /
Pawel Zarembski	0:01f31e923fe2	4266	#define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4267	#define SIM_SRVCOP_SRVCOP_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4268	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
Pawel Zarembski	0:01f31e923fe2	4269
Pawel Zarembski	0:01f31e923fe2	4270
Pawel Zarembski	0:01f31e923fe2	4271	/*!
Pawel Zarembski	0:01f31e923fe2	4272	* @}
Pawel Zarembski	0:01f31e923fe2	4273	/ / end of group SIM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4274
Pawel Zarembski	0:01f31e923fe2	4275
Pawel Zarembski	0:01f31e923fe2	4276	/* SIM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4277	/** Peripheral SIM base address */
Pawel Zarembski	0:01f31e923fe2	4278	#define SIM_BASE (0x40047000u)
Pawel Zarembski	0:01f31e923fe2	4279	/** Peripheral SIM base pointer */
Pawel Zarembski	0:01f31e923fe2	4280	#define SIM ((SIM_Type *)SIM_BASE)
Pawel Zarembski	0:01f31e923fe2	4281	/** Array initializer of SIM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4282	#define SIM_BASE_ADDRS { SIM_BASE }
Pawel Zarembski	0:01f31e923fe2	4283	/** Array initializer of SIM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4284	#define SIM_BASE_PTRS { SIM }
Pawel Zarembski	0:01f31e923fe2	4285
Pawel Zarembski	0:01f31e923fe2	4286	/*!
Pawel Zarembski	0:01f31e923fe2	4287	* @}
Pawel Zarembski	0:01f31e923fe2	4288	/ / end of group SIM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4289
Pawel Zarembski	0:01f31e923fe2	4290
Pawel Zarembski	0:01f31e923fe2	4291	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4292	-- SMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4293	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4294
Pawel Zarembski	0:01f31e923fe2	4295	/*!
Pawel Zarembski	0:01f31e923fe2	4296	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4297	* @{
Pawel Zarembski	0:01f31e923fe2	4298	*/
Pawel Zarembski	0:01f31e923fe2	4299
Pawel Zarembski	0:01f31e923fe2	4300	/** SMC - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4301	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4302	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4303	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	4304	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	4305	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	4306	} SMC_Type;
Pawel Zarembski	0:01f31e923fe2	4307
Pawel Zarembski	0:01f31e923fe2	4308	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4309	-- SMC Register Masks
Pawel Zarembski	0:01f31e923fe2	4310	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4311
Pawel Zarembski	0:01f31e923fe2	4312	/*!
Pawel Zarembski	0:01f31e923fe2	4313	* @addtogroup SMC_Register_Masks SMC Register Masks
Pawel Zarembski	0:01f31e923fe2	4314	* @{
Pawel Zarembski	0:01f31e923fe2	4315	*/
Pawel Zarembski	0:01f31e923fe2	4316
Pawel Zarembski	0:01f31e923fe2	4317	/! @name PMPROT - Power Mode Protection register /
Pawel Zarembski	0:01f31e923fe2	4318	#define SMC_PMPROT_AVLLS_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4319	#define SMC_PMPROT_AVLLS_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4320	#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
Pawel Zarembski	0:01f31e923fe2	4321	#define SMC_PMPROT_ALLS_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4322	#define SMC_PMPROT_ALLS_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4323	#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
Pawel Zarembski	0:01f31e923fe2	4324	#define SMC_PMPROT_AVLP_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4325	#define SMC_PMPROT_AVLP_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4326	#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
Pawel Zarembski	0:01f31e923fe2	4327
Pawel Zarembski	0:01f31e923fe2	4328	/! @name PMCTRL - Power Mode Control register /
Pawel Zarembski	0:01f31e923fe2	4329	#define SMC_PMCTRL_STOPM_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	4330	#define SMC_PMCTRL_STOPM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4331	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
Pawel Zarembski	0:01f31e923fe2	4332	#define SMC_PMCTRL_STOPA_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4333	#define SMC_PMCTRL_STOPA_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4334	#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
Pawel Zarembski	0:01f31e923fe2	4335	#define SMC_PMCTRL_RUNM_MASK (0x60U)
Pawel Zarembski	0:01f31e923fe2	4336	#define SMC_PMCTRL_RUNM_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4337	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
Pawel Zarembski	0:01f31e923fe2	4338
Pawel Zarembski	0:01f31e923fe2	4339	/! @name STOPCTRL - Stop Control Register /
Pawel Zarembski	0:01f31e923fe2	4340	#define SMC_STOPCTRL_VLLSM_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	4341	#define SMC_STOPCTRL_VLLSM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4342	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
Pawel Zarembski	0:01f31e923fe2	4343	#define SMC_STOPCTRL_PORPO_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4344	#define SMC_STOPCTRL_PORPO_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4345	#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
Pawel Zarembski	0:01f31e923fe2	4346	#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	4347	#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4348	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
Pawel Zarembski	0:01f31e923fe2	4349
Pawel Zarembski	0:01f31e923fe2	4350	/! @name PMSTAT - Power Mode Status register /
Pawel Zarembski	0:01f31e923fe2	4351	#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	4352	#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4353	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
Pawel Zarembski	0:01f31e923fe2	4354
Pawel Zarembski	0:01f31e923fe2	4355
Pawel Zarembski	0:01f31e923fe2	4356	/*!
Pawel Zarembski	0:01f31e923fe2	4357	* @}
Pawel Zarembski	0:01f31e923fe2	4358	/ / end of group SMC_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4359
Pawel Zarembski	0:01f31e923fe2	4360
Pawel Zarembski	0:01f31e923fe2	4361	/* SMC - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4362	/** Peripheral SMC base address */
Pawel Zarembski	0:01f31e923fe2	4363	#define SMC_BASE (0x4007E000u)
Pawel Zarembski	0:01f31e923fe2	4364	/** Peripheral SMC base pointer */
Pawel Zarembski	0:01f31e923fe2	4365	#define SMC ((SMC_Type *)SMC_BASE)
Pawel Zarembski	0:01f31e923fe2	4366	/** Array initializer of SMC peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4367	#define SMC_BASE_ADDRS { SMC_BASE }
Pawel Zarembski	0:01f31e923fe2	4368	/** Array initializer of SMC peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4369	#define SMC_BASE_PTRS { SMC }
Pawel Zarembski	0:01f31e923fe2	4370
Pawel Zarembski	0:01f31e923fe2	4371	/*!
Pawel Zarembski	0:01f31e923fe2	4372	* @}
Pawel Zarembski	0:01f31e923fe2	4373	/ / end of group SMC_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4374
Pawel Zarembski	0:01f31e923fe2	4375
Pawel Zarembski	0:01f31e923fe2	4376	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4377	-- SPI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4378	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4379
Pawel Zarembski	0:01f31e923fe2	4380	/*!
Pawel Zarembski	0:01f31e923fe2	4381	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4382	* @{
Pawel Zarembski	0:01f31e923fe2	4383	*/
Pawel Zarembski	0:01f31e923fe2	4384
Pawel Zarembski	0:01f31e923fe2	4385	/** SPI - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4386	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4387	__IO uint8_t S; /*< SPI Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4388	__IO uint8_t BR; /*< SPI Baud Rate Register, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	4389	__IO uint8_t C2; /*< SPI Control Register 2, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	4390	__IO uint8_t C1; /*< SPI Control Register 1, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	4391	__IO uint8_t ML; /*< SPI Match Register low, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4392	__IO uint8_t MH; /*< SPI match register high, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	4393	__IO uint8_t DL; /*< SPI Data Register low, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	4394	__IO uint8_t DH; /*< SPI data register high, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	4395	uint8_t RESERVED_0[2];
Pawel Zarembski	0:01f31e923fe2	4396	__IO uint8_t CI; /*< SPI clear interrupt register, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	4397	__IO uint8_t C3; /*< SPI control register 3, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	4398	} SPI_Type;
Pawel Zarembski	0:01f31e923fe2	4399
Pawel Zarembski	0:01f31e923fe2	4400	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4401	-- SPI Register Masks
Pawel Zarembski	0:01f31e923fe2	4402	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4403
Pawel Zarembski	0:01f31e923fe2	4404	/*!
Pawel Zarembski	0:01f31e923fe2	4405	* @addtogroup SPI_Register_Masks SPI Register Masks
Pawel Zarembski	0:01f31e923fe2	4406	* @{
Pawel Zarembski	0:01f31e923fe2	4407	*/
Pawel Zarembski	0:01f31e923fe2	4408
Pawel Zarembski	0:01f31e923fe2	4409	/! @name S - SPI Status Register /
Pawel Zarembski	0:01f31e923fe2	4410	#define SPI_S_RFIFOEF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4411	#define SPI_S_RFIFOEF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4412	#define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
Pawel Zarembski	0:01f31e923fe2	4413	#define SPI_S_TXFULLF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4414	#define SPI_S_TXFULLF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4415	#define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
Pawel Zarembski	0:01f31e923fe2	4416	#define SPI_S_TNEAREF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4417	#define SPI_S_TNEAREF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4418	#define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
Pawel Zarembski	0:01f31e923fe2	4419	#define SPI_S_RNFULLF_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4420	#define SPI_S_RNFULLF_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4421	#define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
Pawel Zarembski	0:01f31e923fe2	4422	#define SPI_S_MODF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4423	#define SPI_S_MODF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4424	#define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
Pawel Zarembski	0:01f31e923fe2	4425	#define SPI_S_SPTEF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4426	#define SPI_S_SPTEF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4427	#define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
Pawel Zarembski	0:01f31e923fe2	4428	#define SPI_S_SPMF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4429	#define SPI_S_SPMF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4430	#define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
Pawel Zarembski	0:01f31e923fe2	4431	#define SPI_S_SPRF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4432	#define SPI_S_SPRF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4433	#define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
Pawel Zarembski	0:01f31e923fe2	4434
Pawel Zarembski	0:01f31e923fe2	4435	/! @name BR - SPI Baud Rate Register /
Pawel Zarembski	0:01f31e923fe2	4436	#define SPI_BR_SPR_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	4437	#define SPI_BR_SPR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4438	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
Pawel Zarembski	0:01f31e923fe2	4439	#define SPI_BR_SPPR_MASK (0x70U)
Pawel Zarembski	0:01f31e923fe2	4440	#define SPI_BR_SPPR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4441	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
Pawel Zarembski	0:01f31e923fe2	4442
Pawel Zarembski	0:01f31e923fe2	4443	/! @name C2 - SPI Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	4444	#define SPI_C2_SPC0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4445	#define SPI_C2_SPC0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4446	#define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
Pawel Zarembski	0:01f31e923fe2	4447	#define SPI_C2_SPISWAI_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4448	#define SPI_C2_SPISWAI_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4449	#define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
Pawel Zarembski	0:01f31e923fe2	4450	#define SPI_C2_RXDMAE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4451	#define SPI_C2_RXDMAE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4452	#define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
Pawel Zarembski	0:01f31e923fe2	4453	#define SPI_C2_BIDIROE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4454	#define SPI_C2_BIDIROE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4455	#define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
Pawel Zarembski	0:01f31e923fe2	4456	#define SPI_C2_MODFEN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4457	#define SPI_C2_MODFEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4458	#define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4459	#define SPI_C2_TXDMAE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4460	#define SPI_C2_TXDMAE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4461	#define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
Pawel Zarembski	0:01f31e923fe2	4462	#define SPI_C2_SPIMODE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4463	#define SPI_C2_SPIMODE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4464	#define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4465	#define SPI_C2_SPMIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4466	#define SPI_C2_SPMIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4467	#define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4468
Pawel Zarembski	0:01f31e923fe2	4469	/! @name C1 - SPI Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	4470	#define SPI_C1_LSBFE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4471	#define SPI_C1_LSBFE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4472	#define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
Pawel Zarembski	0:01f31e923fe2	4473	#define SPI_C1_SSOE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4474	#define SPI_C1_SSOE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4475	#define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
Pawel Zarembski	0:01f31e923fe2	4476	#define SPI_C1_CPHA_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4477	#define SPI_C1_CPHA_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4478	#define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
Pawel Zarembski	0:01f31e923fe2	4479	#define SPI_C1_CPOL_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4480	#define SPI_C1_CPOL_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4481	#define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
Pawel Zarembski	0:01f31e923fe2	4482	#define SPI_C1_MSTR_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4483	#define SPI_C1_MSTR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4484	#define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
Pawel Zarembski	0:01f31e923fe2	4485	#define SPI_C1_SPTIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4486	#define SPI_C1_SPTIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4487	#define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4488	#define SPI_C1_SPE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4489	#define SPI_C1_SPE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4490	#define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
Pawel Zarembski	0:01f31e923fe2	4491	#define SPI_C1_SPIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4492	#define SPI_C1_SPIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4493	#define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4494
Pawel Zarembski	0:01f31e923fe2	4495	/! @name ML - SPI Match Register low /
Pawel Zarembski	0:01f31e923fe2	4496	#define SPI_ML_Bits_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4497	#define SPI_ML_Bits_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4498	#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
Pawel Zarembski	0:01f31e923fe2	4499
Pawel Zarembski	0:01f31e923fe2	4500	/! @name MH - SPI match register high /
Pawel Zarembski	0:01f31e923fe2	4501	#define SPI_MH_Bits_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4502	#define SPI_MH_Bits_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4503	#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
Pawel Zarembski	0:01f31e923fe2	4504
Pawel Zarembski	0:01f31e923fe2	4505	/! @name DL - SPI Data Register low /
Pawel Zarembski	0:01f31e923fe2	4506	#define SPI_DL_Bits_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4507	#define SPI_DL_Bits_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4508	#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
Pawel Zarembski	0:01f31e923fe2	4509
Pawel Zarembski	0:01f31e923fe2	4510	/! @name DH - SPI data register high /
Pawel Zarembski	0:01f31e923fe2	4511	#define SPI_DH_Bits_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4512	#define SPI_DH_Bits_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4513	#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
Pawel Zarembski	0:01f31e923fe2	4514
Pawel Zarembski	0:01f31e923fe2	4515	/! @name CI - SPI clear interrupt register /
Pawel Zarembski	0:01f31e923fe2	4516	#define SPI_CI_SPRFCI_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4517	#define SPI_CI_SPRFCI_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4518	#define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
Pawel Zarembski	0:01f31e923fe2	4519	#define SPI_CI_SPTEFCI_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4520	#define SPI_CI_SPTEFCI_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4521	#define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
Pawel Zarembski	0:01f31e923fe2	4522	#define SPI_CI_RNFULLFCI_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4523	#define SPI_CI_RNFULLFCI_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4524	#define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
Pawel Zarembski	0:01f31e923fe2	4525	#define SPI_CI_TNEAREFCI_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4526	#define SPI_CI_TNEAREFCI_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4527	#define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
Pawel Zarembski	0:01f31e923fe2	4528	#define SPI_CI_RXFOF_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4529	#define SPI_CI_RXFOF_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4530	#define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
Pawel Zarembski	0:01f31e923fe2	4531	#define SPI_CI_TXFOF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4532	#define SPI_CI_TXFOF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4533	#define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
Pawel Zarembski	0:01f31e923fe2	4534	#define SPI_CI_RXFERR_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4535	#define SPI_CI_RXFERR_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4536	#define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
Pawel Zarembski	0:01f31e923fe2	4537	#define SPI_CI_TXFERR_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4538	#define SPI_CI_TXFERR_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4539	#define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
Pawel Zarembski	0:01f31e923fe2	4540
Pawel Zarembski	0:01f31e923fe2	4541	/! @name C3 - SPI control register 3 /
Pawel Zarembski	0:01f31e923fe2	4542	#define SPI_C3_FIFOMODE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4543	#define SPI_C3_FIFOMODE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4544	#define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4545	#define SPI_C3_RNFULLIEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4546	#define SPI_C3_RNFULLIEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4547	#define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4548	#define SPI_C3_TNEARIEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4549	#define SPI_C3_TNEARIEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4550	#define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4551	#define SPI_C3_INTCLR_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4552	#define SPI_C3_INTCLR_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4553	#define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
Pawel Zarembski	0:01f31e923fe2	4554	#define SPI_C3_RNFULLF_MARK_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4555	#define SPI_C3_RNFULLF_MARK_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4556	#define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
Pawel Zarembski	0:01f31e923fe2	4557	#define SPI_C3_TNEAREF_MARK_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4558	#define SPI_C3_TNEAREF_MARK_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4559	#define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
Pawel Zarembski	0:01f31e923fe2	4560
Pawel Zarembski	0:01f31e923fe2	4561
Pawel Zarembski	0:01f31e923fe2	4562	/*!
Pawel Zarembski	0:01f31e923fe2	4563	* @}
Pawel Zarembski	0:01f31e923fe2	4564	/ / end of group SPI_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4565
Pawel Zarembski	0:01f31e923fe2	4566
Pawel Zarembski	0:01f31e923fe2	4567	/* SPI - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4568	/** Peripheral SPI0 base address */
Pawel Zarembski	0:01f31e923fe2	4569	#define SPI0_BASE (0x40076000u)
Pawel Zarembski	0:01f31e923fe2	4570	/** Peripheral SPI0 base pointer */
Pawel Zarembski	0:01f31e923fe2	4571	#define SPI0 ((SPI_Type *)SPI0_BASE)
Pawel Zarembski	0:01f31e923fe2	4572	/** Peripheral SPI1 base address */
Pawel Zarembski	0:01f31e923fe2	4573	#define SPI1_BASE (0x40077000u)
Pawel Zarembski	0:01f31e923fe2	4574	/** Peripheral SPI1 base pointer */
Pawel Zarembski	0:01f31e923fe2	4575	#define SPI1 ((SPI_Type *)SPI1_BASE)
Pawel Zarembski	0:01f31e923fe2	4576	/** Array initializer of SPI peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4577	#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
Pawel Zarembski	0:01f31e923fe2	4578	/** Array initializer of SPI peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4579	#define SPI_BASE_PTRS { SPI0, SPI1 }
Pawel Zarembski	0:01f31e923fe2	4580	/** Interrupt vectors for the SPI peripheral type */
Pawel Zarembski	0:01f31e923fe2	4581	#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
Pawel Zarembski	0:01f31e923fe2	4582
Pawel Zarembski	0:01f31e923fe2	4583	/*!
Pawel Zarembski	0:01f31e923fe2	4584	* @}
Pawel Zarembski	0:01f31e923fe2	4585	/ / end of group SPI_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4586
Pawel Zarembski	0:01f31e923fe2	4587
Pawel Zarembski	0:01f31e923fe2	4588	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4589	-- TPM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4590	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4591
Pawel Zarembski	0:01f31e923fe2	4592	/*!
Pawel Zarembski	0:01f31e923fe2	4593	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4594	* @{
Pawel Zarembski	0:01f31e923fe2	4595	*/
Pawel Zarembski	0:01f31e923fe2	4596
Pawel Zarembski	0:01f31e923fe2	4597	/** TPM - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4598	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4599	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4600	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4601	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4602	struct { /* offset: 0xC, array step: 0x8 */
Pawel Zarembski	0:01f31e923fe2	4603	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4604	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4605	} CONTROLS[6];
Pawel Zarembski	0:01f31e923fe2	4606	uint8_t RESERVED_0[20];
Pawel Zarembski	0:01f31e923fe2	4607	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
Pawel Zarembski	0:01f31e923fe2	4608	uint8_t RESERVED_1[48];
Pawel Zarembski	0:01f31e923fe2	4609	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	4610	} TPM_Type;
Pawel Zarembski	0:01f31e923fe2	4611
Pawel Zarembski	0:01f31e923fe2	4612	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4613	-- TPM Register Masks
Pawel Zarembski	0:01f31e923fe2	4614	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4615
Pawel Zarembski	0:01f31e923fe2	4616	/*!
Pawel Zarembski	0:01f31e923fe2	4617	* @addtogroup TPM_Register_Masks TPM Register Masks
Pawel Zarembski	0:01f31e923fe2	4618	* @{
Pawel Zarembski	0:01f31e923fe2	4619	*/
Pawel Zarembski	0:01f31e923fe2	4620
Pawel Zarembski	0:01f31e923fe2	4621	/! @name SC - Status and Control /
Pawel Zarembski	0:01f31e923fe2	4622	#define TPM_SC_PS_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	4623	#define TPM_SC_PS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4624	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
Pawel Zarembski	0:01f31e923fe2	4625	#define TPM_SC_CMOD_MASK (0x18U)
Pawel Zarembski	0:01f31e923fe2	4626	#define TPM_SC_CMOD_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4627	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
Pawel Zarembski	0:01f31e923fe2	4628	#define TPM_SC_CPWMS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4629	#define TPM_SC_CPWMS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4630	#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
Pawel Zarembski	0:01f31e923fe2	4631	#define TPM_SC_TOIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4632	#define TPM_SC_TOIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4633	#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4634	#define TPM_SC_TOF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4635	#define TPM_SC_TOF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4636	#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
Pawel Zarembski	0:01f31e923fe2	4637	#define TPM_SC_DMA_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	4638	#define TPM_SC_DMA_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4639	#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
Pawel Zarembski	0:01f31e923fe2	4640
Pawel Zarembski	0:01f31e923fe2	4641	/! @name CNT - Counter /
Pawel Zarembski	0:01f31e923fe2	4642	#define TPM_CNT_COUNT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4643	#define TPM_CNT_COUNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4644	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
Pawel Zarembski	0:01f31e923fe2	4645
Pawel Zarembski	0:01f31e923fe2	4646	/! @name MOD - Modulo /
Pawel Zarembski	0:01f31e923fe2	4647	#define TPM_MOD_MOD_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4648	#define TPM_MOD_MOD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4649	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
Pawel Zarembski	0:01f31e923fe2	4650
Pawel Zarembski	0:01f31e923fe2	4651	/! @name CnSC - Channel (n) Status and Control /
Pawel Zarembski	0:01f31e923fe2	4652	#define TPM_CnSC_DMA_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4653	#define TPM_CnSC_DMA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4654	#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
Pawel Zarembski	0:01f31e923fe2	4655	#define TPM_CnSC_ELSA_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4656	#define TPM_CnSC_ELSA_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4657	#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
Pawel Zarembski	0:01f31e923fe2	4658	#define TPM_CnSC_ELSB_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4659	#define TPM_CnSC_ELSB_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4660	#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
Pawel Zarembski	0:01f31e923fe2	4661	#define TPM_CnSC_MSA_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4662	#define TPM_CnSC_MSA_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4663	#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
Pawel Zarembski	0:01f31e923fe2	4664	#define TPM_CnSC_MSB_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4665	#define TPM_CnSC_MSB_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4666	#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
Pawel Zarembski	0:01f31e923fe2	4667	#define TPM_CnSC_CHIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4668	#define TPM_CnSC_CHIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4669	#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4670	#define TPM_CnSC_CHF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4671	#define TPM_CnSC_CHF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4672	#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
Pawel Zarembski	0:01f31e923fe2	4673
Pawel Zarembski	0:01f31e923fe2	4674	/* The count of TPM_CnSC */
Pawel Zarembski	0:01f31e923fe2	4675	#define TPM_CnSC_COUNT (6U)
Pawel Zarembski	0:01f31e923fe2	4676
Pawel Zarembski	0:01f31e923fe2	4677	/! @name CnV - Channel (n) Value /
Pawel Zarembski	0:01f31e923fe2	4678	#define TPM_CnV_VAL_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4679	#define TPM_CnV_VAL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4680	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
Pawel Zarembski	0:01f31e923fe2	4681
Pawel Zarembski	0:01f31e923fe2	4682	/* The count of TPM_CnV */
Pawel Zarembski	0:01f31e923fe2	4683	#define TPM_CnV_COUNT (6U)
Pawel Zarembski	0:01f31e923fe2	4684
Pawel Zarembski	0:01f31e923fe2	4685	/! @name STATUS - Capture and Compare Status /
Pawel Zarembski	0:01f31e923fe2	4686	#define TPM_STATUS_CH0F_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4687	#define TPM_STATUS_CH0F_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4688	#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
Pawel Zarembski	0:01f31e923fe2	4689	#define TPM_STATUS_CH1F_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4690	#define TPM_STATUS_CH1F_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4691	#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
Pawel Zarembski	0:01f31e923fe2	4692	#define TPM_STATUS_CH2F_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4693	#define TPM_STATUS_CH2F_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4694	#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
Pawel Zarembski	0:01f31e923fe2	4695	#define TPM_STATUS_CH3F_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4696	#define TPM_STATUS_CH3F_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4697	#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
Pawel Zarembski	0:01f31e923fe2	4698	#define TPM_STATUS_CH4F_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4699	#define TPM_STATUS_CH4F_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4700	#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
Pawel Zarembski	0:01f31e923fe2	4701	#define TPM_STATUS_CH5F_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4702	#define TPM_STATUS_CH5F_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4703	#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
Pawel Zarembski	0:01f31e923fe2	4704	#define TPM_STATUS_TOF_MASK (0x100U)
Pawel Zarembski	0:01f31e923fe2	4705	#define TPM_STATUS_TOF_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4706	#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
Pawel Zarembski	0:01f31e923fe2	4707
Pawel Zarembski	0:01f31e923fe2	4708	/! @name CONF - Configuration /
Pawel Zarembski	0:01f31e923fe2	4709	#define TPM_CONF_DOZEEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4710	#define TPM_CONF_DOZEEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4711	#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4712	#define TPM_CONF_DBGMODE_MASK (0xC0U)
Pawel Zarembski	0:01f31e923fe2	4713	#define TPM_CONF_DBGMODE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4714	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4715	#define TPM_CONF_GTBEEN_MASK (0x200U)
Pawel Zarembski	0:01f31e923fe2	4716	#define TPM_CONF_GTBEEN_SHIFT (9U)
Pawel Zarembski	0:01f31e923fe2	4717	#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4718	#define TPM_CONF_CSOT_MASK (0x10000U)
Pawel Zarembski	0:01f31e923fe2	4719	#define TPM_CONF_CSOT_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4720	#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
Pawel Zarembski	0:01f31e923fe2	4721	#define TPM_CONF_CSOO_MASK (0x20000U)
Pawel Zarembski	0:01f31e923fe2	4722	#define TPM_CONF_CSOO_SHIFT (17U)
Pawel Zarembski	0:01f31e923fe2	4723	#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
Pawel Zarembski	0:01f31e923fe2	4724	#define TPM_CONF_CROT_MASK (0x40000U)
Pawel Zarembski	0:01f31e923fe2	4725	#define TPM_CONF_CROT_SHIFT (18U)
Pawel Zarembski	0:01f31e923fe2	4726	#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
Pawel Zarembski	0:01f31e923fe2	4727	#define TPM_CONF_TRGSEL_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	4728	#define TPM_CONF_TRGSEL_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4729	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
Pawel Zarembski	0:01f31e923fe2	4730
Pawel Zarembski	0:01f31e923fe2	4731
Pawel Zarembski	0:01f31e923fe2	4732	/*!
Pawel Zarembski	0:01f31e923fe2	4733	* @}
Pawel Zarembski	0:01f31e923fe2	4734	/ / end of group TPM_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4735
Pawel Zarembski	0:01f31e923fe2	4736
Pawel Zarembski	0:01f31e923fe2	4737	/* TPM - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4738	/** Peripheral TPM0 base address */
Pawel Zarembski	0:01f31e923fe2	4739	#define TPM0_BASE (0x40038000u)
Pawel Zarembski	0:01f31e923fe2	4740	/** Peripheral TPM0 base pointer */
Pawel Zarembski	0:01f31e923fe2	4741	#define TPM0 ((TPM_Type *)TPM0_BASE)
Pawel Zarembski	0:01f31e923fe2	4742	/** Peripheral TPM1 base address */
Pawel Zarembski	0:01f31e923fe2	4743	#define TPM1_BASE (0x40039000u)
Pawel Zarembski	0:01f31e923fe2	4744	/** Peripheral TPM1 base pointer */
Pawel Zarembski	0:01f31e923fe2	4745	#define TPM1 ((TPM_Type *)TPM1_BASE)
Pawel Zarembski	0:01f31e923fe2	4746	/** Peripheral TPM2 base address */
Pawel Zarembski	0:01f31e923fe2	4747	#define TPM2_BASE (0x4003A000u)
Pawel Zarembski	0:01f31e923fe2	4748	/** Peripheral TPM2 base pointer */
Pawel Zarembski	0:01f31e923fe2	4749	#define TPM2 ((TPM_Type *)TPM2_BASE)
Pawel Zarembski	0:01f31e923fe2	4750	/** Array initializer of TPM peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4751	#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
Pawel Zarembski	0:01f31e923fe2	4752	/** Array initializer of TPM peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4753	#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
Pawel Zarembski	0:01f31e923fe2	4754	/** Interrupt vectors for the TPM peripheral type */
Pawel Zarembski	0:01f31e923fe2	4755	#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
Pawel Zarembski	0:01f31e923fe2	4756
Pawel Zarembski	0:01f31e923fe2	4757	/*!
Pawel Zarembski	0:01f31e923fe2	4758	* @}
Pawel Zarembski	0:01f31e923fe2	4759	/ / end of group TPM_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4760
Pawel Zarembski	0:01f31e923fe2	4761
Pawel Zarembski	0:01f31e923fe2	4762	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4763	-- TSI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4764	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4765
Pawel Zarembski	0:01f31e923fe2	4766	/*!
Pawel Zarembski	0:01f31e923fe2	4767	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4768	* @{
Pawel Zarembski	0:01f31e923fe2	4769	*/
Pawel Zarembski	0:01f31e923fe2	4770
Pawel Zarembski	0:01f31e923fe2	4771	/** TSI - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4772	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4773	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4774	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4775	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4776	} TSI_Type;
Pawel Zarembski	0:01f31e923fe2	4777
Pawel Zarembski	0:01f31e923fe2	4778	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4779	-- TSI Register Masks
Pawel Zarembski	0:01f31e923fe2	4780	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4781
Pawel Zarembski	0:01f31e923fe2	4782	/*!
Pawel Zarembski	0:01f31e923fe2	4783	* @addtogroup TSI_Register_Masks TSI Register Masks
Pawel Zarembski	0:01f31e923fe2	4784	* @{
Pawel Zarembski	0:01f31e923fe2	4785	*/
Pawel Zarembski	0:01f31e923fe2	4786
Pawel Zarembski	0:01f31e923fe2	4787	/! @name GENCS - TSI General Control and Status Register /
Pawel Zarembski	0:01f31e923fe2	4788	#define TSI_GENCS_CURSW_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4789	#define TSI_GENCS_CURSW_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4790	#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
Pawel Zarembski	0:01f31e923fe2	4791	#define TSI_GENCS_EOSF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4792	#define TSI_GENCS_EOSF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4793	#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
Pawel Zarembski	0:01f31e923fe2	4794	#define TSI_GENCS_SCNIP_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4795	#define TSI_GENCS_SCNIP_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4796	#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
Pawel Zarembski	0:01f31e923fe2	4797	#define TSI_GENCS_STM_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4798	#define TSI_GENCS_STM_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4799	#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
Pawel Zarembski	0:01f31e923fe2	4800	#define TSI_GENCS_STPE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4801	#define TSI_GENCS_STPE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4802	#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
Pawel Zarembski	0:01f31e923fe2	4803	#define TSI_GENCS_TSIIEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4804	#define TSI_GENCS_TSIIEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4805	#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4806	#define TSI_GENCS_TSIEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4807	#define TSI_GENCS_TSIEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4808	#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4809	#define TSI_GENCS_NSCN_MASK (0x1F00U)
Pawel Zarembski	0:01f31e923fe2	4810	#define TSI_GENCS_NSCN_SHIFT (8U)
Pawel Zarembski	0:01f31e923fe2	4811	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
Pawel Zarembski	0:01f31e923fe2	4812	#define TSI_GENCS_PS_MASK (0xE000U)
Pawel Zarembski	0:01f31e923fe2	4813	#define TSI_GENCS_PS_SHIFT (13U)
Pawel Zarembski	0:01f31e923fe2	4814	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
Pawel Zarembski	0:01f31e923fe2	4815	#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
Pawel Zarembski	0:01f31e923fe2	4816	#define TSI_GENCS_EXTCHRG_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4817	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
Pawel Zarembski	0:01f31e923fe2	4818	#define TSI_GENCS_DVOLT_MASK (0x180000U)
Pawel Zarembski	0:01f31e923fe2	4819	#define TSI_GENCS_DVOLT_SHIFT (19U)
Pawel Zarembski	0:01f31e923fe2	4820	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
Pawel Zarembski	0:01f31e923fe2	4821	#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
Pawel Zarembski	0:01f31e923fe2	4822	#define TSI_GENCS_REFCHRG_SHIFT (21U)
Pawel Zarembski	0:01f31e923fe2	4823	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
Pawel Zarembski	0:01f31e923fe2	4824	#define TSI_GENCS_MODE_MASK (0xF000000U)
Pawel Zarembski	0:01f31e923fe2	4825	#define TSI_GENCS_MODE_SHIFT (24U)
Pawel Zarembski	0:01f31e923fe2	4826	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
Pawel Zarembski	0:01f31e923fe2	4827	#define TSI_GENCS_ESOR_MASK (0x10000000U)
Pawel Zarembski	0:01f31e923fe2	4828	#define TSI_GENCS_ESOR_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	4829	#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
Pawel Zarembski	0:01f31e923fe2	4830	#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
Pawel Zarembski	0:01f31e923fe2	4831	#define TSI_GENCS_OUTRGF_SHIFT (31U)
Pawel Zarembski	0:01f31e923fe2	4832	#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
Pawel Zarembski	0:01f31e923fe2	4833
Pawel Zarembski	0:01f31e923fe2	4834	/! @name DATA - TSI DATA Register /
Pawel Zarembski	0:01f31e923fe2	4835	#define TSI_DATA_TSICNT_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4836	#define TSI_DATA_TSICNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4837	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
Pawel Zarembski	0:01f31e923fe2	4838	#define TSI_DATA_SWTS_MASK (0x400000U)
Pawel Zarembski	0:01f31e923fe2	4839	#define TSI_DATA_SWTS_SHIFT (22U)
Pawel Zarembski	0:01f31e923fe2	4840	#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
Pawel Zarembski	0:01f31e923fe2	4841	#define TSI_DATA_DMAEN_MASK (0x800000U)
Pawel Zarembski	0:01f31e923fe2	4842	#define TSI_DATA_DMAEN_SHIFT (23U)
Pawel Zarembski	0:01f31e923fe2	4843	#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
Pawel Zarembski	0:01f31e923fe2	4844	#define TSI_DATA_TSICH_MASK (0xF0000000U)
Pawel Zarembski	0:01f31e923fe2	4845	#define TSI_DATA_TSICH_SHIFT (28U)
Pawel Zarembski	0:01f31e923fe2	4846	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
Pawel Zarembski	0:01f31e923fe2	4847
Pawel Zarembski	0:01f31e923fe2	4848	/! @name TSHD - TSI Threshold Register /
Pawel Zarembski	0:01f31e923fe2	4849	#define TSI_TSHD_THRESL_MASK (0xFFFFU)
Pawel Zarembski	0:01f31e923fe2	4850	#define TSI_TSHD_THRESL_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4851	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
Pawel Zarembski	0:01f31e923fe2	4852	#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
Pawel Zarembski	0:01f31e923fe2	4853	#define TSI_TSHD_THRESH_SHIFT (16U)
Pawel Zarembski	0:01f31e923fe2	4854	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
Pawel Zarembski	0:01f31e923fe2	4855
Pawel Zarembski	0:01f31e923fe2	4856
Pawel Zarembski	0:01f31e923fe2	4857	/*!
Pawel Zarembski	0:01f31e923fe2	4858	* @}
Pawel Zarembski	0:01f31e923fe2	4859	/ / end of group TSI_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	4860
Pawel Zarembski	0:01f31e923fe2	4861
Pawel Zarembski	0:01f31e923fe2	4862	/* TSI - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	4863	/** Peripheral TSI0 base address */
Pawel Zarembski	0:01f31e923fe2	4864	#define TSI0_BASE (0x40045000u)
Pawel Zarembski	0:01f31e923fe2	4865	/** Peripheral TSI0 base pointer */
Pawel Zarembski	0:01f31e923fe2	4866	#define TSI0 ((TSI_Type *)TSI0_BASE)
Pawel Zarembski	0:01f31e923fe2	4867	/** Array initializer of TSI peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	4868	#define TSI_BASE_ADDRS { TSI0_BASE }
Pawel Zarembski	0:01f31e923fe2	4869	/** Array initializer of TSI peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	4870	#define TSI_BASE_PTRS { TSI0 }
Pawel Zarembski	0:01f31e923fe2	4871	/** Interrupt vectors for the TSI peripheral type */
Pawel Zarembski	0:01f31e923fe2	4872	#define TSI_IRQS { TSI0_IRQn }
Pawel Zarembski	0:01f31e923fe2	4873
Pawel Zarembski	0:01f31e923fe2	4874	/*!
Pawel Zarembski	0:01f31e923fe2	4875	* @}
Pawel Zarembski	0:01f31e923fe2	4876	/ / end of group TSI_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	4877
Pawel Zarembski	0:01f31e923fe2	4878
Pawel Zarembski	0:01f31e923fe2	4879	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4880	-- UART Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4881	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4882
Pawel Zarembski	0:01f31e923fe2	4883	/*!
Pawel Zarembski	0:01f31e923fe2	4884	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	4885	* @{
Pawel Zarembski	0:01f31e923fe2	4886	*/
Pawel Zarembski	0:01f31e923fe2	4887
Pawel Zarembski	0:01f31e923fe2	4888	/** UART - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	4889	typedef struct {
Pawel Zarembski	0:01f31e923fe2	4890	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	4891	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	4892	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	4893	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	4894	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	4895	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	4896	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	4897	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	4898	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	4899	} UART_Type;
Pawel Zarembski	0:01f31e923fe2	4900
Pawel Zarembski	0:01f31e923fe2	4901	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	4902	-- UART Register Masks
Pawel Zarembski	0:01f31e923fe2	4903	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	4904
Pawel Zarembski	0:01f31e923fe2	4905	/*!
Pawel Zarembski	0:01f31e923fe2	4906	* @addtogroup UART_Register_Masks UART Register Masks
Pawel Zarembski	0:01f31e923fe2	4907	* @{
Pawel Zarembski	0:01f31e923fe2	4908	*/
Pawel Zarembski	0:01f31e923fe2	4909
Pawel Zarembski	0:01f31e923fe2	4910	/! @name BDH - UART Baud Rate Register: High /
Pawel Zarembski	0:01f31e923fe2	4911	#define UART_BDH_SBR_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	4912	#define UART_BDH_SBR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4913	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
Pawel Zarembski	0:01f31e923fe2	4914	#define UART_BDH_SBNS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4915	#define UART_BDH_SBNS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4916	#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
Pawel Zarembski	0:01f31e923fe2	4917	#define UART_BDH_RXEDGIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4918	#define UART_BDH_RXEDGIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4919	#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4920	#define UART_BDH_LBKDIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4921	#define UART_BDH_LBKDIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4922	#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4923
Pawel Zarembski	0:01f31e923fe2	4924	/! @name BDL - UART Baud Rate Register: Low /
Pawel Zarembski	0:01f31e923fe2	4925	#define UART_BDL_SBR_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	4926	#define UART_BDL_SBR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4927	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
Pawel Zarembski	0:01f31e923fe2	4928
Pawel Zarembski	0:01f31e923fe2	4929	/! @name C1 - UART Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	4930	#define UART_C1_PT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4931	#define UART_C1_PT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4932	#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
Pawel Zarembski	0:01f31e923fe2	4933	#define UART_C1_PE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4934	#define UART_C1_PE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4935	#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
Pawel Zarembski	0:01f31e923fe2	4936	#define UART_C1_ILT_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4937	#define UART_C1_ILT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4938	#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
Pawel Zarembski	0:01f31e923fe2	4939	#define UART_C1_WAKE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4940	#define UART_C1_WAKE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4941	#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
Pawel Zarembski	0:01f31e923fe2	4942	#define UART_C1_M_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4943	#define UART_C1_M_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4944	#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
Pawel Zarembski	0:01f31e923fe2	4945	#define UART_C1_RSRC_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4946	#define UART_C1_RSRC_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4947	#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	4948	#define UART_C1_UARTSWAI_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4949	#define UART_C1_UARTSWAI_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4950	#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
Pawel Zarembski	0:01f31e923fe2	4951	#define UART_C1_LOOPS_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4952	#define UART_C1_LOOPS_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4953	#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
Pawel Zarembski	0:01f31e923fe2	4954
Pawel Zarembski	0:01f31e923fe2	4955	/! @name C2 - UART Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	4956	#define UART_C2_SBK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4957	#define UART_C2_SBK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4958	#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
Pawel Zarembski	0:01f31e923fe2	4959	#define UART_C2_RWU_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4960	#define UART_C2_RWU_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4961	#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
Pawel Zarembski	0:01f31e923fe2	4962	#define UART_C2_RE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4963	#define UART_C2_RE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4964	#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	4965	#define UART_C2_TE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4966	#define UART_C2_TE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4967	#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
Pawel Zarembski	0:01f31e923fe2	4968	#define UART_C2_ILIE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4969	#define UART_C2_ILIE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4970	#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4971	#define UART_C2_RIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4972	#define UART_C2_RIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4973	#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4974	#define UART_C2_TCIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	4975	#define UART_C2_TCIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	4976	#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4977	#define UART_C2_TIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	4978	#define UART_C2_TIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	4979	#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	4980
Pawel Zarembski	0:01f31e923fe2	4981	/! @name S1 - UART Status Register 1 /
Pawel Zarembski	0:01f31e923fe2	4982	#define UART_S1_PF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	4983	#define UART_S1_PF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	4984	#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
Pawel Zarembski	0:01f31e923fe2	4985	#define UART_S1_FE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	4986	#define UART_S1_FE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	4987	#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
Pawel Zarembski	0:01f31e923fe2	4988	#define UART_S1_NF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	4989	#define UART_S1_NF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	4990	#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
Pawel Zarembski	0:01f31e923fe2	4991	#define UART_S1_OR_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	4992	#define UART_S1_OR_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	4993	#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
Pawel Zarembski	0:01f31e923fe2	4994	#define UART_S1_IDLE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	4995	#define UART_S1_IDLE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	4996	#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
Pawel Zarembski	0:01f31e923fe2	4997	#define UART_S1_RDRF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	4998	#define UART_S1_RDRF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	4999	#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
Pawel Zarembski	0:01f31e923fe2	5000	#define UART_S1_TC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5001	#define UART_S1_TC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5002	#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
Pawel Zarembski	0:01f31e923fe2	5003	#define UART_S1_TDRE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5004	#define UART_S1_TDRE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5005	#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
Pawel Zarembski	0:01f31e923fe2	5006
Pawel Zarembski	0:01f31e923fe2	5007	/! @name S2 - UART Status Register 2 /
Pawel Zarembski	0:01f31e923fe2	5008	#define UART_S2_RAF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5009	#define UART_S2_RAF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5010	#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
Pawel Zarembski	0:01f31e923fe2	5011	#define UART_S2_LBKDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5012	#define UART_S2_LBKDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5013	#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
Pawel Zarembski	0:01f31e923fe2	5014	#define UART_S2_BRK13_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5015	#define UART_S2_BRK13_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5016	#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
Pawel Zarembski	0:01f31e923fe2	5017	#define UART_S2_RWUID_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5018	#define UART_S2_RWUID_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5019	#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
Pawel Zarembski	0:01f31e923fe2	5020	#define UART_S2_RXINV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5021	#define UART_S2_RXINV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5022	#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
Pawel Zarembski	0:01f31e923fe2	5023	#define UART_S2_RXEDGIF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5024	#define UART_S2_RXEDGIF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5025	#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
Pawel Zarembski	0:01f31e923fe2	5026	#define UART_S2_LBKDIF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5027	#define UART_S2_LBKDIF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5028	#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
Pawel Zarembski	0:01f31e923fe2	5029
Pawel Zarembski	0:01f31e923fe2	5030	/! @name C3 - UART Control Register 3 /
Pawel Zarembski	0:01f31e923fe2	5031	#define UART_C3_PEIE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5032	#define UART_C3_PEIE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5033	#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5034	#define UART_C3_FEIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5035	#define UART_C3_FEIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5036	#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5037	#define UART_C3_NEIE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5038	#define UART_C3_NEIE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5039	#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5040	#define UART_C3_ORIE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5041	#define UART_C3_ORIE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5042	#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5043	#define UART_C3_TXINV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5044	#define UART_C3_TXINV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5045	#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
Pawel Zarembski	0:01f31e923fe2	5046	#define UART_C3_TXDIR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5047	#define UART_C3_TXDIR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5048	#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
Pawel Zarembski	0:01f31e923fe2	5049	#define UART_C3_T8_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5050	#define UART_C3_T8_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5051	#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
Pawel Zarembski	0:01f31e923fe2	5052	#define UART_C3_R8_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5053	#define UART_C3_R8_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5054	#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
Pawel Zarembski	0:01f31e923fe2	5055
Pawel Zarembski	0:01f31e923fe2	5056	/! @name D - UART Data Register /
Pawel Zarembski	0:01f31e923fe2	5057	#define UART_D_R0T0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5058	#define UART_D_R0T0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5059	#define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK)
Pawel Zarembski	0:01f31e923fe2	5060	#define UART_D_R1T1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5061	#define UART_D_R1T1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5062	#define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK)
Pawel Zarembski	0:01f31e923fe2	5063	#define UART_D_R2T2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5064	#define UART_D_R2T2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5065	#define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK)
Pawel Zarembski	0:01f31e923fe2	5066	#define UART_D_R3T3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5067	#define UART_D_R3T3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5068	#define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK)
Pawel Zarembski	0:01f31e923fe2	5069	#define UART_D_R4T4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5070	#define UART_D_R4T4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5071	#define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK)
Pawel Zarembski	0:01f31e923fe2	5072	#define UART_D_R5T5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5073	#define UART_D_R5T5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5074	#define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK)
Pawel Zarembski	0:01f31e923fe2	5075	#define UART_D_R6T6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5076	#define UART_D_R6T6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5077	#define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK)
Pawel Zarembski	0:01f31e923fe2	5078	#define UART_D_R7T7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5079	#define UART_D_R7T7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5080	#define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK)
Pawel Zarembski	0:01f31e923fe2	5081
Pawel Zarembski	0:01f31e923fe2	5082	/! @name C4 - UART Control Register 4 /
Pawel Zarembski	0:01f31e923fe2	5083	#define UART_C4_RDMAS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5084	#define UART_C4_RDMAS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5085	#define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK)
Pawel Zarembski	0:01f31e923fe2	5086	#define UART_C4_TDMAS_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5087	#define UART_C4_TDMAS_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5088	#define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK)
Pawel Zarembski	0:01f31e923fe2	5089
Pawel Zarembski	0:01f31e923fe2	5090
Pawel Zarembski	0:01f31e923fe2	5091	/*!
Pawel Zarembski	0:01f31e923fe2	5092	* @}
Pawel Zarembski	0:01f31e923fe2	5093	/ / end of group UART_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5094
Pawel Zarembski	0:01f31e923fe2	5095
Pawel Zarembski	0:01f31e923fe2	5096	/* UART - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5097	/** Peripheral UART1 base address */
Pawel Zarembski	0:01f31e923fe2	5098	#define UART1_BASE (0x4006B000u)
Pawel Zarembski	0:01f31e923fe2	5099	/** Peripheral UART1 base pointer */
Pawel Zarembski	0:01f31e923fe2	5100	#define UART1 ((UART_Type *)UART1_BASE)
Pawel Zarembski	0:01f31e923fe2	5101	/** Peripheral UART2 base address */
Pawel Zarembski	0:01f31e923fe2	5102	#define UART2_BASE (0x4006C000u)
Pawel Zarembski	0:01f31e923fe2	5103	/** Peripheral UART2 base pointer */
Pawel Zarembski	0:01f31e923fe2	5104	#define UART2 ((UART_Type *)UART2_BASE)
Pawel Zarembski	0:01f31e923fe2	5105	/** Array initializer of UART peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5106	#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE }
Pawel Zarembski	0:01f31e923fe2	5107	/** Array initializer of UART peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5108	#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 }
Pawel Zarembski	0:01f31e923fe2	5109	/** Interrupt vectors for the UART peripheral type */
Pawel Zarembski	0:01f31e923fe2	5110	#define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
Pawel Zarembski	0:01f31e923fe2	5111	#define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
Pawel Zarembski	0:01f31e923fe2	5112
Pawel Zarembski	0:01f31e923fe2	5113	/*!
Pawel Zarembski	0:01f31e923fe2	5114	* @}
Pawel Zarembski	0:01f31e923fe2	5115	/ / end of group UART_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5116
Pawel Zarembski	0:01f31e923fe2	5117
Pawel Zarembski	0:01f31e923fe2	5118	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5119	-- UART0 Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5120	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5121
Pawel Zarembski	0:01f31e923fe2	5122	/*!
Pawel Zarembski	0:01f31e923fe2	5123	* @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5124	* @{
Pawel Zarembski	0:01f31e923fe2	5125	*/
Pawel Zarembski	0:01f31e923fe2	5126
Pawel Zarembski	0:01f31e923fe2	5127	/** UART0 - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	5128	typedef struct {
Pawel Zarembski	0:01f31e923fe2	5129	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	5130	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
Pawel Zarembski	0:01f31e923fe2	5131	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
Pawel Zarembski	0:01f31e923fe2	5132	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
Pawel Zarembski	0:01f31e923fe2	5133	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5134	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
Pawel Zarembski	0:01f31e923fe2	5135	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
Pawel Zarembski	0:01f31e923fe2	5136	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
Pawel Zarembski	0:01f31e923fe2	5137	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	5138	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
Pawel Zarembski	0:01f31e923fe2	5139	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
Pawel Zarembski	0:01f31e923fe2	5140	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
Pawel Zarembski	0:01f31e923fe2	5141	} UART0_Type;
Pawel Zarembski	0:01f31e923fe2	5142
Pawel Zarembski	0:01f31e923fe2	5143	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5144	-- UART0 Register Masks
Pawel Zarembski	0:01f31e923fe2	5145	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5146
Pawel Zarembski	0:01f31e923fe2	5147	/*!
Pawel Zarembski	0:01f31e923fe2	5148	* @addtogroup UART0_Register_Masks UART0 Register Masks
Pawel Zarembski	0:01f31e923fe2	5149	* @{
Pawel Zarembski	0:01f31e923fe2	5150	*/
Pawel Zarembski	0:01f31e923fe2	5151
Pawel Zarembski	0:01f31e923fe2	5152	/! @name BDH - UART Baud Rate Register High /
Pawel Zarembski	0:01f31e923fe2	5153	#define UART0_BDH_SBR_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	5154	#define UART0_BDH_SBR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5155	#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK)
Pawel Zarembski	0:01f31e923fe2	5156	#define UART0_BDH_SBNS_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5157	#define UART0_BDH_SBNS_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5158	#define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK)
Pawel Zarembski	0:01f31e923fe2	5159	#define UART0_BDH_RXEDGIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5160	#define UART0_BDH_RXEDGIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5161	#define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5162	#define UART0_BDH_LBKDIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5163	#define UART0_BDH_LBKDIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5164	#define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5165
Pawel Zarembski	0:01f31e923fe2	5166	/! @name BDL - UART Baud Rate Register Low /
Pawel Zarembski	0:01f31e923fe2	5167	#define UART0_BDL_SBR_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5168	#define UART0_BDL_SBR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5169	#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK)
Pawel Zarembski	0:01f31e923fe2	5170
Pawel Zarembski	0:01f31e923fe2	5171	/! @name C1 - UART Control Register 1 /
Pawel Zarembski	0:01f31e923fe2	5172	#define UART0_C1_PT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5173	#define UART0_C1_PT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5174	#define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK)
Pawel Zarembski	0:01f31e923fe2	5175	#define UART0_C1_PE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5176	#define UART0_C1_PE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5177	#define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK)
Pawel Zarembski	0:01f31e923fe2	5178	#define UART0_C1_ILT_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5179	#define UART0_C1_ILT_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5180	#define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK)
Pawel Zarembski	0:01f31e923fe2	5181	#define UART0_C1_WAKE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5182	#define UART0_C1_WAKE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5183	#define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK)
Pawel Zarembski	0:01f31e923fe2	5184	#define UART0_C1_M_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5185	#define UART0_C1_M_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5186	#define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK)
Pawel Zarembski	0:01f31e923fe2	5187	#define UART0_C1_RSRC_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5188	#define UART0_C1_RSRC_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5189	#define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK)
Pawel Zarembski	0:01f31e923fe2	5190	#define UART0_C1_DOZEEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5191	#define UART0_C1_DOZEEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5192	#define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5193	#define UART0_C1_LOOPS_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5194	#define UART0_C1_LOOPS_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5195	#define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK)
Pawel Zarembski	0:01f31e923fe2	5196
Pawel Zarembski	0:01f31e923fe2	5197	/! @name C2 - UART Control Register 2 /
Pawel Zarembski	0:01f31e923fe2	5198	#define UART0_C2_SBK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5199	#define UART0_C2_SBK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5200	#define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK)
Pawel Zarembski	0:01f31e923fe2	5201	#define UART0_C2_RWU_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5202	#define UART0_C2_RWU_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5203	#define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK)
Pawel Zarembski	0:01f31e923fe2	5204	#define UART0_C2_RE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5205	#define UART0_C2_RE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5206	#define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK)
Pawel Zarembski	0:01f31e923fe2	5207	#define UART0_C2_TE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5208	#define UART0_C2_TE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5209	#define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK)
Pawel Zarembski	0:01f31e923fe2	5210	#define UART0_C2_ILIE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5211	#define UART0_C2_ILIE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5212	#define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5213	#define UART0_C2_RIE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5214	#define UART0_C2_RIE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5215	#define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5216	#define UART0_C2_TCIE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5217	#define UART0_C2_TCIE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5218	#define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5219	#define UART0_C2_TIE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5220	#define UART0_C2_TIE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5221	#define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5222
Pawel Zarembski	0:01f31e923fe2	5223	/! @name S1 - UART Status Register 1 /
Pawel Zarembski	0:01f31e923fe2	5224	#define UART0_S1_PF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5225	#define UART0_S1_PF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5226	#define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK)
Pawel Zarembski	0:01f31e923fe2	5227	#define UART0_S1_FE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5228	#define UART0_S1_FE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5229	#define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK)
Pawel Zarembski	0:01f31e923fe2	5230	#define UART0_S1_NF_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5231	#define UART0_S1_NF_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5232	#define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK)
Pawel Zarembski	0:01f31e923fe2	5233	#define UART0_S1_OR_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5234	#define UART0_S1_OR_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5235	#define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK)
Pawel Zarembski	0:01f31e923fe2	5236	#define UART0_S1_IDLE_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5237	#define UART0_S1_IDLE_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5238	#define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK)
Pawel Zarembski	0:01f31e923fe2	5239	#define UART0_S1_RDRF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5240	#define UART0_S1_RDRF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5241	#define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK)
Pawel Zarembski	0:01f31e923fe2	5242	#define UART0_S1_TC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5243	#define UART0_S1_TC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5244	#define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK)
Pawel Zarembski	0:01f31e923fe2	5245	#define UART0_S1_TDRE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5246	#define UART0_S1_TDRE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5247	#define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK)
Pawel Zarembski	0:01f31e923fe2	5248
Pawel Zarembski	0:01f31e923fe2	5249	/! @name S2 - UART Status Register 2 /
Pawel Zarembski	0:01f31e923fe2	5250	#define UART0_S2_RAF_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5251	#define UART0_S2_RAF_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5252	#define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK)
Pawel Zarembski	0:01f31e923fe2	5253	#define UART0_S2_LBKDE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5254	#define UART0_S2_LBKDE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5255	#define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK)
Pawel Zarembski	0:01f31e923fe2	5256	#define UART0_S2_BRK13_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5257	#define UART0_S2_BRK13_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5258	#define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK)
Pawel Zarembski	0:01f31e923fe2	5259	#define UART0_S2_RWUID_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5260	#define UART0_S2_RWUID_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5261	#define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK)
Pawel Zarembski	0:01f31e923fe2	5262	#define UART0_S2_RXINV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5263	#define UART0_S2_RXINV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5264	#define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK)
Pawel Zarembski	0:01f31e923fe2	5265	#define UART0_S2_MSBF_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5266	#define UART0_S2_MSBF_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5267	#define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK)
Pawel Zarembski	0:01f31e923fe2	5268	#define UART0_S2_RXEDGIF_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5269	#define UART0_S2_RXEDGIF_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5270	#define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK)
Pawel Zarembski	0:01f31e923fe2	5271	#define UART0_S2_LBKDIF_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5272	#define UART0_S2_LBKDIF_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5273	#define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK)
Pawel Zarembski	0:01f31e923fe2	5274
Pawel Zarembski	0:01f31e923fe2	5275	/! @name C3 - UART Control Register 3 /
Pawel Zarembski	0:01f31e923fe2	5276	#define UART0_C3_PEIE_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5277	#define UART0_C3_PEIE_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5278	#define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5279	#define UART0_C3_FEIE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5280	#define UART0_C3_FEIE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5281	#define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5282	#define UART0_C3_NEIE_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5283	#define UART0_C3_NEIE_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5284	#define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5285	#define UART0_C3_ORIE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5286	#define UART0_C3_ORIE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5287	#define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK)
Pawel Zarembski	0:01f31e923fe2	5288	#define UART0_C3_TXINV_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5289	#define UART0_C3_TXINV_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5290	#define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK)
Pawel Zarembski	0:01f31e923fe2	5291	#define UART0_C3_TXDIR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5292	#define UART0_C3_TXDIR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5293	#define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK)
Pawel Zarembski	0:01f31e923fe2	5294	#define UART0_C3_R9T8_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5295	#define UART0_C3_R9T8_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5296	#define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK)
Pawel Zarembski	0:01f31e923fe2	5297	#define UART0_C3_R8T9_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5298	#define UART0_C3_R8T9_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5299	#define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK)
Pawel Zarembski	0:01f31e923fe2	5300
Pawel Zarembski	0:01f31e923fe2	5301	/! @name D - UART Data Register /
Pawel Zarembski	0:01f31e923fe2	5302	#define UART0_D_R0T0_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5303	#define UART0_D_R0T0_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5304	#define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK)
Pawel Zarembski	0:01f31e923fe2	5305	#define UART0_D_R1T1_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5306	#define UART0_D_R1T1_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5307	#define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK)
Pawel Zarembski	0:01f31e923fe2	5308	#define UART0_D_R2T2_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5309	#define UART0_D_R2T2_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5310	#define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK)
Pawel Zarembski	0:01f31e923fe2	5311	#define UART0_D_R3T3_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5312	#define UART0_D_R3T3_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5313	#define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK)
Pawel Zarembski	0:01f31e923fe2	5314	#define UART0_D_R4T4_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5315	#define UART0_D_R4T4_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5316	#define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK)
Pawel Zarembski	0:01f31e923fe2	5317	#define UART0_D_R5T5_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5318	#define UART0_D_R5T5_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5319	#define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK)
Pawel Zarembski	0:01f31e923fe2	5320	#define UART0_D_R6T6_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5321	#define UART0_D_R6T6_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5322	#define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK)
Pawel Zarembski	0:01f31e923fe2	5323	#define UART0_D_R7T7_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5324	#define UART0_D_R7T7_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5325	#define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK)
Pawel Zarembski	0:01f31e923fe2	5326
Pawel Zarembski	0:01f31e923fe2	5327	/! @name MA1 - UART Match Address Registers 1 /
Pawel Zarembski	0:01f31e923fe2	5328	#define UART0_MA1_MA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5329	#define UART0_MA1_MA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5330	#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK)
Pawel Zarembski	0:01f31e923fe2	5331
Pawel Zarembski	0:01f31e923fe2	5332	/! @name MA2 - UART Match Address Registers 2 /
Pawel Zarembski	0:01f31e923fe2	5333	#define UART0_MA2_MA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5334	#define UART0_MA2_MA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5335	#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK)
Pawel Zarembski	0:01f31e923fe2	5336
Pawel Zarembski	0:01f31e923fe2	5337	/! @name C4 - UART Control Register 4 /
Pawel Zarembski	0:01f31e923fe2	5338	#define UART0_C4_OSR_MASK (0x1FU)
Pawel Zarembski	0:01f31e923fe2	5339	#define UART0_C4_OSR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5340	#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK)
Pawel Zarembski	0:01f31e923fe2	5341	#define UART0_C4_M10_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5342	#define UART0_C4_M10_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5343	#define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK)
Pawel Zarembski	0:01f31e923fe2	5344	#define UART0_C4_MAEN2_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5345	#define UART0_C4_MAEN2_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5346	#define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK)
Pawel Zarembski	0:01f31e923fe2	5347	#define UART0_C4_MAEN1_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5348	#define UART0_C4_MAEN1_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5349	#define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK)
Pawel Zarembski	0:01f31e923fe2	5350
Pawel Zarembski	0:01f31e923fe2	5351	/! @name C5 - UART Control Register 5 /
Pawel Zarembski	0:01f31e923fe2	5352	#define UART0_C5_RESYNCDIS_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5353	#define UART0_C5_RESYNCDIS_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5354	#define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	5355	#define UART0_C5_BOTHEDGE_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5356	#define UART0_C5_BOTHEDGE_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5357	#define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK)
Pawel Zarembski	0:01f31e923fe2	5358	#define UART0_C5_RDMAE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5359	#define UART0_C5_RDMAE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5360	#define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK)
Pawel Zarembski	0:01f31e923fe2	5361	#define UART0_C5_TDMAE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5362	#define UART0_C5_TDMAE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5363	#define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK)
Pawel Zarembski	0:01f31e923fe2	5364
Pawel Zarembski	0:01f31e923fe2	5365
Pawel Zarembski	0:01f31e923fe2	5366	/*!
Pawel Zarembski	0:01f31e923fe2	5367	* @}
Pawel Zarembski	0:01f31e923fe2	5368	/ / end of group UART0_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5369
Pawel Zarembski	0:01f31e923fe2	5370
Pawel Zarembski	0:01f31e923fe2	5371	/* UART0 - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5372	/** Peripheral UART0 base address */
Pawel Zarembski	0:01f31e923fe2	5373	#define UART0_BASE (0x4006A000u)
Pawel Zarembski	0:01f31e923fe2	5374	/** Peripheral UART0 base pointer */
Pawel Zarembski	0:01f31e923fe2	5375	#define UART0 ((UART0_Type *)UART0_BASE)
Pawel Zarembski	0:01f31e923fe2	5376	/** Array initializer of UART0 peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5377	#define UART0_BASE_ADDRS { UART0_BASE }
Pawel Zarembski	0:01f31e923fe2	5378	/** Array initializer of UART0 peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5379	#define UART0_BASE_PTRS { UART0 }
Pawel Zarembski	0:01f31e923fe2	5380	/** Interrupt vectors for the UART0 peripheral type */
Pawel Zarembski	0:01f31e923fe2	5381	#define UART0_RX_TX_IRQS { UART0_IRQn }
Pawel Zarembski	0:01f31e923fe2	5382	#define UART0_ERR_IRQS { UART0_IRQn }
Pawel Zarembski	0:01f31e923fe2	5383
Pawel Zarembski	0:01f31e923fe2	5384	/*!
Pawel Zarembski	0:01f31e923fe2	5385	* @}
Pawel Zarembski	0:01f31e923fe2	5386	/ / end of group UART0_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5387
Pawel Zarembski	0:01f31e923fe2	5388
Pawel Zarembski	0:01f31e923fe2	5389	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5390	-- USB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5391	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5392
Pawel Zarembski	0:01f31e923fe2	5393	/*!
Pawel Zarembski	0:01f31e923fe2	5394	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Pawel Zarembski	0:01f31e923fe2	5395	* @{
Pawel Zarembski	0:01f31e923fe2	5396	*/
Pawel Zarembski	0:01f31e923fe2	5397
Pawel Zarembski	0:01f31e923fe2	5398	/** USB - Register Layout Typedef */
Pawel Zarembski	0:01f31e923fe2	5399	typedef struct {
Pawel Zarembski	0:01f31e923fe2	5400	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
Pawel Zarembski	0:01f31e923fe2	5401	uint8_t RESERVED_0[3];
Pawel Zarembski	0:01f31e923fe2	5402	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5403	uint8_t RESERVED_1[3];
Pawel Zarembski	0:01f31e923fe2	5404	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
Pawel Zarembski	0:01f31e923fe2	5405	uint8_t RESERVED_2[3];
Pawel Zarembski	0:01f31e923fe2	5406	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
Pawel Zarembski	0:01f31e923fe2	5407	uint8_t RESERVED_3[3];
Pawel Zarembski	0:01f31e923fe2	5408	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
Pawel Zarembski	0:01f31e923fe2	5409	uint8_t RESERVED_4[3];
Pawel Zarembski	0:01f31e923fe2	5410	__IO uint8_t OTGICR; /*< OTG Interrupt Control register, offset: 0x14 /
Pawel Zarembski	0:01f31e923fe2	5411	uint8_t RESERVED_5[3];
Pawel Zarembski	0:01f31e923fe2	5412	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
Pawel Zarembski	0:01f31e923fe2	5413	uint8_t RESERVED_6[3];
Pawel Zarembski	0:01f31e923fe2	5414	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
Pawel Zarembski	0:01f31e923fe2	5415	uint8_t RESERVED_7[99];
Pawel Zarembski	0:01f31e923fe2	5416	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
Pawel Zarembski	0:01f31e923fe2	5417	uint8_t RESERVED_8[3];
Pawel Zarembski	0:01f31e923fe2	5418	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
Pawel Zarembski	0:01f31e923fe2	5419	uint8_t RESERVED_9[3];
Pawel Zarembski	0:01f31e923fe2	5420	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
Pawel Zarembski	0:01f31e923fe2	5421	uint8_t RESERVED_10[3];
Pawel Zarembski	0:01f31e923fe2	5422	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
Pawel Zarembski	0:01f31e923fe2	5423	uint8_t RESERVED_11[3];
Pawel Zarembski	0:01f31e923fe2	5424	__I uint8_t STAT; /*< Status register, offset: 0x90 /
Pawel Zarembski	0:01f31e923fe2	5425	uint8_t RESERVED_12[3];
Pawel Zarembski	0:01f31e923fe2	5426	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
Pawel Zarembski	0:01f31e923fe2	5427	uint8_t RESERVED_13[3];
Pawel Zarembski	0:01f31e923fe2	5428	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
Pawel Zarembski	0:01f31e923fe2	5429	uint8_t RESERVED_14[3];
Pawel Zarembski	0:01f31e923fe2	5430	__IO uint8_t BDTPAGE1; /*< BDT Page register 1, offset: 0x9C /
Pawel Zarembski	0:01f31e923fe2	5431	uint8_t RESERVED_15[3];
Pawel Zarembski	0:01f31e923fe2	5432	__IO uint8_t FRMNUML; /*< Frame Number register Low, offset: 0xA0 /
Pawel Zarembski	0:01f31e923fe2	5433	uint8_t RESERVED_16[3];
Pawel Zarembski	0:01f31e923fe2	5434	__IO uint8_t FRMNUMH; /*< Frame Number register High, offset: 0xA4 /
Pawel Zarembski	0:01f31e923fe2	5435	uint8_t RESERVED_17[3];
Pawel Zarembski	0:01f31e923fe2	5436	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
Pawel Zarembski	0:01f31e923fe2	5437	uint8_t RESERVED_18[3];
Pawel Zarembski	0:01f31e923fe2	5438	__IO uint8_t SOFTHLD; /*< SOF Threshold register, offset: 0xAC /
Pawel Zarembski	0:01f31e923fe2	5439	uint8_t RESERVED_19[3];
Pawel Zarembski	0:01f31e923fe2	5440	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
Pawel Zarembski	0:01f31e923fe2	5441	uint8_t RESERVED_20[3];
Pawel Zarembski	0:01f31e923fe2	5442	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
Pawel Zarembski	0:01f31e923fe2	5443	uint8_t RESERVED_21[11];
Pawel Zarembski	0:01f31e923fe2	5444	struct { /* offset: 0xC0, array step: 0x4 */
Pawel Zarembski	0:01f31e923fe2	5445	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
Pawel Zarembski	0:01f31e923fe2	5446	uint8_t RESERVED_0[3];
Pawel Zarembski	0:01f31e923fe2	5447	} ENDPOINT[16];
Pawel Zarembski	0:01f31e923fe2	5448	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
Pawel Zarembski	0:01f31e923fe2	5449	uint8_t RESERVED_22[3];
Pawel Zarembski	0:01f31e923fe2	5450	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
Pawel Zarembski	0:01f31e923fe2	5451	uint8_t RESERVED_23[3];
Pawel Zarembski	0:01f31e923fe2	5452	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
Pawel Zarembski	0:01f31e923fe2	5453	uint8_t RESERVED_24[3];
Pawel Zarembski	0:01f31e923fe2	5454	__IO uint8_t USBTRC0; /*< USB Transceiver Control register 0, offset: 0x10C /
Pawel Zarembski	0:01f31e923fe2	5455	uint8_t RESERVED_25[7];
Pawel Zarembski	0:01f31e923fe2	5456	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
Pawel Zarembski	0:01f31e923fe2	5457	} USB_Type;
Pawel Zarembski	0:01f31e923fe2	5458
Pawel Zarembski	0:01f31e923fe2	5459	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5460	-- USB Register Masks
Pawel Zarembski	0:01f31e923fe2	5461	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5462
Pawel Zarembski	0:01f31e923fe2	5463	/*!
Pawel Zarembski	0:01f31e923fe2	5464	* @addtogroup USB_Register_Masks USB Register Masks
Pawel Zarembski	0:01f31e923fe2	5465	* @{
Pawel Zarembski	0:01f31e923fe2	5466	*/
Pawel Zarembski	0:01f31e923fe2	5467
Pawel Zarembski	0:01f31e923fe2	5468	/! @name PERID - Peripheral ID register /
Pawel Zarembski	0:01f31e923fe2	5469	#define USB_PERID_ID_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	5470	#define USB_PERID_ID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5471	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
Pawel Zarembski	0:01f31e923fe2	5472
Pawel Zarembski	0:01f31e923fe2	5473	/! @name IDCOMP - Peripheral ID Complement register /
Pawel Zarembski	0:01f31e923fe2	5474	#define USB_IDCOMP_NID_MASK (0x3FU)
Pawel Zarembski	0:01f31e923fe2	5475	#define USB_IDCOMP_NID_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5476	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
Pawel Zarembski	0:01f31e923fe2	5477
Pawel Zarembski	0:01f31e923fe2	5478	/! @name REV - Peripheral Revision register /
Pawel Zarembski	0:01f31e923fe2	5479	#define USB_REV_REV_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5480	#define USB_REV_REV_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5481	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
Pawel Zarembski	0:01f31e923fe2	5482
Pawel Zarembski	0:01f31e923fe2	5483	/! @name ADDINFO - Peripheral Additional Info register /
Pawel Zarembski	0:01f31e923fe2	5484	#define USB_ADDINFO_IEHOST_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5485	#define USB_ADDINFO_IEHOST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5486	#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
Pawel Zarembski	0:01f31e923fe2	5487	#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
Pawel Zarembski	0:01f31e923fe2	5488	#define USB_ADDINFO_IRQNUM_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5489	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
Pawel Zarembski	0:01f31e923fe2	5490
Pawel Zarembski	0:01f31e923fe2	5491	/! @name OTGISTAT - OTG Interrupt Status register /
Pawel Zarembski	0:01f31e923fe2	5492	#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5493	#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5494	#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
Pawel Zarembski	0:01f31e923fe2	5495	#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5496	#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5497	#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
Pawel Zarembski	0:01f31e923fe2	5498	#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5499	#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5500	#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
Pawel Zarembski	0:01f31e923fe2	5501	#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5502	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5503	#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
Pawel Zarembski	0:01f31e923fe2	5504	#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5505	#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5506	#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
Pawel Zarembski	0:01f31e923fe2	5507	#define USB_OTGISTAT_IDCHG_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5508	#define USB_OTGISTAT_IDCHG_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5509	#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
Pawel Zarembski	0:01f31e923fe2	5510
Pawel Zarembski	0:01f31e923fe2	5511	/! @name OTGICR - OTG Interrupt Control register /
Pawel Zarembski	0:01f31e923fe2	5512	#define USB_OTGICR_AVBUSEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5513	#define USB_OTGICR_AVBUSEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5514	#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5515	#define USB_OTGICR_BSESSEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5516	#define USB_OTGICR_BSESSEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5517	#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5518	#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5519	#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5520	#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5521	#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5522	#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5523	#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5524	#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5525	#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5526	#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5527	#define USB_OTGICR_IDEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5528	#define USB_OTGICR_IDEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5529	#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5530
Pawel Zarembski	0:01f31e923fe2	5531	/! @name OTGSTAT - OTG Status register /
Pawel Zarembski	0:01f31e923fe2	5532	#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5533	#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5534	#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
Pawel Zarembski	0:01f31e923fe2	5535	#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5536	#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5537	#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
Pawel Zarembski	0:01f31e923fe2	5538	#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5539	#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5540	#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
Pawel Zarembski	0:01f31e923fe2	5541	#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5542	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5543	#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
Pawel Zarembski	0:01f31e923fe2	5544	#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5545	#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5546	#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5547	#define USB_OTGSTAT_ID_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5548	#define USB_OTGSTAT_ID_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5549	#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
Pawel Zarembski	0:01f31e923fe2	5550
Pawel Zarembski	0:01f31e923fe2	5551	/! @name OTGCTL - OTG Control register /
Pawel Zarembski	0:01f31e923fe2	5552	#define USB_OTGCTL_OTGEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5553	#define USB_OTGCTL_OTGEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5554	#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5555	#define USB_OTGCTL_DMLOW_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5556	#define USB_OTGCTL_DMLOW_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5557	#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	5558	#define USB_OTGCTL_DPLOW_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5559	#define USB_OTGCTL_DPLOW_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5560	#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
Pawel Zarembski	0:01f31e923fe2	5561	#define USB_OTGCTL_DPHIGH_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5562	#define USB_OTGCTL_DPHIGH_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5563	#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
Pawel Zarembski	0:01f31e923fe2	5564
Pawel Zarembski	0:01f31e923fe2	5565	/! @name ISTAT - Interrupt Status register /
Pawel Zarembski	0:01f31e923fe2	5566	#define USB_ISTAT_USBRST_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5567	#define USB_ISTAT_USBRST_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5568	#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
Pawel Zarembski	0:01f31e923fe2	5569	#define USB_ISTAT_ERROR_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5570	#define USB_ISTAT_ERROR_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5571	#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
Pawel Zarembski	0:01f31e923fe2	5572	#define USB_ISTAT_SOFTOK_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5573	#define USB_ISTAT_SOFTOK_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5574	#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
Pawel Zarembski	0:01f31e923fe2	5575	#define USB_ISTAT_TOKDNE_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5576	#define USB_ISTAT_TOKDNE_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5577	#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
Pawel Zarembski	0:01f31e923fe2	5578	#define USB_ISTAT_SLEEP_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5579	#define USB_ISTAT_SLEEP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5580	#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
Pawel Zarembski	0:01f31e923fe2	5581	#define USB_ISTAT_RESUME_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5582	#define USB_ISTAT_RESUME_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5583	#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
Pawel Zarembski	0:01f31e923fe2	5584	#define USB_ISTAT_ATTACH_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5585	#define USB_ISTAT_ATTACH_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5586	#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
Pawel Zarembski	0:01f31e923fe2	5587	#define USB_ISTAT_STALL_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5588	#define USB_ISTAT_STALL_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5589	#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
Pawel Zarembski	0:01f31e923fe2	5590
Pawel Zarembski	0:01f31e923fe2	5591	/! @name INTEN - Interrupt Enable register /
Pawel Zarembski	0:01f31e923fe2	5592	#define USB_INTEN_USBRSTEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5593	#define USB_INTEN_USBRSTEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5594	#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5595	#define USB_INTEN_ERROREN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5596	#define USB_INTEN_ERROREN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5597	#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
Pawel Zarembski	0:01f31e923fe2	5598	#define USB_INTEN_SOFTOKEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5599	#define USB_INTEN_SOFTOKEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5600	#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5601	#define USB_INTEN_TOKDNEEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5602	#define USB_INTEN_TOKDNEEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5603	#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5604	#define USB_INTEN_SLEEPEN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5605	#define USB_INTEN_SLEEPEN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5606	#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5607	#define USB_INTEN_RESUMEEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5608	#define USB_INTEN_RESUMEEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5609	#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5610	#define USB_INTEN_ATTACHEN_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5611	#define USB_INTEN_ATTACHEN_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5612	#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5613	#define USB_INTEN_STALLEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5614	#define USB_INTEN_STALLEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5615	#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5616
Pawel Zarembski	0:01f31e923fe2	5617	/! @name ERRSTAT - Error Interrupt Status register /
Pawel Zarembski	0:01f31e923fe2	5618	#define USB_ERRSTAT_PIDERR_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5619	#define USB_ERRSTAT_PIDERR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5620	#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
Pawel Zarembski	0:01f31e923fe2	5621	#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5622	#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5623	#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
Pawel Zarembski	0:01f31e923fe2	5624	#define USB_ERRSTAT_CRC16_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5625	#define USB_ERRSTAT_CRC16_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5626	#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
Pawel Zarembski	0:01f31e923fe2	5627	#define USB_ERRSTAT_DFN8_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5628	#define USB_ERRSTAT_DFN8_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5629	#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
Pawel Zarembski	0:01f31e923fe2	5630	#define USB_ERRSTAT_BTOERR_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5631	#define USB_ERRSTAT_BTOERR_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5632	#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
Pawel Zarembski	0:01f31e923fe2	5633	#define USB_ERRSTAT_DMAERR_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5634	#define USB_ERRSTAT_DMAERR_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5635	#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
Pawel Zarembski	0:01f31e923fe2	5636	#define USB_ERRSTAT_BTSERR_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5637	#define USB_ERRSTAT_BTSERR_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5638	#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
Pawel Zarembski	0:01f31e923fe2	5639
Pawel Zarembski	0:01f31e923fe2	5640	/! @name ERREN - Error Interrupt Enable register /
Pawel Zarembski	0:01f31e923fe2	5641	#define USB_ERREN_PIDERREN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5642	#define USB_ERREN_PIDERREN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5643	#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	5644	#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5645	#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5646	#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5647	#define USB_ERREN_CRC16EN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5648	#define USB_ERREN_CRC16EN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5649	#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
Pawel Zarembski	0:01f31e923fe2	5650	#define USB_ERREN_DFN8EN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5651	#define USB_ERREN_DFN8EN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5652	#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
Pawel Zarembski	0:01f31e923fe2	5653	#define USB_ERREN_BTOERREN_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5654	#define USB_ERREN_BTOERREN_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5655	#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	5656	#define USB_ERREN_DMAERREN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5657	#define USB_ERREN_DMAERREN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5658	#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	5659	#define USB_ERREN_BTSERREN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5660	#define USB_ERREN_BTSERREN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5661	#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
Pawel Zarembski	0:01f31e923fe2	5662
Pawel Zarembski	0:01f31e923fe2	5663	/! @name STAT - Status register /
Pawel Zarembski	0:01f31e923fe2	5664	#define USB_STAT_ODD_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5665	#define USB_STAT_ODD_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5666	#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
Pawel Zarembski	0:01f31e923fe2	5667	#define USB_STAT_TX_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5668	#define USB_STAT_TX_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5669	#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
Pawel Zarembski	0:01f31e923fe2	5670	#define USB_STAT_ENDP_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	5671	#define USB_STAT_ENDP_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5672	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
Pawel Zarembski	0:01f31e923fe2	5673
Pawel Zarembski	0:01f31e923fe2	5674	/! @name CTL - Control register /
Pawel Zarembski	0:01f31e923fe2	5675	#define USB_CTL_USBENSOFEN_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5676	#define USB_CTL_USBENSOFEN_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5677	#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5678	#define USB_CTL_ODDRST_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5679	#define USB_CTL_ODDRST_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5680	#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
Pawel Zarembski	0:01f31e923fe2	5681	#define USB_CTL_RESUME_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5682	#define USB_CTL_RESUME_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5683	#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
Pawel Zarembski	0:01f31e923fe2	5684	#define USB_CTL_HOSTMODEEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5685	#define USB_CTL_HOSTMODEEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5686	#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5687	#define USB_CTL_RESET_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5688	#define USB_CTL_RESET_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5689	#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
Pawel Zarembski	0:01f31e923fe2	5690	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5691	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5692	#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
Pawel Zarembski	0:01f31e923fe2	5693	#define USB_CTL_SE0_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5694	#define USB_CTL_SE0_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5695	#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
Pawel Zarembski	0:01f31e923fe2	5696	#define USB_CTL_JSTATE_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5697	#define USB_CTL_JSTATE_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5698	#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
Pawel Zarembski	0:01f31e923fe2	5699
Pawel Zarembski	0:01f31e923fe2	5700	/! @name ADDR - Address register /
Pawel Zarembski	0:01f31e923fe2	5701	#define USB_ADDR_ADDR_MASK (0x7FU)
Pawel Zarembski	0:01f31e923fe2	5702	#define USB_ADDR_ADDR_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5703	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
Pawel Zarembski	0:01f31e923fe2	5704	#define USB_ADDR_LSEN_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5705	#define USB_ADDR_LSEN_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5706	#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5707
Pawel Zarembski	0:01f31e923fe2	5708	/! @name BDTPAGE1 - BDT Page register 1 /
Pawel Zarembski	0:01f31e923fe2	5709	#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
Pawel Zarembski	0:01f31e923fe2	5710	#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5711	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
Pawel Zarembski	0:01f31e923fe2	5712
Pawel Zarembski	0:01f31e923fe2	5713	/! @name FRMNUML - Frame Number register Low /
Pawel Zarembski	0:01f31e923fe2	5714	#define USB_FRMNUML_FRM_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5715	#define USB_FRMNUML_FRM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5716	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
Pawel Zarembski	0:01f31e923fe2	5717
Pawel Zarembski	0:01f31e923fe2	5718	/! @name FRMNUMH - Frame Number register High /
Pawel Zarembski	0:01f31e923fe2	5719	#define USB_FRMNUMH_FRM_MASK (0x7U)
Pawel Zarembski	0:01f31e923fe2	5720	#define USB_FRMNUMH_FRM_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5721	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
Pawel Zarembski	0:01f31e923fe2	5722
Pawel Zarembski	0:01f31e923fe2	5723	/! @name TOKEN - Token register /
Pawel Zarembski	0:01f31e923fe2	5724	#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
Pawel Zarembski	0:01f31e923fe2	5725	#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5726	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
Pawel Zarembski	0:01f31e923fe2	5727	#define USB_TOKEN_TOKENPID_MASK (0xF0U)
Pawel Zarembski	0:01f31e923fe2	5728	#define USB_TOKEN_TOKENPID_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5729	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
Pawel Zarembski	0:01f31e923fe2	5730
Pawel Zarembski	0:01f31e923fe2	5731	/! @name SOFTHLD - SOF Threshold register /
Pawel Zarembski	0:01f31e923fe2	5732	#define USB_SOFTHLD_CNT_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5733	#define USB_SOFTHLD_CNT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5734	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
Pawel Zarembski	0:01f31e923fe2	5735
Pawel Zarembski	0:01f31e923fe2	5736	/! @name BDTPAGE2 - BDT Page Register 2 /
Pawel Zarembski	0:01f31e923fe2	5737	#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5738	#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5739	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
Pawel Zarembski	0:01f31e923fe2	5740
Pawel Zarembski	0:01f31e923fe2	5741	/! @name BDTPAGE3 - BDT Page Register 3 /
Pawel Zarembski	0:01f31e923fe2	5742	#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5743	#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5744	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
Pawel Zarembski	0:01f31e923fe2	5745
Pawel Zarembski	0:01f31e923fe2	5746	/! @name ENDPT - Endpoint Control register /
Pawel Zarembski	0:01f31e923fe2	5747	#define USB_ENDPT_EPHSHK_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5748	#define USB_ENDPT_EPHSHK_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5749	#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
Pawel Zarembski	0:01f31e923fe2	5750	#define USB_ENDPT_EPSTALL_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5751	#define USB_ENDPT_EPSTALL_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5752	#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
Pawel Zarembski	0:01f31e923fe2	5753	#define USB_ENDPT_EPTXEN_MASK (0x4U)
Pawel Zarembski	0:01f31e923fe2	5754	#define USB_ENDPT_EPTXEN_SHIFT (2U)
Pawel Zarembski	0:01f31e923fe2	5755	#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5756	#define USB_ENDPT_EPRXEN_MASK (0x8U)
Pawel Zarembski	0:01f31e923fe2	5757	#define USB_ENDPT_EPRXEN_SHIFT (3U)
Pawel Zarembski	0:01f31e923fe2	5758	#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5759	#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5760	#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5761	#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	5762	#define USB_ENDPT_RETRYDIS_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5763	#define USB_ENDPT_RETRYDIS_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5764	#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
Pawel Zarembski	0:01f31e923fe2	5765	#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5766	#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5767	#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
Pawel Zarembski	0:01f31e923fe2	5768
Pawel Zarembski	0:01f31e923fe2	5769	/* The count of USB_ENDPT */
Pawel Zarembski	0:01f31e923fe2	5770	#define USB_ENDPT_COUNT (16U)
Pawel Zarembski	0:01f31e923fe2	5771
Pawel Zarembski	0:01f31e923fe2	5772	/! @name USBCTRL - USB Control register /
Pawel Zarembski	0:01f31e923fe2	5773	#define USB_USBCTRL_PDE_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5774	#define USB_USBCTRL_PDE_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5775	#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
Pawel Zarembski	0:01f31e923fe2	5776	#define USB_USBCTRL_SUSP_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5777	#define USB_USBCTRL_SUSP_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5778	#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
Pawel Zarembski	0:01f31e923fe2	5779
Pawel Zarembski	0:01f31e923fe2	5780	/! @name OBSERVE - USB OTG Observe register /
Pawel Zarembski	0:01f31e923fe2	5781	#define USB_OBSERVE_DMPD_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5782	#define USB_OBSERVE_DMPD_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5783	#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
Pawel Zarembski	0:01f31e923fe2	5784	#define USB_OBSERVE_DPPD_MASK (0x40U)
Pawel Zarembski	0:01f31e923fe2	5785	#define USB_OBSERVE_DPPD_SHIFT (6U)
Pawel Zarembski	0:01f31e923fe2	5786	#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
Pawel Zarembski	0:01f31e923fe2	5787	#define USB_OBSERVE_DPPU_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5788	#define USB_OBSERVE_DPPU_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5789	#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
Pawel Zarembski	0:01f31e923fe2	5790
Pawel Zarembski	0:01f31e923fe2	5791	/! @name CONTROL - USB OTG Control register /
Pawel Zarembski	0:01f31e923fe2	5792	#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
Pawel Zarembski	0:01f31e923fe2	5793	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
Pawel Zarembski	0:01f31e923fe2	5794	#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
Pawel Zarembski	0:01f31e923fe2	5795
Pawel Zarembski	0:01f31e923fe2	5796	/! @name USBTRC0 - USB Transceiver Control register 0 /
Pawel Zarembski	0:01f31e923fe2	5797	#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
Pawel Zarembski	0:01f31e923fe2	5798	#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5799	#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
Pawel Zarembski	0:01f31e923fe2	5800	#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
Pawel Zarembski	0:01f31e923fe2	5801	#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
Pawel Zarembski	0:01f31e923fe2	5802	#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
Pawel Zarembski	0:01f31e923fe2	5803	#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
Pawel Zarembski	0:01f31e923fe2	5804	#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
Pawel Zarembski	0:01f31e923fe2	5805	#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
Pawel Zarembski	0:01f31e923fe2	5806	#define USB_USBTRC0_USBRESET_MASK (0x80U)
Pawel Zarembski	0:01f31e923fe2	5807	#define USB_USBTRC0_USBRESET_SHIFT (7U)
Pawel Zarembski	0:01f31e923fe2	5808	#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
Pawel Zarembski	0:01f31e923fe2	5809
Pawel Zarembski	0:01f31e923fe2	5810	/! @name USBFRMADJUST - Frame Adjust Register /
Pawel Zarembski	0:01f31e923fe2	5811	#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
Pawel Zarembski	0:01f31e923fe2	5812	#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
Pawel Zarembski	0:01f31e923fe2	5813	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
Pawel Zarembski	0:01f31e923fe2	5814
Pawel Zarembski	0:01f31e923fe2	5815
Pawel Zarembski	0:01f31e923fe2	5816	/*!
Pawel Zarembski	0:01f31e923fe2	5817	* @}
Pawel Zarembski	0:01f31e923fe2	5818	/ / end of group USB_Register_Masks */
Pawel Zarembski	0:01f31e923fe2	5819
Pawel Zarembski	0:01f31e923fe2	5820
Pawel Zarembski	0:01f31e923fe2	5821	/* USB - Peripheral instance base addresses */
Pawel Zarembski	0:01f31e923fe2	5822	/** Peripheral USB0 base address */
Pawel Zarembski	0:01f31e923fe2	5823	#define USB0_BASE (0x40072000u)
Pawel Zarembski	0:01f31e923fe2	5824	/** Peripheral USB0 base pointer */
Pawel Zarembski	0:01f31e923fe2	5825	#define USB0 ((USB_Type *)USB0_BASE)
Pawel Zarembski	0:01f31e923fe2	5826	/** Array initializer of USB peripheral base addresses */
Pawel Zarembski	0:01f31e923fe2	5827	#define USB_BASE_ADDRS { USB0_BASE }
Pawel Zarembski	0:01f31e923fe2	5828	/** Array initializer of USB peripheral base pointers */
Pawel Zarembski	0:01f31e923fe2	5829	#define USB_BASE_PTRS { USB0 }
Pawel Zarembski	0:01f31e923fe2	5830	/** Interrupt vectors for the USB peripheral type */
Pawel Zarembski	0:01f31e923fe2	5831	#define USB_IRQS { USB0_IRQn }
Pawel Zarembski	0:01f31e923fe2	5832
Pawel Zarembski	0:01f31e923fe2	5833	/*!
Pawel Zarembski	0:01f31e923fe2	5834	* @}
Pawel Zarembski	0:01f31e923fe2	5835	/ / end of group USB_Peripheral_Access_Layer */
Pawel Zarembski	0:01f31e923fe2	5836
Pawel Zarembski	0:01f31e923fe2	5837
Pawel Zarembski	0:01f31e923fe2	5838	/*
Pawel Zarembski	0:01f31e923fe2	5839	** End of section using anonymous unions
Pawel Zarembski	0:01f31e923fe2	5840	*/
Pawel Zarembski	0:01f31e923fe2	5841
Pawel Zarembski	0:01f31e923fe2	5842	#if defined(__ARMCC_VERSION)
Pawel Zarembski	0:01f31e923fe2	5843	#pragma pop
Pawel Zarembski	0:01f31e923fe2	5844	#elif defined(__CWCC__)
Pawel Zarembski	0:01f31e923fe2	5845	#pragma pop
Pawel Zarembski	0:01f31e923fe2	5846	#elif defined(__GNUC__)
Pawel Zarembski	0:01f31e923fe2	5847	/* leave anonymous unions enabled */
Pawel Zarembski	0:01f31e923fe2	5848	#elif defined(__IAR_SYSTEMS_ICC__)
Pawel Zarembski	0:01f31e923fe2	5849	#pragma language=default
Pawel Zarembski	0:01f31e923fe2	5850	#else
Pawel Zarembski	0:01f31e923fe2	5851	#error Not supported compiler type
Pawel Zarembski	0:01f31e923fe2	5852	#endif
Pawel Zarembski	0:01f31e923fe2	5853
Pawel Zarembski	0:01f31e923fe2	5854	/*!
Pawel Zarembski	0:01f31e923fe2	5855	* @}
Pawel Zarembski	0:01f31e923fe2	5856	/ / end of group Peripheral_access_layer */
Pawel Zarembski	0:01f31e923fe2	5857
Pawel Zarembski	0:01f31e923fe2	5858
Pawel Zarembski	0:01f31e923fe2	5859	/* ----------------------------------------------------------------------------
Pawel Zarembski	0:01f31e923fe2	5860	-- SDK Compatibility
Pawel Zarembski	0:01f31e923fe2	5861	---------------------------------------------------------------------------- */
Pawel Zarembski	0:01f31e923fe2	5862
Pawel Zarembski	0:01f31e923fe2	5863	/*!
Pawel Zarembski	0:01f31e923fe2	5864	* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
Pawel Zarembski	0:01f31e923fe2	5865	* @{
Pawel Zarembski	0:01f31e923fe2	5866	*/
Pawel Zarembski	0:01f31e923fe2	5867
Pawel Zarembski	0:01f31e923fe2	5868	#define FPTA_BASE FGPIOA_BASE
Pawel Zarembski	0:01f31e923fe2	5869	#define FPTA FGPIOA
Pawel Zarembski	0:01f31e923fe2	5870	#define FPTB_BASE FGPIOB_BASE
Pawel Zarembski	0:01f31e923fe2	5871	#define FPTB FGPIOB
Pawel Zarembski	0:01f31e923fe2	5872	#define FPTC_BASE FGPIOC_BASE
Pawel Zarembski	0:01f31e923fe2	5873	#define FPTC FGPIOC
Pawel Zarembski	0:01f31e923fe2	5874	#define FPTD_BASE FGPIOD_BASE
Pawel Zarembski	0:01f31e923fe2	5875	#define FPTD FGPIOD
Pawel Zarembski	0:01f31e923fe2	5876	#define FPTE_BASE FGPIOE_BASE
Pawel Zarembski	0:01f31e923fe2	5877	#define FPTE FGPIOE
Pawel Zarembski	0:01f31e923fe2	5878	#define PTA_BASE GPIOA_BASE
Pawel Zarembski	0:01f31e923fe2	5879	#define PTA GPIOA
Pawel Zarembski	0:01f31e923fe2	5880	#define PTB_BASE GPIOB_BASE
Pawel Zarembski	0:01f31e923fe2	5881	#define PTB GPIOB
Pawel Zarembski	0:01f31e923fe2	5882	#define PTC_BASE GPIOC_BASE
Pawel Zarembski	0:01f31e923fe2	5883	#define PTC GPIOC
Pawel Zarembski	0:01f31e923fe2	5884	#define PTD_BASE GPIOD_BASE
Pawel Zarembski	0:01f31e923fe2	5885	#define PTD GPIOD
Pawel Zarembski	0:01f31e923fe2	5886	#define PTE_BASE GPIOE_BASE
Pawel Zarembski	0:01f31e923fe2	5887	#define PTE GPIOE
Pawel Zarembski	0:01f31e923fe2	5888	#define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
Pawel Zarembski	0:01f31e923fe2	5889	#define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
Pawel Zarembski	0:01f31e923fe2	5890	#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
Pawel Zarembski	0:01f31e923fe2	5891	#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
Pawel Zarembski	0:01f31e923fe2	5892	#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
Pawel Zarembski	0:01f31e923fe2	5893	#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
Pawel Zarembski	0:01f31e923fe2	5894	#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
Pawel Zarembski	0:01f31e923fe2	5895	#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
Pawel Zarembski	0:01f31e923fe2	5896	#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
Pawel Zarembski	0:01f31e923fe2	5897	#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
Pawel Zarembski	0:01f31e923fe2	5898	#define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)
Pawel Zarembski	0:01f31e923fe2	5899	#define LPTimer_IRQn LPTMR0_IRQn
Pawel Zarembski	0:01f31e923fe2	5900	#define LPTimer_IRQHandler LPTMR0_IRQHandler
Pawel Zarembski	0:01f31e923fe2	5901	#define LLW_IRQn LLWU_IRQn
Pawel Zarembski	0:01f31e923fe2	5902	#define LLW_IRQHandler LLWU_IRQHandler
Pawel Zarembski	0:01f31e923fe2	5903
Pawel Zarembski	0:01f31e923fe2	5904	/*!
Pawel Zarembski	0:01f31e923fe2	5905	* @}
Pawel Zarembski	0:01f31e923fe2	5906	/ / end of group SDK_Compatibility_Symbols */
Pawel Zarembski	0:01f31e923fe2	5907
Pawel Zarembski	0:01f31e923fe2	5908
Pawel Zarembski	0:01f31e923fe2	5909	#endif /* _MKL26Z4_H_ */
Pawel Zarembski	0:01f31e923fe2	5910

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Type:	Library
Created:	07 Apr 2020
Imports:	6
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	12

source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h@0:01f31e923fe2, 2020-04-07 (annotated)

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