Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k26f/usb_phy.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /*
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
Pawel Zarembski 0:01f31e923fe2 3 * All rights reserved.
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * Redistribution and use in source and binary forms, with or without modification,
Pawel Zarembski 0:01f31e923fe2 6 * are permitted provided that the following conditions are met:
Pawel Zarembski 0:01f31e923fe2 7 *
Pawel Zarembski 0:01f31e923fe2 8 * o Redistributions of source code must retain the above copyright notice, this list
Pawel Zarembski 0:01f31e923fe2 9 * of conditions and the following disclaimer.
Pawel Zarembski 0:01f31e923fe2 10 *
Pawel Zarembski 0:01f31e923fe2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
Pawel Zarembski 0:01f31e923fe2 12 * list of conditions and the following disclaimer in the documentation and/or
Pawel Zarembski 0:01f31e923fe2 13 * other materials provided with the distribution.
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Pawel Zarembski 0:01f31e923fe2 16 * contributors may be used to endorse or promote products derived from this
Pawel Zarembski 0:01f31e923fe2 17 * software without specific prior written permission.
Pawel Zarembski 0:01f31e923fe2 18 *
Pawel Zarembski 0:01f31e923fe2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Pawel Zarembski 0:01f31e923fe2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Pawel Zarembski 0:01f31e923fe2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Pawel Zarembski 0:01f31e923fe2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Pawel Zarembski 0:01f31e923fe2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Pawel Zarembski 0:01f31e923fe2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Pawel Zarembski 0:01f31e923fe2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Pawel Zarembski 0:01f31e923fe2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Pawel Zarembski 0:01f31e923fe2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Pawel Zarembski 0:01f31e923fe2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Pawel Zarembski 0:01f31e923fe2 29 */
Pawel Zarembski 0:01f31e923fe2 30
Pawel Zarembski 0:01f31e923fe2 31 #include "fsl_usb.h"
Pawel Zarembski 0:01f31e923fe2 32 #include "fsl_device_registers.h"
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /*!
Pawel Zarembski 0:01f31e923fe2 35 * @brief ehci phy initialization.
Pawel Zarembski 0:01f31e923fe2 36 *
Pawel Zarembski 0:01f31e923fe2 37 * This function initialize ehci phy IP.
Pawel Zarembski 0:01f31e923fe2 38 *
Pawel Zarembski 0:01f31e923fe2 39 * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
Pawel Zarembski 0:01f31e923fe2 40 * @param[in] freq the external input clock.
Pawel Zarembski 0:01f31e923fe2 41 * for example: if the external input clock is 16M, the parameter freq should be 16000000.
Pawel Zarembski 0:01f31e923fe2 42 *
Pawel Zarembski 0:01f31e923fe2 43 * @retval kStatus_USB_Success cancel successfully.
Pawel Zarembski 0:01f31e923fe2 44 * @retval kStatus_USB_Error the freq value is incorrect.
Pawel Zarembski 0:01f31e923fe2 45 */
Pawel Zarembski 0:01f31e923fe2 46 uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq)
Pawel Zarembski 0:01f31e923fe2 47 {
Pawel Zarembski 0:01f31e923fe2 48 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
Pawel Zarembski 0:01f31e923fe2 49 USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
Pawel Zarembski 0:01f31e923fe2 50 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
Pawel Zarembski 0:01f31e923fe2 51 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
Pawel Zarembski 0:01f31e923fe2 52 if (freq == 24000000U)
Pawel Zarembski 0:01f31e923fe2 53 {
Pawel Zarembski 0:01f31e923fe2 54 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
Pawel Zarembski 0:01f31e923fe2 55 }
Pawel Zarembski 0:01f31e923fe2 56 else if (freq == 16000000U)
Pawel Zarembski 0:01f31e923fe2 57 {
Pawel Zarembski 0:01f31e923fe2 58 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
Pawel Zarembski 0:01f31e923fe2 59 }
Pawel Zarembski 0:01f31e923fe2 60 else if (freq == 12000000U)
Pawel Zarembski 0:01f31e923fe2 61 {
Pawel Zarembski 0:01f31e923fe2 62 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
Pawel Zarembski 0:01f31e923fe2 63 }
Pawel Zarembski 0:01f31e923fe2 64 else
Pawel Zarembski 0:01f31e923fe2 65 {
Pawel Zarembski 0:01f31e923fe2 66 return kStatus_USB_Error; /* error */
Pawel Zarembski 0:01f31e923fe2 67 }
Pawel Zarembski 0:01f31e923fe2 68 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* clear bypass bit */
Pawel Zarembski 0:01f31e923fe2 69 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* enable USB clock output from USB PHY PLL */
Pawel Zarembski 0:01f31e923fe2 70 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
Pawel Zarembski 0:01f31e923fe2 71
Pawel Zarembski 0:01f31e923fe2 72 USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
Pawel Zarembski 0:01f31e923fe2 73 USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
Pawel Zarembski 0:01f31e923fe2 74 /* PWD register provides overall control of the PHY power state */
Pawel Zarembski 0:01f31e923fe2 75 USBPHY->PWD = 0U;
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
Pawel Zarembski 0:01f31e923fe2 78 {
Pawel Zarembski 0:01f31e923fe2 79 }
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
Pawel Zarembski 0:01f31e923fe2 82 USBPHY->TX = ((USBPHY->TX & (~USBPHY_TX_D_CAL_MASK)) | USBPHY_TX_D_CAL(0xcU));
Pawel Zarembski 0:01f31e923fe2 83 #endif
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 return kStatus_USB_Success;
Pawel Zarembski 0:01f31e923fe2 86 }
Pawel Zarembski 0:01f31e923fe2 87
Pawel Zarembski 0:01f31e923fe2 88 /*!
Pawel Zarembski 0:01f31e923fe2 89 * @brief ehci phy initialization for suspend and resume.
Pawel Zarembski 0:01f31e923fe2 90 *
Pawel Zarembski 0:01f31e923fe2 91 * This function initialize ehci phy IP for suspend and resume.
Pawel Zarembski 0:01f31e923fe2 92 *
Pawel Zarembski 0:01f31e923fe2 93 * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
Pawel Zarembski 0:01f31e923fe2 94 * @param[in] freq the external input clock.
Pawel Zarembski 0:01f31e923fe2 95 * for example: if the external input clock is 16M, the parameter freq should be 16000000.
Pawel Zarembski 0:01f31e923fe2 96 *
Pawel Zarembski 0:01f31e923fe2 97 * @retval kStatus_USB_Success cancel successfully.
Pawel Zarembski 0:01f31e923fe2 98 * @retval kStatus_USB_Error the freq value is incorrect.
Pawel Zarembski 0:01f31e923fe2 99 */
Pawel Zarembski 0:01f31e923fe2 100 uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq)
Pawel Zarembski 0:01f31e923fe2 101 {
Pawel Zarembski 0:01f31e923fe2 102 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
Pawel Zarembski 0:01f31e923fe2 103 USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
Pawel Zarembski 0:01f31e923fe2 104 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
Pawel Zarembski 0:01f31e923fe2 105 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
Pawel Zarembski 0:01f31e923fe2 106 if (freq == 24000000U)
Pawel Zarembski 0:01f31e923fe2 107 {
Pawel Zarembski 0:01f31e923fe2 108 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
Pawel Zarembski 0:01f31e923fe2 109 }
Pawel Zarembski 0:01f31e923fe2 110 else if (freq == 16000000U)
Pawel Zarembski 0:01f31e923fe2 111 {
Pawel Zarembski 0:01f31e923fe2 112 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
Pawel Zarembski 0:01f31e923fe2 113 }
Pawel Zarembski 0:01f31e923fe2 114 else if (freq == 12000000U)
Pawel Zarembski 0:01f31e923fe2 115 {
Pawel Zarembski 0:01f31e923fe2 116 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
Pawel Zarembski 0:01f31e923fe2 117 }
Pawel Zarembski 0:01f31e923fe2 118 else
Pawel Zarembski 0:01f31e923fe2 119 {
Pawel Zarembski 0:01f31e923fe2 120 return kStatus_USB_Error; /* error */
Pawel Zarembski 0:01f31e923fe2 121 }
Pawel Zarembski 0:01f31e923fe2 122 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* clear bypass bit */
Pawel Zarembski 0:01f31e923fe2 123 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* enable USB clock output from USB PHY PLL */
Pawel Zarembski 0:01f31e923fe2 124 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
Pawel Zarembski 0:01f31e923fe2 125 USBPHY->CTRL |=
Pawel Zarembski 0:01f31e923fe2 126 USBPHY_CTRL_AUTORESUME_EN_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
Pawel Zarembski 0:01f31e923fe2 127 USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
Pawel Zarembski 0:01f31e923fe2 128 USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
Pawel Zarembski 0:01f31e923fe2 129 /* PWD register provides overall control of the PHY power state */
Pawel Zarembski 0:01f31e923fe2 130 USBPHY->PWD = 0U;
Pawel Zarembski 0:01f31e923fe2 131
Pawel Zarembski 0:01f31e923fe2 132 while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
Pawel Zarembski 0:01f31e923fe2 133 {
Pawel Zarembski 0:01f31e923fe2 134 }
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
Pawel Zarembski 0:01f31e923fe2 137 * pfd clock = 480MHz*18/N, where N=18~35
Pawel Zarembski 0:01f31e923fe2 138 * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
Pawel Zarembski 0:01f31e923fe2 139 */
Pawel Zarembski 0:01f31e923fe2 140 USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */
Pawel Zarembski 0:01f31e923fe2 141 USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(4); /* div by 4 */
Pawel Zarembski 0:01f31e923fe2 142
Pawel Zarembski 0:01f31e923fe2 143 USBPHY->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
Pawel Zarembski 0:01f31e923fe2 144 USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
Pawel Zarembski 0:01f31e923fe2 145 while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
Pawel Zarembski 0:01f31e923fe2 146 {
Pawel Zarembski 0:01f31e923fe2 147 }
Pawel Zarembski 0:01f31e923fe2 148
Pawel Zarembski 0:01f31e923fe2 149 /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
Pawel Zarembski 0:01f31e923fe2 150 USBPHY->TX = ((USBPHY->TX & (~USBPHY_TX_D_CAL_MASK)) | USBPHY_TX_D_CAL(0xcU));
Pawel Zarembski 0:01f31e923fe2 151 #endif
Pawel Zarembski 0:01f31e923fe2 152
Pawel Zarembski 0:01f31e923fe2 153 return kStatus_USB_Success;
Pawel Zarembski 0:01f31e923fe2 154 }
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 /*!
Pawel Zarembski 0:01f31e923fe2 157 * @brief ehci phy de-initialization.
Pawel Zarembski 0:01f31e923fe2 158 *
Pawel Zarembski 0:01f31e923fe2 159 * This function de-initialize ehci phy IP.
Pawel Zarembski 0:01f31e923fe2 160 *
Pawel Zarembski 0:01f31e923fe2 161 * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
Pawel Zarembski 0:01f31e923fe2 162 */
Pawel Zarembski 0:01f31e923fe2 163 void USB_EhciPhyDeinit(uint8_t controllerId)
Pawel Zarembski 0:01f31e923fe2 164 {
Pawel Zarembski 0:01f31e923fe2 165 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
Pawel Zarembski 0:01f31e923fe2 166 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */
Pawel Zarembski 0:01f31e923fe2 167 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
Pawel Zarembski 0:01f31e923fe2 168 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */
Pawel Zarembski 0:01f31e923fe2 169 #endif
Pawel Zarembski 0:01f31e923fe2 170 }
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 /*!
Pawel Zarembski 0:01f31e923fe2 173 * @brief ehci phy disconnect detection enable or disable.
Pawel Zarembski 0:01f31e923fe2 174 *
Pawel Zarembski 0:01f31e923fe2 175 * This function enable/disable host ehci disconnect detection.
Pawel Zarembski 0:01f31e923fe2 176 *
Pawel Zarembski 0:01f31e923fe2 177 * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
Pawel Zarembski 0:01f31e923fe2 178 * @param[in] enable
Pawel Zarembski 0:01f31e923fe2 179 * 1U - enable;
Pawel Zarembski 0:01f31e923fe2 180 * 0U - disable;
Pawel Zarembski 0:01f31e923fe2 181 */
Pawel Zarembski 0:01f31e923fe2 182 void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
Pawel Zarembski 0:01f31e923fe2 183 {
Pawel Zarembski 0:01f31e923fe2 184 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
Pawel Zarembski 0:01f31e923fe2 185 if (enable)
Pawel Zarembski 0:01f31e923fe2 186 {
Pawel Zarembski 0:01f31e923fe2 187 USBPHY->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
Pawel Zarembski 0:01f31e923fe2 188 }
Pawel Zarembski 0:01f31e923fe2 189 else
Pawel Zarembski 0:01f31e923fe2 190 {
Pawel Zarembski 0:01f31e923fe2 191 USBPHY->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
Pawel Zarembski 0:01f31e923fe2 192 }
Pawel Zarembski 0:01f31e923fe2 193 #endif
Pawel Zarembski 0:01f31e923fe2 194 }