Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k26f/fsl_edma.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /*
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
Pawel Zarembski 0:01f31e923fe2 3 * Copyright 2016-2018 NXP
Pawel Zarembski 0:01f31e923fe2 4 * All rights reserved.
Pawel Zarembski 0:01f31e923fe2 5 *
Pawel Zarembski 0:01f31e923fe2 6 * SPDX-License-Identifier: BSD-3-Clause
Pawel Zarembski 0:01f31e923fe2 7 */
Pawel Zarembski 0:01f31e923fe2 8
Pawel Zarembski 0:01f31e923fe2 9 #include "fsl_edma.h"
Pawel Zarembski 0:01f31e923fe2 10 #include "fsl_clock.h"
Pawel Zarembski 0:01f31e923fe2 11
Pawel Zarembski 0:01f31e923fe2 12 /*******************************************************************************
Pawel Zarembski 0:01f31e923fe2 13 * Definitions
Pawel Zarembski 0:01f31e923fe2 14 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 15
Pawel Zarembski 0:01f31e923fe2 16 /* Component ID definition, used by tools. */
Pawel Zarembski 0:01f31e923fe2 17 #ifndef FSL_COMPONENT_ID
Pawel Zarembski 0:01f31e923fe2 18 #define FSL_COMPONENT_ID "platform.drivers.edma"
Pawel Zarembski 0:01f31e923fe2 19 #endif
Pawel Zarembski 0:01f31e923fe2 20
Pawel Zarembski 0:01f31e923fe2 21 #define EDMA_TRANSFER_ENABLED_MASK 0x80U
Pawel Zarembski 0:01f31e923fe2 22
Pawel Zarembski 0:01f31e923fe2 23 /*******************************************************************************
Pawel Zarembski 0:01f31e923fe2 24 * Prototypes
Pawel Zarembski 0:01f31e923fe2 25 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 /*!
Pawel Zarembski 0:01f31e923fe2 28 * @brief Get instance number for EDMA.
Pawel Zarembski 0:01f31e923fe2 29 *
Pawel Zarembski 0:01f31e923fe2 30 * @param base EDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 31 */
Pawel Zarembski 0:01f31e923fe2 32 static uint32_t EDMA_GetInstance(DMA_Type *base);
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 /*******************************************************************************
Pawel Zarembski 0:01f31e923fe2 35 * Variables
Pawel Zarembski 0:01f31e923fe2 36 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 /*! @brief Array to map EDMA instance number to base pointer. */
Pawel Zarembski 0:01f31e923fe2 39 static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
Pawel Zarembski 0:01f31e923fe2 42 /*! @brief Array to map EDMA instance number to clock name. */
Pawel Zarembski 0:01f31e923fe2 43 static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
Pawel Zarembski 0:01f31e923fe2 44 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
Pawel Zarembski 0:01f31e923fe2 45
Pawel Zarembski 0:01f31e923fe2 46 /*! @brief Array to map EDMA instance number to IRQ number. */
Pawel Zarembski 0:01f31e923fe2 47 static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
Pawel Zarembski 0:01f31e923fe2 48
Pawel Zarembski 0:01f31e923fe2 49 /*! @brief Pointers to transfer handle for each EDMA channel. */
Pawel Zarembski 0:01f31e923fe2 50 static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
Pawel Zarembski 0:01f31e923fe2 51
Pawel Zarembski 0:01f31e923fe2 52 /*******************************************************************************
Pawel Zarembski 0:01f31e923fe2 53 * Code
Pawel Zarembski 0:01f31e923fe2 54 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 55
Pawel Zarembski 0:01f31e923fe2 56 static uint32_t EDMA_GetInstance(DMA_Type *base)
Pawel Zarembski 0:01f31e923fe2 57 {
Pawel Zarembski 0:01f31e923fe2 58 uint32_t instance;
Pawel Zarembski 0:01f31e923fe2 59
Pawel Zarembski 0:01f31e923fe2 60 /* Find the instance index from base address mappings. */
Pawel Zarembski 0:01f31e923fe2 61 for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
Pawel Zarembski 0:01f31e923fe2 62 {
Pawel Zarembski 0:01f31e923fe2 63 if (s_edmaBases[instance] == base)
Pawel Zarembski 0:01f31e923fe2 64 {
Pawel Zarembski 0:01f31e923fe2 65 break;
Pawel Zarembski 0:01f31e923fe2 66 }
Pawel Zarembski 0:01f31e923fe2 67 }
Pawel Zarembski 0:01f31e923fe2 68
Pawel Zarembski 0:01f31e923fe2 69 assert(instance < ARRAY_SIZE(s_edmaBases));
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 return instance;
Pawel Zarembski 0:01f31e923fe2 72 }
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 /*!
Pawel Zarembski 0:01f31e923fe2 75 * brief Push content of TCD structure into hardware TCD register.
Pawel Zarembski 0:01f31e923fe2 76 *
Pawel Zarembski 0:01f31e923fe2 77 * param base EDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 78 * param channel EDMA channel number.
Pawel Zarembski 0:01f31e923fe2 79 * param tcd Point to TCD structure.
Pawel Zarembski 0:01f31e923fe2 80 */
Pawel Zarembski 0:01f31e923fe2 81 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
Pawel Zarembski 0:01f31e923fe2 82 {
Pawel Zarembski 0:01f31e923fe2 83 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 84 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 85 assert(((uint32_t)tcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 /* Push tcd into hardware TCD register */
Pawel Zarembski 0:01f31e923fe2 88 base->TCD[channel].SADDR = tcd->SADDR;
Pawel Zarembski 0:01f31e923fe2 89 base->TCD[channel].SOFF = tcd->SOFF;
Pawel Zarembski 0:01f31e923fe2 90 base->TCD[channel].ATTR = tcd->ATTR;
Pawel Zarembski 0:01f31e923fe2 91 base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
Pawel Zarembski 0:01f31e923fe2 92 base->TCD[channel].SLAST = tcd->SLAST;
Pawel Zarembski 0:01f31e923fe2 93 base->TCD[channel].DADDR = tcd->DADDR;
Pawel Zarembski 0:01f31e923fe2 94 base->TCD[channel].DOFF = tcd->DOFF;
Pawel Zarembski 0:01f31e923fe2 95 base->TCD[channel].CITER_ELINKNO = tcd->CITER;
Pawel Zarembski 0:01f31e923fe2 96 base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
Pawel Zarembski 0:01f31e923fe2 97 /* Clear DONE bit first, otherwise ESG cannot be set */
Pawel Zarembski 0:01f31e923fe2 98 base->TCD[channel].CSR = 0;
Pawel Zarembski 0:01f31e923fe2 99 base->TCD[channel].CSR = tcd->CSR;
Pawel Zarembski 0:01f31e923fe2 100 base->TCD[channel].BITER_ELINKNO = tcd->BITER;
Pawel Zarembski 0:01f31e923fe2 101 }
Pawel Zarembski 0:01f31e923fe2 102
Pawel Zarembski 0:01f31e923fe2 103 /*!
Pawel Zarembski 0:01f31e923fe2 104 * brief Initializes the eDMA peripheral.
Pawel Zarembski 0:01f31e923fe2 105 *
Pawel Zarembski 0:01f31e923fe2 106 * This function ungates the eDMA clock and configures the eDMA peripheral according
Pawel Zarembski 0:01f31e923fe2 107 * to the configuration structure.
Pawel Zarembski 0:01f31e923fe2 108 *
Pawel Zarembski 0:01f31e923fe2 109 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 110 * param config A pointer to the configuration structure, see "edma_config_t".
Pawel Zarembski 0:01f31e923fe2 111 * note This function enables the minor loop map feature.
Pawel Zarembski 0:01f31e923fe2 112 */
Pawel Zarembski 0:01f31e923fe2 113 void EDMA_Init(DMA_Type *base, const edma_config_t *config)
Pawel Zarembski 0:01f31e923fe2 114 {
Pawel Zarembski 0:01f31e923fe2 115 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 116
Pawel Zarembski 0:01f31e923fe2 117 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 118
Pawel Zarembski 0:01f31e923fe2 119 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
Pawel Zarembski 0:01f31e923fe2 120 /* Ungate EDMA peripheral clock */
Pawel Zarembski 0:01f31e923fe2 121 CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
Pawel Zarembski 0:01f31e923fe2 122 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 /* clear all the enabled request, status to make sure EDMA status is in normal condition */
Pawel Zarembski 0:01f31e923fe2 125 base->ERQ = 0U;
Pawel Zarembski 0:01f31e923fe2 126 base->INT = 0xFFFFFFFFU;
Pawel Zarembski 0:01f31e923fe2 127 base->ERR = 0xFFFFFFFFU;
Pawel Zarembski 0:01f31e923fe2 128 /* Configure EDMA peripheral according to the configuration structure. */
Pawel Zarembski 0:01f31e923fe2 129 tmpreg = base->CR;
Pawel Zarembski 0:01f31e923fe2 130 tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
Pawel Zarembski 0:01f31e923fe2 131 tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
Pawel Zarembski 0:01f31e923fe2 132 DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
Pawel Zarembski 0:01f31e923fe2 133 base->CR = tmpreg;
Pawel Zarembski 0:01f31e923fe2 134 }
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 /*!
Pawel Zarembski 0:01f31e923fe2 137 * brief Deinitializes the eDMA peripheral.
Pawel Zarembski 0:01f31e923fe2 138 *
Pawel Zarembski 0:01f31e923fe2 139 * This function gates the eDMA clock.
Pawel Zarembski 0:01f31e923fe2 140 *
Pawel Zarembski 0:01f31e923fe2 141 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 142 */
Pawel Zarembski 0:01f31e923fe2 143 void EDMA_Deinit(DMA_Type *base)
Pawel Zarembski 0:01f31e923fe2 144 {
Pawel Zarembski 0:01f31e923fe2 145 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
Pawel Zarembski 0:01f31e923fe2 146 /* Gate EDMA peripheral clock */
Pawel Zarembski 0:01f31e923fe2 147 CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
Pawel Zarembski 0:01f31e923fe2 148 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
Pawel Zarembski 0:01f31e923fe2 149 }
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 /*!
Pawel Zarembski 0:01f31e923fe2 152 * brief Gets the eDMA default configuration structure.
Pawel Zarembski 0:01f31e923fe2 153 *
Pawel Zarembski 0:01f31e923fe2 154 * This function sets the configuration structure to default values.
Pawel Zarembski 0:01f31e923fe2 155 * The default configuration is set to the following values.
Pawel Zarembski 0:01f31e923fe2 156 * code
Pawel Zarembski 0:01f31e923fe2 157 * config.enableContinuousLinkMode = false;
Pawel Zarembski 0:01f31e923fe2 158 * config.enableHaltOnError = true;
Pawel Zarembski 0:01f31e923fe2 159 * config.enableRoundRobinArbitration = false;
Pawel Zarembski 0:01f31e923fe2 160 * config.enableDebugMode = false;
Pawel Zarembski 0:01f31e923fe2 161 * endcode
Pawel Zarembski 0:01f31e923fe2 162 *
Pawel Zarembski 0:01f31e923fe2 163 * param config A pointer to the eDMA configuration structure.
Pawel Zarembski 0:01f31e923fe2 164 */
Pawel Zarembski 0:01f31e923fe2 165 void EDMA_GetDefaultConfig(edma_config_t *config)
Pawel Zarembski 0:01f31e923fe2 166 {
Pawel Zarembski 0:01f31e923fe2 167 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 /* Initializes the configure structure to zero. */
Pawel Zarembski 0:01f31e923fe2 170 memset(config, 0, sizeof(*config));
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 config->enableRoundRobinArbitration = false;
Pawel Zarembski 0:01f31e923fe2 173 config->enableHaltOnError = true;
Pawel Zarembski 0:01f31e923fe2 174 config->enableContinuousLinkMode = false;
Pawel Zarembski 0:01f31e923fe2 175 config->enableDebugMode = false;
Pawel Zarembski 0:01f31e923fe2 176 }
Pawel Zarembski 0:01f31e923fe2 177
Pawel Zarembski 0:01f31e923fe2 178 /*!
Pawel Zarembski 0:01f31e923fe2 179 * brief Sets all TCD registers to default values.
Pawel Zarembski 0:01f31e923fe2 180 *
Pawel Zarembski 0:01f31e923fe2 181 * This function sets TCD registers for this channel to default values.
Pawel Zarembski 0:01f31e923fe2 182 *
Pawel Zarembski 0:01f31e923fe2 183 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 184 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 185 * note This function must not be called while the channel transfer is ongoing
Pawel Zarembski 0:01f31e923fe2 186 * or it causes unpredictable results.
Pawel Zarembski 0:01f31e923fe2 187 * note This function enables the auto stop request feature.
Pawel Zarembski 0:01f31e923fe2 188 */
Pawel Zarembski 0:01f31e923fe2 189 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
Pawel Zarembski 0:01f31e923fe2 190 {
Pawel Zarembski 0:01f31e923fe2 191 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 192
Pawel Zarembski 0:01f31e923fe2 193 EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
Pawel Zarembski 0:01f31e923fe2 194 }
Pawel Zarembski 0:01f31e923fe2 195
Pawel Zarembski 0:01f31e923fe2 196 /*!
Pawel Zarembski 0:01f31e923fe2 197 * brief Configures the eDMA transfer attribute.
Pawel Zarembski 0:01f31e923fe2 198 *
Pawel Zarembski 0:01f31e923fe2 199 * This function configures the transfer attribute, including source address, destination address,
Pawel Zarembski 0:01f31e923fe2 200 * transfer size, address offset, and so on. It also configures the scatter gather feature if the
Pawel Zarembski 0:01f31e923fe2 201 * user supplies the TCD address.
Pawel Zarembski 0:01f31e923fe2 202 * Example:
Pawel Zarembski 0:01f31e923fe2 203 * code
Pawel Zarembski 0:01f31e923fe2 204 * edma_transfer_t config;
Pawel Zarembski 0:01f31e923fe2 205 * edma_tcd_t tcd;
Pawel Zarembski 0:01f31e923fe2 206 * config.srcAddr = ..;
Pawel Zarembski 0:01f31e923fe2 207 * config.destAddr = ..;
Pawel Zarembski 0:01f31e923fe2 208 * ...
Pawel Zarembski 0:01f31e923fe2 209 * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
Pawel Zarembski 0:01f31e923fe2 210 * endcode
Pawel Zarembski 0:01f31e923fe2 211 *
Pawel Zarembski 0:01f31e923fe2 212 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 213 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 214 * param config Pointer to eDMA transfer configuration structure.
Pawel Zarembski 0:01f31e923fe2 215 * param nextTcd Point to TCD structure. It can be NULL if users
Pawel Zarembski 0:01f31e923fe2 216 * do not want to enable scatter/gather feature.
Pawel Zarembski 0:01f31e923fe2 217 * note If nextTcd is not NULL, it means scatter gather feature is enabled
Pawel Zarembski 0:01f31e923fe2 218 * and DREQ bit is cleared in the previous transfer configuration, which
Pawel Zarembski 0:01f31e923fe2 219 * is set in the eDMA_ResetChannel.
Pawel Zarembski 0:01f31e923fe2 220 */
Pawel Zarembski 0:01f31e923fe2 221 void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Pawel Zarembski 0:01f31e923fe2 222 {
Pawel Zarembski 0:01f31e923fe2 223 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 224 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 225 assert(((uint32_t)nextTcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 226
Pawel Zarembski 0:01f31e923fe2 227 EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
Pawel Zarembski 0:01f31e923fe2 228 }
Pawel Zarembski 0:01f31e923fe2 229
Pawel Zarembski 0:01f31e923fe2 230 /*!
Pawel Zarembski 0:01f31e923fe2 231 * brief Configures the eDMA minor offset feature.
Pawel Zarembski 0:01f31e923fe2 232 *
Pawel Zarembski 0:01f31e923fe2 233 * The minor offset means that the signed-extended value is added to the source address or destination
Pawel Zarembski 0:01f31e923fe2 234 * address after each minor loop.
Pawel Zarembski 0:01f31e923fe2 235 *
Pawel Zarembski 0:01f31e923fe2 236 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 237 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 238 * param config A pointer to the minor offset configuration structure.
Pawel Zarembski 0:01f31e923fe2 239 */
Pawel Zarembski 0:01f31e923fe2 240 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
Pawel Zarembski 0:01f31e923fe2 241 {
Pawel Zarembski 0:01f31e923fe2 242 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 243 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 244
Pawel Zarembski 0:01f31e923fe2 245 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 246
Pawel Zarembski 0:01f31e923fe2 247 tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
Pawel Zarembski 0:01f31e923fe2 248 tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
Pawel Zarembski 0:01f31e923fe2 249 tmpreg |=
Pawel Zarembski 0:01f31e923fe2 250 (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
Pawel Zarembski 0:01f31e923fe2 251 DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
Pawel Zarembski 0:01f31e923fe2 252 base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
Pawel Zarembski 0:01f31e923fe2 253 }
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255 /*!
Pawel Zarembski 0:01f31e923fe2 256 * brief Sets the channel link for the eDMA transfer.
Pawel Zarembski 0:01f31e923fe2 257 *
Pawel Zarembski 0:01f31e923fe2 258 * This function configures either the minor link or the major link mode. The minor link means that the channel link is
Pawel Zarembski 0:01f31e923fe2 259 * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
Pawel Zarembski 0:01f31e923fe2 260 * exhausted.
Pawel Zarembski 0:01f31e923fe2 261 *
Pawel Zarembski 0:01f31e923fe2 262 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 263 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 264 * param type A channel link type, which can be one of the following:
Pawel Zarembski 0:01f31e923fe2 265 * arg kEDMA_LinkNone
Pawel Zarembski 0:01f31e923fe2 266 * arg kEDMA_MinorLink
Pawel Zarembski 0:01f31e923fe2 267 * arg kEDMA_MajorLink
Pawel Zarembski 0:01f31e923fe2 268 * param linkedChannel The linked channel number.
Pawel Zarembski 0:01f31e923fe2 269 * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
Pawel Zarembski 0:01f31e923fe2 270 */
Pawel Zarembski 0:01f31e923fe2 271 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
Pawel Zarembski 0:01f31e923fe2 272 {
Pawel Zarembski 0:01f31e923fe2 273 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 274 assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 275
Pawel Zarembski 0:01f31e923fe2 276 EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
Pawel Zarembski 0:01f31e923fe2 277 }
Pawel Zarembski 0:01f31e923fe2 278
Pawel Zarembski 0:01f31e923fe2 279 /*!
Pawel Zarembski 0:01f31e923fe2 280 * brief Sets the bandwidth for the eDMA transfer.
Pawel Zarembski 0:01f31e923fe2 281 *
Pawel Zarembski 0:01f31e923fe2 282 * Because the eDMA processes the minor loop, it continuously generates read/write sequences
Pawel Zarembski 0:01f31e923fe2 283 * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
Pawel Zarembski 0:01f31e923fe2 284 * each read/write access to control the bus request bandwidth seen by the crossbar switch.
Pawel Zarembski 0:01f31e923fe2 285 *
Pawel Zarembski 0:01f31e923fe2 286 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 287 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 288 * param bandWidth A bandwidth setting, which can be one of the following:
Pawel Zarembski 0:01f31e923fe2 289 * arg kEDMABandwidthStallNone
Pawel Zarembski 0:01f31e923fe2 290 * arg kEDMABandwidthStall4Cycle
Pawel Zarembski 0:01f31e923fe2 291 * arg kEDMABandwidthStall8Cycle
Pawel Zarembski 0:01f31e923fe2 292 */
Pawel Zarembski 0:01f31e923fe2 293 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
Pawel Zarembski 0:01f31e923fe2 294 {
Pawel Zarembski 0:01f31e923fe2 295 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 296
Pawel Zarembski 0:01f31e923fe2 297 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
Pawel Zarembski 0:01f31e923fe2 298 }
Pawel Zarembski 0:01f31e923fe2 299
Pawel Zarembski 0:01f31e923fe2 300 /*!
Pawel Zarembski 0:01f31e923fe2 301 * brief Sets the source modulo and the destination modulo for the eDMA transfer.
Pawel Zarembski 0:01f31e923fe2 302 *
Pawel Zarembski 0:01f31e923fe2 303 * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
Pawel Zarembski 0:01f31e923fe2 304 * calculation is performed or the original register value. It provides the ability to implement a circular data
Pawel Zarembski 0:01f31e923fe2 305 * queue easily.
Pawel Zarembski 0:01f31e923fe2 306 *
Pawel Zarembski 0:01f31e923fe2 307 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 308 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 309 * param srcModulo A source modulo value.
Pawel Zarembski 0:01f31e923fe2 310 * param destModulo A destination modulo value.
Pawel Zarembski 0:01f31e923fe2 311 */
Pawel Zarembski 0:01f31e923fe2 312 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
Pawel Zarembski 0:01f31e923fe2 313 {
Pawel Zarembski 0:01f31e923fe2 314 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 315
Pawel Zarembski 0:01f31e923fe2 316 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 317
Pawel Zarembski 0:01f31e923fe2 318 tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
Pawel Zarembski 0:01f31e923fe2 319 base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
Pawel Zarembski 0:01f31e923fe2 320 }
Pawel Zarembski 0:01f31e923fe2 321
Pawel Zarembski 0:01f31e923fe2 322 /*!
Pawel Zarembski 0:01f31e923fe2 323 * brief Enables the interrupt source for the eDMA transfer.
Pawel Zarembski 0:01f31e923fe2 324 *
Pawel Zarembski 0:01f31e923fe2 325 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 326 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 327 * param mask The mask of interrupt source to be set. Users need to use
Pawel Zarembski 0:01f31e923fe2 328 * the defined edma_interrupt_enable_t type.
Pawel Zarembski 0:01f31e923fe2 329 */
Pawel Zarembski 0:01f31e923fe2 330 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
Pawel Zarembski 0:01f31e923fe2 331 {
Pawel Zarembski 0:01f31e923fe2 332 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 333
Pawel Zarembski 0:01f31e923fe2 334 /* Enable error interrupt */
Pawel Zarembski 0:01f31e923fe2 335 if (mask & kEDMA_ErrorInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 336 {
Pawel Zarembski 0:01f31e923fe2 337 base->EEI |= (0x1U << channel);
Pawel Zarembski 0:01f31e923fe2 338 }
Pawel Zarembski 0:01f31e923fe2 339
Pawel Zarembski 0:01f31e923fe2 340 /* Enable Major interrupt */
Pawel Zarembski 0:01f31e923fe2 341 if (mask & kEDMA_MajorInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 342 {
Pawel Zarembski 0:01f31e923fe2 343 base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
Pawel Zarembski 0:01f31e923fe2 344 }
Pawel Zarembski 0:01f31e923fe2 345
Pawel Zarembski 0:01f31e923fe2 346 /* Enable Half major interrupt */
Pawel Zarembski 0:01f31e923fe2 347 if (mask & kEDMA_HalfInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 348 {
Pawel Zarembski 0:01f31e923fe2 349 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
Pawel Zarembski 0:01f31e923fe2 350 }
Pawel Zarembski 0:01f31e923fe2 351 }
Pawel Zarembski 0:01f31e923fe2 352
Pawel Zarembski 0:01f31e923fe2 353 /*!
Pawel Zarembski 0:01f31e923fe2 354 * brief Disables the interrupt source for the eDMA transfer.
Pawel Zarembski 0:01f31e923fe2 355 *
Pawel Zarembski 0:01f31e923fe2 356 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 357 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 358 * param mask The mask of the interrupt source to be set. Use
Pawel Zarembski 0:01f31e923fe2 359 * the defined edma_interrupt_enable_t type.
Pawel Zarembski 0:01f31e923fe2 360 */
Pawel Zarembski 0:01f31e923fe2 361 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
Pawel Zarembski 0:01f31e923fe2 362 {
Pawel Zarembski 0:01f31e923fe2 363 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 364
Pawel Zarembski 0:01f31e923fe2 365 /* Disable error interrupt */
Pawel Zarembski 0:01f31e923fe2 366 if (mask & kEDMA_ErrorInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 367 {
Pawel Zarembski 0:01f31e923fe2 368 base->EEI &= ~(0x1U << channel);
Pawel Zarembski 0:01f31e923fe2 369 }
Pawel Zarembski 0:01f31e923fe2 370
Pawel Zarembski 0:01f31e923fe2 371 /* Disable Major interrupt */
Pawel Zarembski 0:01f31e923fe2 372 if (mask & kEDMA_MajorInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 373 {
Pawel Zarembski 0:01f31e923fe2 374 base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
Pawel Zarembski 0:01f31e923fe2 375 }
Pawel Zarembski 0:01f31e923fe2 376
Pawel Zarembski 0:01f31e923fe2 377 /* Disable Half major interrupt */
Pawel Zarembski 0:01f31e923fe2 378 if (mask & kEDMA_HalfInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 379 {
Pawel Zarembski 0:01f31e923fe2 380 base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
Pawel Zarembski 0:01f31e923fe2 381 }
Pawel Zarembski 0:01f31e923fe2 382 }
Pawel Zarembski 0:01f31e923fe2 383
Pawel Zarembski 0:01f31e923fe2 384 /*!
Pawel Zarembski 0:01f31e923fe2 385 * brief Sets all fields to default values for the TCD structure.
Pawel Zarembski 0:01f31e923fe2 386 *
Pawel Zarembski 0:01f31e923fe2 387 * This function sets all fields for this TCD structure to default value.
Pawel Zarembski 0:01f31e923fe2 388 *
Pawel Zarembski 0:01f31e923fe2 389 * param tcd Pointer to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 390 * note This function enables the auto stop request feature.
Pawel Zarembski 0:01f31e923fe2 391 */
Pawel Zarembski 0:01f31e923fe2 392 void EDMA_TcdReset(edma_tcd_t *tcd)
Pawel Zarembski 0:01f31e923fe2 393 {
Pawel Zarembski 0:01f31e923fe2 394 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 395 assert(((uint32_t)tcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 396
Pawel Zarembski 0:01f31e923fe2 397 /* Reset channel TCD */
Pawel Zarembski 0:01f31e923fe2 398 tcd->SADDR = 0U;
Pawel Zarembski 0:01f31e923fe2 399 tcd->SOFF = 0U;
Pawel Zarembski 0:01f31e923fe2 400 tcd->ATTR = 0U;
Pawel Zarembski 0:01f31e923fe2 401 tcd->NBYTES = 0U;
Pawel Zarembski 0:01f31e923fe2 402 tcd->SLAST = 0U;
Pawel Zarembski 0:01f31e923fe2 403 tcd->DADDR = 0U;
Pawel Zarembski 0:01f31e923fe2 404 tcd->DOFF = 0U;
Pawel Zarembski 0:01f31e923fe2 405 tcd->CITER = 0U;
Pawel Zarembski 0:01f31e923fe2 406 tcd->DLAST_SGA = 0U;
Pawel Zarembski 0:01f31e923fe2 407 /* Enable auto disable request feature */
Pawel Zarembski 0:01f31e923fe2 408 tcd->CSR = DMA_CSR_DREQ(true);
Pawel Zarembski 0:01f31e923fe2 409 tcd->BITER = 0U;
Pawel Zarembski 0:01f31e923fe2 410 }
Pawel Zarembski 0:01f31e923fe2 411
Pawel Zarembski 0:01f31e923fe2 412 /*!
Pawel Zarembski 0:01f31e923fe2 413 * brief Configures the eDMA TCD transfer attribute.
Pawel Zarembski 0:01f31e923fe2 414 *
Pawel Zarembski 0:01f31e923fe2 415 * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
Pawel Zarembski 0:01f31e923fe2 416 * The STCD is used in the scatter-gather mode.
Pawel Zarembski 0:01f31e923fe2 417 * This function configures the TCD transfer attribute, including source address, destination address,
Pawel Zarembski 0:01f31e923fe2 418 * transfer size, address offset, and so on. It also configures the scatter gather feature if the
Pawel Zarembski 0:01f31e923fe2 419 * user supplies the next TCD address.
Pawel Zarembski 0:01f31e923fe2 420 * Example:
Pawel Zarembski 0:01f31e923fe2 421 * code
Pawel Zarembski 0:01f31e923fe2 422 * edma_transfer_t config = {
Pawel Zarembski 0:01f31e923fe2 423 * ...
Pawel Zarembski 0:01f31e923fe2 424 * }
Pawel Zarembski 0:01f31e923fe2 425 * edma_tcd_t tcd __aligned(32);
Pawel Zarembski 0:01f31e923fe2 426 * edma_tcd_t nextTcd __aligned(32);
Pawel Zarembski 0:01f31e923fe2 427 * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
Pawel Zarembski 0:01f31e923fe2 428 * endcode
Pawel Zarembski 0:01f31e923fe2 429 *
Pawel Zarembski 0:01f31e923fe2 430 * param tcd Pointer to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 431 * param config Pointer to eDMA transfer configuration structure.
Pawel Zarembski 0:01f31e923fe2 432 * param nextTcd Pointer to the next TCD structure. It can be NULL if users
Pawel Zarembski 0:01f31e923fe2 433 * do not want to enable scatter/gather feature.
Pawel Zarembski 0:01f31e923fe2 434 * note TCD address should be 32 bytes aligned or it causes an eDMA error.
Pawel Zarembski 0:01f31e923fe2 435 * note If the nextTcd is not NULL, the scatter gather feature is enabled
Pawel Zarembski 0:01f31e923fe2 436 * and DREQ bit is cleared in the previous transfer configuration, which
Pawel Zarembski 0:01f31e923fe2 437 * is set in the EDMA_TcdReset.
Pawel Zarembski 0:01f31e923fe2 438 */
Pawel Zarembski 0:01f31e923fe2 439 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Pawel Zarembski 0:01f31e923fe2 440 {
Pawel Zarembski 0:01f31e923fe2 441 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 442 assert(((uint32_t)tcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 443 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 444 assert(((uint32_t)nextTcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 445
Pawel Zarembski 0:01f31e923fe2 446 /* source address */
Pawel Zarembski 0:01f31e923fe2 447 tcd->SADDR = config->srcAddr;
Pawel Zarembski 0:01f31e923fe2 448 /* destination address */
Pawel Zarembski 0:01f31e923fe2 449 tcd->DADDR = config->destAddr;
Pawel Zarembski 0:01f31e923fe2 450 /* Source data and destination data transfer size */
Pawel Zarembski 0:01f31e923fe2 451 tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
Pawel Zarembski 0:01f31e923fe2 452 /* Source address signed offset */
Pawel Zarembski 0:01f31e923fe2 453 tcd->SOFF = config->srcOffset;
Pawel Zarembski 0:01f31e923fe2 454 /* Destination address signed offset */
Pawel Zarembski 0:01f31e923fe2 455 tcd->DOFF = config->destOffset;
Pawel Zarembski 0:01f31e923fe2 456 /* Minor byte transfer count */
Pawel Zarembski 0:01f31e923fe2 457 tcd->NBYTES = config->minorLoopBytes;
Pawel Zarembski 0:01f31e923fe2 458 /* Current major iteration count */
Pawel Zarembski 0:01f31e923fe2 459 tcd->CITER = config->majorLoopCounts;
Pawel Zarembski 0:01f31e923fe2 460 /* Starting major iteration count */
Pawel Zarembski 0:01f31e923fe2 461 tcd->BITER = config->majorLoopCounts;
Pawel Zarembski 0:01f31e923fe2 462 /* Enable scatter/gather processing */
Pawel Zarembski 0:01f31e923fe2 463 if (nextTcd != NULL)
Pawel Zarembski 0:01f31e923fe2 464 {
Pawel Zarembski 0:01f31e923fe2 465 tcd->DLAST_SGA = (uint32_t)nextTcd;
Pawel Zarembski 0:01f31e923fe2 466 /*
Pawel Zarembski 0:01f31e923fe2 467 Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
Pawel Zarembski 0:01f31e923fe2 468 user must call EDMA_TcdReset or EDMA_ResetChannel which will set
Pawel Zarembski 0:01f31e923fe2 469 DREQ, so must use "|" or "&" rather than "=".
Pawel Zarembski 0:01f31e923fe2 470
Pawel Zarembski 0:01f31e923fe2 471 Clear the DREQ bit because scatter gather has been enabled, so the
Pawel Zarembski 0:01f31e923fe2 472 previous transfer is not the last transfer, and channel request should
Pawel Zarembski 0:01f31e923fe2 473 be enabled at the next transfer(the next TCD).
Pawel Zarembski 0:01f31e923fe2 474 */
Pawel Zarembski 0:01f31e923fe2 475 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
Pawel Zarembski 0:01f31e923fe2 476 }
Pawel Zarembski 0:01f31e923fe2 477 }
Pawel Zarembski 0:01f31e923fe2 478
Pawel Zarembski 0:01f31e923fe2 479 /*!
Pawel Zarembski 0:01f31e923fe2 480 * brief Configures the eDMA TCD minor offset feature.
Pawel Zarembski 0:01f31e923fe2 481 *
Pawel Zarembski 0:01f31e923fe2 482 * A minor offset is a signed-extended value added to the source address or a destination
Pawel Zarembski 0:01f31e923fe2 483 * address after each minor loop.
Pawel Zarembski 0:01f31e923fe2 484 *
Pawel Zarembski 0:01f31e923fe2 485 * param tcd A point to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 486 * param config A pointer to the minor offset configuration structure.
Pawel Zarembski 0:01f31e923fe2 487 */
Pawel Zarembski 0:01f31e923fe2 488 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
Pawel Zarembski 0:01f31e923fe2 489 {
Pawel Zarembski 0:01f31e923fe2 490 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 491 assert(((uint32_t)tcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 492
Pawel Zarembski 0:01f31e923fe2 493 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 494
Pawel Zarembski 0:01f31e923fe2 495 tmpreg = tcd->NBYTES &
Pawel Zarembski 0:01f31e923fe2 496 ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
Pawel Zarembski 0:01f31e923fe2 497 tmpreg |=
Pawel Zarembski 0:01f31e923fe2 498 (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
Pawel Zarembski 0:01f31e923fe2 499 DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
Pawel Zarembski 0:01f31e923fe2 500 tcd->NBYTES = tmpreg;
Pawel Zarembski 0:01f31e923fe2 501 }
Pawel Zarembski 0:01f31e923fe2 502
Pawel Zarembski 0:01f31e923fe2 503 /*!
Pawel Zarembski 0:01f31e923fe2 504 * brief Sets the channel link for the eDMA TCD.
Pawel Zarembski 0:01f31e923fe2 505 *
Pawel Zarembski 0:01f31e923fe2 506 * This function configures either a minor link or a major link. The minor link means the channel link is
Pawel Zarembski 0:01f31e923fe2 507 * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
Pawel Zarembski 0:01f31e923fe2 508 * exhausted.
Pawel Zarembski 0:01f31e923fe2 509 *
Pawel Zarembski 0:01f31e923fe2 510 * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
Pawel Zarembski 0:01f31e923fe2 511 * param tcd Point to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 512 * param type Channel link type, it can be one of:
Pawel Zarembski 0:01f31e923fe2 513 * arg kEDMA_LinkNone
Pawel Zarembski 0:01f31e923fe2 514 * arg kEDMA_MinorLink
Pawel Zarembski 0:01f31e923fe2 515 * arg kEDMA_MajorLink
Pawel Zarembski 0:01f31e923fe2 516 * param linkedChannel The linked channel number.
Pawel Zarembski 0:01f31e923fe2 517 */
Pawel Zarembski 0:01f31e923fe2 518 void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
Pawel Zarembski 0:01f31e923fe2 519 {
Pawel Zarembski 0:01f31e923fe2 520 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 521 assert(((uint32_t)tcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 522 assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 523
Pawel Zarembski 0:01f31e923fe2 524 if (type == kEDMA_MinorLink) /* Minor link config */
Pawel Zarembski 0:01f31e923fe2 525 {
Pawel Zarembski 0:01f31e923fe2 526 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 527
Pawel Zarembski 0:01f31e923fe2 528 /* Enable minor link */
Pawel Zarembski 0:01f31e923fe2 529 tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
Pawel Zarembski 0:01f31e923fe2 530 tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
Pawel Zarembski 0:01f31e923fe2 531 /* Set linked channel */
Pawel Zarembski 0:01f31e923fe2 532 tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
Pawel Zarembski 0:01f31e923fe2 533 tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
Pawel Zarembski 0:01f31e923fe2 534 tcd->CITER = tmpreg;
Pawel Zarembski 0:01f31e923fe2 535 tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
Pawel Zarembski 0:01f31e923fe2 536 tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
Pawel Zarembski 0:01f31e923fe2 537 tcd->BITER = tmpreg;
Pawel Zarembski 0:01f31e923fe2 538 }
Pawel Zarembski 0:01f31e923fe2 539 else if (type == kEDMA_MajorLink) /* Major link config */
Pawel Zarembski 0:01f31e923fe2 540 {
Pawel Zarembski 0:01f31e923fe2 541 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 542
Pawel Zarembski 0:01f31e923fe2 543 /* Enable major link */
Pawel Zarembski 0:01f31e923fe2 544 tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
Pawel Zarembski 0:01f31e923fe2 545 /* Set major linked channel */
Pawel Zarembski 0:01f31e923fe2 546 tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
Pawel Zarembski 0:01f31e923fe2 547 tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
Pawel Zarembski 0:01f31e923fe2 548 }
Pawel Zarembski 0:01f31e923fe2 549 else /* Link none */
Pawel Zarembski 0:01f31e923fe2 550 {
Pawel Zarembski 0:01f31e923fe2 551 tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
Pawel Zarembski 0:01f31e923fe2 552 tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
Pawel Zarembski 0:01f31e923fe2 553 tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
Pawel Zarembski 0:01f31e923fe2 554 }
Pawel Zarembski 0:01f31e923fe2 555 }
Pawel Zarembski 0:01f31e923fe2 556
Pawel Zarembski 0:01f31e923fe2 557 /*!
Pawel Zarembski 0:01f31e923fe2 558 * brief Sets the source modulo and the destination modulo for the eDMA TCD.
Pawel Zarembski 0:01f31e923fe2 559 *
Pawel Zarembski 0:01f31e923fe2 560 * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
Pawel Zarembski 0:01f31e923fe2 561 * calculation is performed or the original register value. It provides the ability to implement a circular data
Pawel Zarembski 0:01f31e923fe2 562 * queue easily.
Pawel Zarembski 0:01f31e923fe2 563 *
Pawel Zarembski 0:01f31e923fe2 564 * param tcd A pointer to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 565 * param srcModulo A source modulo value.
Pawel Zarembski 0:01f31e923fe2 566 * param destModulo A destination modulo value.
Pawel Zarembski 0:01f31e923fe2 567 */
Pawel Zarembski 0:01f31e923fe2 568 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
Pawel Zarembski 0:01f31e923fe2 569 {
Pawel Zarembski 0:01f31e923fe2 570 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 571 assert(((uint32_t)tcd & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 572
Pawel Zarembski 0:01f31e923fe2 573 uint32_t tmpreg;
Pawel Zarembski 0:01f31e923fe2 574
Pawel Zarembski 0:01f31e923fe2 575 tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
Pawel Zarembski 0:01f31e923fe2 576 tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
Pawel Zarembski 0:01f31e923fe2 577 }
Pawel Zarembski 0:01f31e923fe2 578
Pawel Zarembski 0:01f31e923fe2 579 /*!
Pawel Zarembski 0:01f31e923fe2 580 * brief Enables the interrupt source for the eDMA TCD.
Pawel Zarembski 0:01f31e923fe2 581 *
Pawel Zarembski 0:01f31e923fe2 582 * param tcd Point to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 583 * param mask The mask of interrupt source to be set. Users need to use
Pawel Zarembski 0:01f31e923fe2 584 * the defined edma_interrupt_enable_t type.
Pawel Zarembski 0:01f31e923fe2 585 */
Pawel Zarembski 0:01f31e923fe2 586 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
Pawel Zarembski 0:01f31e923fe2 587 {
Pawel Zarembski 0:01f31e923fe2 588 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 589
Pawel Zarembski 0:01f31e923fe2 590 /* Enable Major interrupt */
Pawel Zarembski 0:01f31e923fe2 591 if (mask & kEDMA_MajorInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 592 {
Pawel Zarembski 0:01f31e923fe2 593 tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
Pawel Zarembski 0:01f31e923fe2 594 }
Pawel Zarembski 0:01f31e923fe2 595
Pawel Zarembski 0:01f31e923fe2 596 /* Enable Half major interrupt */
Pawel Zarembski 0:01f31e923fe2 597 if (mask & kEDMA_HalfInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 598 {
Pawel Zarembski 0:01f31e923fe2 599 tcd->CSR |= DMA_CSR_INTHALF_MASK;
Pawel Zarembski 0:01f31e923fe2 600 }
Pawel Zarembski 0:01f31e923fe2 601 }
Pawel Zarembski 0:01f31e923fe2 602
Pawel Zarembski 0:01f31e923fe2 603 /*!
Pawel Zarembski 0:01f31e923fe2 604 * brief Disables the interrupt source for the eDMA TCD.
Pawel Zarembski 0:01f31e923fe2 605 *
Pawel Zarembski 0:01f31e923fe2 606 * param tcd Point to the TCD structure.
Pawel Zarembski 0:01f31e923fe2 607 * param mask The mask of interrupt source to be set. Users need to use
Pawel Zarembski 0:01f31e923fe2 608 * the defined edma_interrupt_enable_t type.
Pawel Zarembski 0:01f31e923fe2 609 */
Pawel Zarembski 0:01f31e923fe2 610 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
Pawel Zarembski 0:01f31e923fe2 611 {
Pawel Zarembski 0:01f31e923fe2 612 assert(tcd != NULL);
Pawel Zarembski 0:01f31e923fe2 613
Pawel Zarembski 0:01f31e923fe2 614 /* Disable Major interrupt */
Pawel Zarembski 0:01f31e923fe2 615 if (mask & kEDMA_MajorInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 616 {
Pawel Zarembski 0:01f31e923fe2 617 tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
Pawel Zarembski 0:01f31e923fe2 618 }
Pawel Zarembski 0:01f31e923fe2 619
Pawel Zarembski 0:01f31e923fe2 620 /* Disable Half major interrupt */
Pawel Zarembski 0:01f31e923fe2 621 if (mask & kEDMA_HalfInterruptEnable)
Pawel Zarembski 0:01f31e923fe2 622 {
Pawel Zarembski 0:01f31e923fe2 623 tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
Pawel Zarembski 0:01f31e923fe2 624 }
Pawel Zarembski 0:01f31e923fe2 625 }
Pawel Zarembski 0:01f31e923fe2 626
Pawel Zarembski 0:01f31e923fe2 627 /*!
Pawel Zarembski 0:01f31e923fe2 628 * brief Gets the remaining major loop count from the eDMA current channel TCD.
Pawel Zarembski 0:01f31e923fe2 629 *
Pawel Zarembski 0:01f31e923fe2 630 * This function checks the TCD (Task Control Descriptor) status for a specified
Pawel Zarembski 0:01f31e923fe2 631 * eDMA channel and returns the number of major loop count that has not finished.
Pawel Zarembski 0:01f31e923fe2 632 *
Pawel Zarembski 0:01f31e923fe2 633 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 634 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 635 * return Major loop count which has not been transferred yet for the current TCD.
Pawel Zarembski 0:01f31e923fe2 636 * note 1. This function can only be used to get unfinished major loop count of transfer without
Pawel Zarembski 0:01f31e923fe2 637 * the next TCD, or it might be inaccuracy.
Pawel Zarembski 0:01f31e923fe2 638 * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
Pawel Zarembski 0:01f31e923fe2 639 * the channel is running.
Pawel Zarembski 0:01f31e923fe2 640 * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
Pawel Zarembski 0:01f31e923fe2 641 * register is needed while the eDMA IP does not support getting it while a channel is active.
Pawel Zarembski 0:01f31e923fe2 642 * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
Pawel Zarembski 0:01f31e923fe2 643 * is working with while a channel is running.
Pawel Zarembski 0:01f31e923fe2 644 * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
Pawel Zarembski 0:01f31e923fe2 645 * copied before enabling the channel) is needed. The formula to calculate it is shown below:
Pawel Zarembski 0:01f31e923fe2 646 * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
Pawel Zarembski 0:01f31e923fe2 647 */
Pawel Zarembski 0:01f31e923fe2 648 uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
Pawel Zarembski 0:01f31e923fe2 649 {
Pawel Zarembski 0:01f31e923fe2 650 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 651
Pawel Zarembski 0:01f31e923fe2 652 uint32_t remainingCount = 0;
Pawel Zarembski 0:01f31e923fe2 653
Pawel Zarembski 0:01f31e923fe2 654 if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
Pawel Zarembski 0:01f31e923fe2 655 {
Pawel Zarembski 0:01f31e923fe2 656 remainingCount = 0;
Pawel Zarembski 0:01f31e923fe2 657 }
Pawel Zarembski 0:01f31e923fe2 658 else
Pawel Zarembski 0:01f31e923fe2 659 {
Pawel Zarembski 0:01f31e923fe2 660 /* Calculate the unfinished bytes */
Pawel Zarembski 0:01f31e923fe2 661 if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
Pawel Zarembski 0:01f31e923fe2 662 {
Pawel Zarembski 0:01f31e923fe2 663 remainingCount =
Pawel Zarembski 0:01f31e923fe2 664 (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
Pawel Zarembski 0:01f31e923fe2 665 }
Pawel Zarembski 0:01f31e923fe2 666 else
Pawel Zarembski 0:01f31e923fe2 667 {
Pawel Zarembski 0:01f31e923fe2 668 remainingCount =
Pawel Zarembski 0:01f31e923fe2 669 (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
Pawel Zarembski 0:01f31e923fe2 670 }
Pawel Zarembski 0:01f31e923fe2 671 }
Pawel Zarembski 0:01f31e923fe2 672
Pawel Zarembski 0:01f31e923fe2 673 return remainingCount;
Pawel Zarembski 0:01f31e923fe2 674 }
Pawel Zarembski 0:01f31e923fe2 675
Pawel Zarembski 0:01f31e923fe2 676 /*!
Pawel Zarembski 0:01f31e923fe2 677 * brief Gets the eDMA channel status flags.
Pawel Zarembski 0:01f31e923fe2 678 *
Pawel Zarembski 0:01f31e923fe2 679 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 680 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 681 * return The mask of channel status flags. Users need to use the
Pawel Zarembski 0:01f31e923fe2 682 * _edma_channel_status_flags type to decode the return variables.
Pawel Zarembski 0:01f31e923fe2 683 */
Pawel Zarembski 0:01f31e923fe2 684 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
Pawel Zarembski 0:01f31e923fe2 685 {
Pawel Zarembski 0:01f31e923fe2 686 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 687
Pawel Zarembski 0:01f31e923fe2 688 uint32_t retval = 0;
Pawel Zarembski 0:01f31e923fe2 689
Pawel Zarembski 0:01f31e923fe2 690 /* Get DONE bit flag */
Pawel Zarembski 0:01f31e923fe2 691 retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
Pawel Zarembski 0:01f31e923fe2 692 /* Get ERROR bit flag */
Pawel Zarembski 0:01f31e923fe2 693 retval |= (((base->ERR >> channel) & 0x1U) << 1U);
Pawel Zarembski 0:01f31e923fe2 694 /* Get INT bit flag */
Pawel Zarembski 0:01f31e923fe2 695 retval |= (((base->INT >> channel) & 0x1U) << 2U);
Pawel Zarembski 0:01f31e923fe2 696
Pawel Zarembski 0:01f31e923fe2 697 return retval;
Pawel Zarembski 0:01f31e923fe2 698 }
Pawel Zarembski 0:01f31e923fe2 699
Pawel Zarembski 0:01f31e923fe2 700 /*!
Pawel Zarembski 0:01f31e923fe2 701 * brief Clears the eDMA channel status flags.
Pawel Zarembski 0:01f31e923fe2 702 *
Pawel Zarembski 0:01f31e923fe2 703 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 704 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 705 * param mask The mask of channel status to be cleared. Users need to use
Pawel Zarembski 0:01f31e923fe2 706 * the defined _edma_channel_status_flags type.
Pawel Zarembski 0:01f31e923fe2 707 */
Pawel Zarembski 0:01f31e923fe2 708 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
Pawel Zarembski 0:01f31e923fe2 709 {
Pawel Zarembski 0:01f31e923fe2 710 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 711
Pawel Zarembski 0:01f31e923fe2 712 /* Clear DONE bit flag */
Pawel Zarembski 0:01f31e923fe2 713 if (mask & kEDMA_DoneFlag)
Pawel Zarembski 0:01f31e923fe2 714 {
Pawel Zarembski 0:01f31e923fe2 715 base->CDNE = channel;
Pawel Zarembski 0:01f31e923fe2 716 }
Pawel Zarembski 0:01f31e923fe2 717 /* Clear ERROR bit flag */
Pawel Zarembski 0:01f31e923fe2 718 if (mask & kEDMA_ErrorFlag)
Pawel Zarembski 0:01f31e923fe2 719 {
Pawel Zarembski 0:01f31e923fe2 720 base->CERR = channel;
Pawel Zarembski 0:01f31e923fe2 721 }
Pawel Zarembski 0:01f31e923fe2 722 /* Clear INT bit flag */
Pawel Zarembski 0:01f31e923fe2 723 if (mask & kEDMA_InterruptFlag)
Pawel Zarembski 0:01f31e923fe2 724 {
Pawel Zarembski 0:01f31e923fe2 725 base->CINT = channel;
Pawel Zarembski 0:01f31e923fe2 726 }
Pawel Zarembski 0:01f31e923fe2 727 }
Pawel Zarembski 0:01f31e923fe2 728
Pawel Zarembski 0:01f31e923fe2 729 static uint8_t Get_StartInstance(void)
Pawel Zarembski 0:01f31e923fe2 730 {
Pawel Zarembski 0:01f31e923fe2 731 static uint8_t StartInstanceNum;
Pawel Zarembski 0:01f31e923fe2 732
Pawel Zarembski 0:01f31e923fe2 733 #if defined(DMA0)
Pawel Zarembski 0:01f31e923fe2 734 StartInstanceNum = EDMA_GetInstance(DMA0);
Pawel Zarembski 0:01f31e923fe2 735 #elif defined(DMA1)
Pawel Zarembski 0:01f31e923fe2 736 StartInstanceNum = EDMA_GetInstance(DMA1);
Pawel Zarembski 0:01f31e923fe2 737 #elif defined(DMA2)
Pawel Zarembski 0:01f31e923fe2 738 StartInstanceNum = EDMA_GetInstance(DMA2);
Pawel Zarembski 0:01f31e923fe2 739 #elif defined(DMA3)
Pawel Zarembski 0:01f31e923fe2 740 StartInstanceNum = EDMA_GetInstance(DMA3);
Pawel Zarembski 0:01f31e923fe2 741 #endif
Pawel Zarembski 0:01f31e923fe2 742
Pawel Zarembski 0:01f31e923fe2 743 return StartInstanceNum;
Pawel Zarembski 0:01f31e923fe2 744 }
Pawel Zarembski 0:01f31e923fe2 745
Pawel Zarembski 0:01f31e923fe2 746 /*!
Pawel Zarembski 0:01f31e923fe2 747 * brief Creates the eDMA handle.
Pawel Zarembski 0:01f31e923fe2 748 *
Pawel Zarembski 0:01f31e923fe2 749 * This function is called if using the transactional API for eDMA. This function
Pawel Zarembski 0:01f31e923fe2 750 * initializes the internal state of the eDMA handle.
Pawel Zarembski 0:01f31e923fe2 751 *
Pawel Zarembski 0:01f31e923fe2 752 * param handle eDMA handle pointer. The eDMA handle stores callback function and
Pawel Zarembski 0:01f31e923fe2 753 * parameters.
Pawel Zarembski 0:01f31e923fe2 754 * param base eDMA peripheral base address.
Pawel Zarembski 0:01f31e923fe2 755 * param channel eDMA channel number.
Pawel Zarembski 0:01f31e923fe2 756 */
Pawel Zarembski 0:01f31e923fe2 757 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
Pawel Zarembski 0:01f31e923fe2 758 {
Pawel Zarembski 0:01f31e923fe2 759 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 760 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
Pawel Zarembski 0:01f31e923fe2 761
Pawel Zarembski 0:01f31e923fe2 762 uint32_t edmaInstance;
Pawel Zarembski 0:01f31e923fe2 763 uint32_t channelIndex;
Pawel Zarembski 0:01f31e923fe2 764 uint8_t StartInstance;
Pawel Zarembski 0:01f31e923fe2 765 edma_tcd_t *tcdRegs;
Pawel Zarembski 0:01f31e923fe2 766
Pawel Zarembski 0:01f31e923fe2 767 /* Zero the handle */
Pawel Zarembski 0:01f31e923fe2 768 memset(handle, 0, sizeof(*handle));
Pawel Zarembski 0:01f31e923fe2 769
Pawel Zarembski 0:01f31e923fe2 770 handle->base = base;
Pawel Zarembski 0:01f31e923fe2 771 handle->channel = channel;
Pawel Zarembski 0:01f31e923fe2 772 /* Get the DMA instance number */
Pawel Zarembski 0:01f31e923fe2 773 edmaInstance = EDMA_GetInstance(base);
Pawel Zarembski 0:01f31e923fe2 774 StartInstance = Get_StartInstance();
Pawel Zarembski 0:01f31e923fe2 775 channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
Pawel Zarembski 0:01f31e923fe2 776 s_EDMAHandle[channelIndex] = handle;
Pawel Zarembski 0:01f31e923fe2 777
Pawel Zarembski 0:01f31e923fe2 778 /* Enable NVIC interrupt */
Pawel Zarembski 0:01f31e923fe2 779 EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
Pawel Zarembski 0:01f31e923fe2 780
Pawel Zarembski 0:01f31e923fe2 781 /*
Pawel Zarembski 0:01f31e923fe2 782 Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
Pawel Zarembski 0:01f31e923fe2 783 CSR will be 0. Because in order to suit EDMA busy check mechanism in
Pawel Zarembski 0:01f31e923fe2 784 EDMA_SubmitTransfer, CSR must be set 0.
Pawel Zarembski 0:01f31e923fe2 785 */
Pawel Zarembski 0:01f31e923fe2 786 tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
Pawel Zarembski 0:01f31e923fe2 787 tcdRegs->SADDR = 0;
Pawel Zarembski 0:01f31e923fe2 788 tcdRegs->SOFF = 0;
Pawel Zarembski 0:01f31e923fe2 789 tcdRegs->ATTR = 0;
Pawel Zarembski 0:01f31e923fe2 790 tcdRegs->NBYTES = 0;
Pawel Zarembski 0:01f31e923fe2 791 tcdRegs->SLAST = 0;
Pawel Zarembski 0:01f31e923fe2 792 tcdRegs->DADDR = 0;
Pawel Zarembski 0:01f31e923fe2 793 tcdRegs->DOFF = 0;
Pawel Zarembski 0:01f31e923fe2 794 tcdRegs->CITER = 0;
Pawel Zarembski 0:01f31e923fe2 795 tcdRegs->DLAST_SGA = 0;
Pawel Zarembski 0:01f31e923fe2 796 tcdRegs->CSR = 0;
Pawel Zarembski 0:01f31e923fe2 797 tcdRegs->BITER = 0;
Pawel Zarembski 0:01f31e923fe2 798 }
Pawel Zarembski 0:01f31e923fe2 799
Pawel Zarembski 0:01f31e923fe2 800 /*!
Pawel Zarembski 0:01f31e923fe2 801 * brief Installs the TCDs memory pool into the eDMA handle.
Pawel Zarembski 0:01f31e923fe2 802 *
Pawel Zarembski 0:01f31e923fe2 803 * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
Pawel Zarembski 0:01f31e923fe2 804 * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
Pawel Zarembski 0:01f31e923fe2 805 * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
Pawel Zarembski 0:01f31e923fe2 806 * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
Pawel Zarembski 0:01f31e923fe2 807 *
Pawel Zarembski 0:01f31e923fe2 808 * param handle eDMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 809 * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
Pawel Zarembski 0:01f31e923fe2 810 * param tcdSize The number of TCD slots.
Pawel Zarembski 0:01f31e923fe2 811 */
Pawel Zarembski 0:01f31e923fe2 812 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
Pawel Zarembski 0:01f31e923fe2 813 {
Pawel Zarembski 0:01f31e923fe2 814 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 815 assert(((uint32_t)tcdPool & 0x1FU) == 0);
Pawel Zarembski 0:01f31e923fe2 816
Pawel Zarembski 0:01f31e923fe2 817 /* Initialize tcd queue attribute. */
Pawel Zarembski 0:01f31e923fe2 818 handle->header = 0;
Pawel Zarembski 0:01f31e923fe2 819 handle->tail = 0;
Pawel Zarembski 0:01f31e923fe2 820 handle->tcdUsed = 0;
Pawel Zarembski 0:01f31e923fe2 821 handle->tcdSize = tcdSize;
Pawel Zarembski 0:01f31e923fe2 822 handle->flags = 0;
Pawel Zarembski 0:01f31e923fe2 823 handle->tcdPool = tcdPool;
Pawel Zarembski 0:01f31e923fe2 824 }
Pawel Zarembski 0:01f31e923fe2 825
Pawel Zarembski 0:01f31e923fe2 826 /*!
Pawel Zarembski 0:01f31e923fe2 827 * brief Installs a callback function for the eDMA transfer.
Pawel Zarembski 0:01f31e923fe2 828 *
Pawel Zarembski 0:01f31e923fe2 829 * This callback is called in the eDMA IRQ handler. Use the callback to do something after
Pawel Zarembski 0:01f31e923fe2 830 * the current major loop transfer completes. This function will be called every time one tcd finished transfer.
Pawel Zarembski 0:01f31e923fe2 831 *
Pawel Zarembski 0:01f31e923fe2 832 * param handle eDMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 833 * param callback eDMA callback function pointer.
Pawel Zarembski 0:01f31e923fe2 834 * param userData A parameter for the callback function.
Pawel Zarembski 0:01f31e923fe2 835 */
Pawel Zarembski 0:01f31e923fe2 836 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
Pawel Zarembski 0:01f31e923fe2 837 {
Pawel Zarembski 0:01f31e923fe2 838 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 839
Pawel Zarembski 0:01f31e923fe2 840 handle->callback = callback;
Pawel Zarembski 0:01f31e923fe2 841 handle->userData = userData;
Pawel Zarembski 0:01f31e923fe2 842 }
Pawel Zarembski 0:01f31e923fe2 843
Pawel Zarembski 0:01f31e923fe2 844 /*!
Pawel Zarembski 0:01f31e923fe2 845 * brief Prepares the eDMA transfer structure.
Pawel Zarembski 0:01f31e923fe2 846 *
Pawel Zarembski 0:01f31e923fe2 847 * This function prepares the transfer configuration structure according to the user input.
Pawel Zarembski 0:01f31e923fe2 848 *
Pawel Zarembski 0:01f31e923fe2 849 * param config The user configuration structure of type edma_transfer_t.
Pawel Zarembski 0:01f31e923fe2 850 * param srcAddr eDMA transfer source address.
Pawel Zarembski 0:01f31e923fe2 851 * param srcWidth eDMA transfer source address width(bytes).
Pawel Zarembski 0:01f31e923fe2 852 * param destAddr eDMA transfer destination address.
Pawel Zarembski 0:01f31e923fe2 853 * param destWidth eDMA transfer destination address width(bytes).
Pawel Zarembski 0:01f31e923fe2 854 * param bytesEachRequest eDMA transfer bytes per channel request.
Pawel Zarembski 0:01f31e923fe2 855 * param transferBytes eDMA transfer bytes to be transferred.
Pawel Zarembski 0:01f31e923fe2 856 * param type eDMA transfer type.
Pawel Zarembski 0:01f31e923fe2 857 * note The data address and the data width must be consistent. For example, if the SRC
Pawel Zarembski 0:01f31e923fe2 858 * is 4 bytes, the source address must be 4 bytes aligned, or it results in
Pawel Zarembski 0:01f31e923fe2 859 * source address error (SAE).
Pawel Zarembski 0:01f31e923fe2 860 */
Pawel Zarembski 0:01f31e923fe2 861 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
Pawel Zarembski 0:01f31e923fe2 862 void *srcAddr,
Pawel Zarembski 0:01f31e923fe2 863 uint32_t srcWidth,
Pawel Zarembski 0:01f31e923fe2 864 void *destAddr,
Pawel Zarembski 0:01f31e923fe2 865 uint32_t destWidth,
Pawel Zarembski 0:01f31e923fe2 866 uint32_t bytesEachRequest,
Pawel Zarembski 0:01f31e923fe2 867 uint32_t transferBytes,
Pawel Zarembski 0:01f31e923fe2 868 edma_transfer_type_t type)
Pawel Zarembski 0:01f31e923fe2 869 {
Pawel Zarembski 0:01f31e923fe2 870 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 871 assert(srcAddr != NULL);
Pawel Zarembski 0:01f31e923fe2 872 assert(destAddr != NULL);
Pawel Zarembski 0:01f31e923fe2 873 assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
Pawel Zarembski 0:01f31e923fe2 874 assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
Pawel Zarembski 0:01f31e923fe2 875 assert(transferBytes % bytesEachRequest == 0);
Pawel Zarembski 0:01f31e923fe2 876
Pawel Zarembski 0:01f31e923fe2 877 /* Initializes the configure structure to zero. */
Pawel Zarembski 0:01f31e923fe2 878 memset(config, 0, sizeof(*config));
Pawel Zarembski 0:01f31e923fe2 879
Pawel Zarembski 0:01f31e923fe2 880 config->destAddr = (uint32_t)destAddr;
Pawel Zarembski 0:01f31e923fe2 881 config->srcAddr = (uint32_t)srcAddr;
Pawel Zarembski 0:01f31e923fe2 882 config->minorLoopBytes = bytesEachRequest;
Pawel Zarembski 0:01f31e923fe2 883 config->majorLoopCounts = transferBytes / bytesEachRequest;
Pawel Zarembski 0:01f31e923fe2 884 switch (srcWidth)
Pawel Zarembski 0:01f31e923fe2 885 {
Pawel Zarembski 0:01f31e923fe2 886 case 1U:
Pawel Zarembski 0:01f31e923fe2 887 config->srcTransferSize = kEDMA_TransferSize1Bytes;
Pawel Zarembski 0:01f31e923fe2 888 break;
Pawel Zarembski 0:01f31e923fe2 889 case 2U:
Pawel Zarembski 0:01f31e923fe2 890 config->srcTransferSize = kEDMA_TransferSize2Bytes;
Pawel Zarembski 0:01f31e923fe2 891 break;
Pawel Zarembski 0:01f31e923fe2 892 case 4U:
Pawel Zarembski 0:01f31e923fe2 893 config->srcTransferSize = kEDMA_TransferSize4Bytes;
Pawel Zarembski 0:01f31e923fe2 894 break;
Pawel Zarembski 0:01f31e923fe2 895 case 16U:
Pawel Zarembski 0:01f31e923fe2 896 config->srcTransferSize = kEDMA_TransferSize16Bytes;
Pawel Zarembski 0:01f31e923fe2 897 break;
Pawel Zarembski 0:01f31e923fe2 898 case 32U:
Pawel Zarembski 0:01f31e923fe2 899 config->srcTransferSize = kEDMA_TransferSize32Bytes;
Pawel Zarembski 0:01f31e923fe2 900 break;
Pawel Zarembski 0:01f31e923fe2 901 default:
Pawel Zarembski 0:01f31e923fe2 902 break;
Pawel Zarembski 0:01f31e923fe2 903 }
Pawel Zarembski 0:01f31e923fe2 904 switch (destWidth)
Pawel Zarembski 0:01f31e923fe2 905 {
Pawel Zarembski 0:01f31e923fe2 906 case 1U:
Pawel Zarembski 0:01f31e923fe2 907 config->destTransferSize = kEDMA_TransferSize1Bytes;
Pawel Zarembski 0:01f31e923fe2 908 break;
Pawel Zarembski 0:01f31e923fe2 909 case 2U:
Pawel Zarembski 0:01f31e923fe2 910 config->destTransferSize = kEDMA_TransferSize2Bytes;
Pawel Zarembski 0:01f31e923fe2 911 break;
Pawel Zarembski 0:01f31e923fe2 912 case 4U:
Pawel Zarembski 0:01f31e923fe2 913 config->destTransferSize = kEDMA_TransferSize4Bytes;
Pawel Zarembski 0:01f31e923fe2 914 break;
Pawel Zarembski 0:01f31e923fe2 915 case 16U:
Pawel Zarembski 0:01f31e923fe2 916 config->destTransferSize = kEDMA_TransferSize16Bytes;
Pawel Zarembski 0:01f31e923fe2 917 break;
Pawel Zarembski 0:01f31e923fe2 918 case 32U:
Pawel Zarembski 0:01f31e923fe2 919 config->destTransferSize = kEDMA_TransferSize32Bytes;
Pawel Zarembski 0:01f31e923fe2 920 break;
Pawel Zarembski 0:01f31e923fe2 921 default:
Pawel Zarembski 0:01f31e923fe2 922 break;
Pawel Zarembski 0:01f31e923fe2 923 }
Pawel Zarembski 0:01f31e923fe2 924 switch (type)
Pawel Zarembski 0:01f31e923fe2 925 {
Pawel Zarembski 0:01f31e923fe2 926 case kEDMA_MemoryToMemory:
Pawel Zarembski 0:01f31e923fe2 927 config->destOffset = destWidth;
Pawel Zarembski 0:01f31e923fe2 928 config->srcOffset = srcWidth;
Pawel Zarembski 0:01f31e923fe2 929 break;
Pawel Zarembski 0:01f31e923fe2 930 case kEDMA_MemoryToPeripheral:
Pawel Zarembski 0:01f31e923fe2 931 config->destOffset = 0U;
Pawel Zarembski 0:01f31e923fe2 932 config->srcOffset = srcWidth;
Pawel Zarembski 0:01f31e923fe2 933 break;
Pawel Zarembski 0:01f31e923fe2 934 case kEDMA_PeripheralToMemory:
Pawel Zarembski 0:01f31e923fe2 935 config->destOffset = destWidth;
Pawel Zarembski 0:01f31e923fe2 936 config->srcOffset = 0U;
Pawel Zarembski 0:01f31e923fe2 937 break;
Pawel Zarembski 0:01f31e923fe2 938 default:
Pawel Zarembski 0:01f31e923fe2 939 break;
Pawel Zarembski 0:01f31e923fe2 940 }
Pawel Zarembski 0:01f31e923fe2 941 }
Pawel Zarembski 0:01f31e923fe2 942
Pawel Zarembski 0:01f31e923fe2 943 /*!
Pawel Zarembski 0:01f31e923fe2 944 * brief Submits the eDMA transfer request.
Pawel Zarembski 0:01f31e923fe2 945 *
Pawel Zarembski 0:01f31e923fe2 946 * This function submits the eDMA transfer request according to the transfer configuration structure.
Pawel Zarembski 0:01f31e923fe2 947 * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
Pawel Zarembski 0:01f31e923fe2 948 * The tcd pools is setup by call function EDMA_InstallTCDMemory before.
Pawel Zarembski 0:01f31e923fe2 949 *
Pawel Zarembski 0:01f31e923fe2 950 * param handle eDMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 951 * param config Pointer to eDMA transfer configuration structure.
Pawel Zarembski 0:01f31e923fe2 952 * retval kStatus_EDMA_Success It means submit transfer request succeed.
Pawel Zarembski 0:01f31e923fe2 953 * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
Pawel Zarembski 0:01f31e923fe2 954 * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
Pawel Zarembski 0:01f31e923fe2 955 */
Pawel Zarembski 0:01f31e923fe2 956 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
Pawel Zarembski 0:01f31e923fe2 957 {
Pawel Zarembski 0:01f31e923fe2 958 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 959 assert(config != NULL);
Pawel Zarembski 0:01f31e923fe2 960
Pawel Zarembski 0:01f31e923fe2 961 edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
Pawel Zarembski 0:01f31e923fe2 962
Pawel Zarembski 0:01f31e923fe2 963 if (handle->tcdPool == NULL)
Pawel Zarembski 0:01f31e923fe2 964 {
Pawel Zarembski 0:01f31e923fe2 965 /*
Pawel Zarembski 0:01f31e923fe2 966 Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
Pawel Zarembski 0:01f31e923fe2 967 if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
Pawel Zarembski 0:01f31e923fe2 968 this check mechanism, EDMA_CreatHandle will clear CSR register.
Pawel Zarembski 0:01f31e923fe2 969 */
Pawel Zarembski 0:01f31e923fe2 970 if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
Pawel Zarembski 0:01f31e923fe2 971 {
Pawel Zarembski 0:01f31e923fe2 972 return kStatus_EDMA_Busy;
Pawel Zarembski 0:01f31e923fe2 973 }
Pawel Zarembski 0:01f31e923fe2 974 else
Pawel Zarembski 0:01f31e923fe2 975 {
Pawel Zarembski 0:01f31e923fe2 976 EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL);
Pawel Zarembski 0:01f31e923fe2 977 /* Enable auto disable request feature */
Pawel Zarembski 0:01f31e923fe2 978 handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK;
Pawel Zarembski 0:01f31e923fe2 979 /* Enable major interrupt */
Pawel Zarembski 0:01f31e923fe2 980 handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK;
Pawel Zarembski 0:01f31e923fe2 981
Pawel Zarembski 0:01f31e923fe2 982 return kStatus_Success;
Pawel Zarembski 0:01f31e923fe2 983 }
Pawel Zarembski 0:01f31e923fe2 984 }
Pawel Zarembski 0:01f31e923fe2 985 else /* Use the TCD queue. */
Pawel Zarembski 0:01f31e923fe2 986 {
Pawel Zarembski 0:01f31e923fe2 987 uint32_t primask;
Pawel Zarembski 0:01f31e923fe2 988 uint32_t csr;
Pawel Zarembski 0:01f31e923fe2 989 int8_t currentTcd;
Pawel Zarembski 0:01f31e923fe2 990 int8_t previousTcd;
Pawel Zarembski 0:01f31e923fe2 991 int8_t nextTcd;
Pawel Zarembski 0:01f31e923fe2 992
Pawel Zarembski 0:01f31e923fe2 993 /* Check if tcd pool is full. */
Pawel Zarembski 0:01f31e923fe2 994 primask = DisableGlobalIRQ();
Pawel Zarembski 0:01f31e923fe2 995 if (handle->tcdUsed >= handle->tcdSize)
Pawel Zarembski 0:01f31e923fe2 996 {
Pawel Zarembski 0:01f31e923fe2 997 EnableGlobalIRQ(primask);
Pawel Zarembski 0:01f31e923fe2 998
Pawel Zarembski 0:01f31e923fe2 999 return kStatus_EDMA_QueueFull;
Pawel Zarembski 0:01f31e923fe2 1000 }
Pawel Zarembski 0:01f31e923fe2 1001 currentTcd = handle->tail;
Pawel Zarembski 0:01f31e923fe2 1002 handle->tcdUsed++;
Pawel Zarembski 0:01f31e923fe2 1003 /* Calculate index of next TCD */
Pawel Zarembski 0:01f31e923fe2 1004 nextTcd = currentTcd + 1U;
Pawel Zarembski 0:01f31e923fe2 1005 if (nextTcd == handle->tcdSize)
Pawel Zarembski 0:01f31e923fe2 1006 {
Pawel Zarembski 0:01f31e923fe2 1007 nextTcd = 0U;
Pawel Zarembski 0:01f31e923fe2 1008 }
Pawel Zarembski 0:01f31e923fe2 1009 /* Advance queue tail index */
Pawel Zarembski 0:01f31e923fe2 1010 handle->tail = nextTcd;
Pawel Zarembski 0:01f31e923fe2 1011 EnableGlobalIRQ(primask);
Pawel Zarembski 0:01f31e923fe2 1012 /* Calculate index of previous TCD */
Pawel Zarembski 0:01f31e923fe2 1013 previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
Pawel Zarembski 0:01f31e923fe2 1014 /* Configure current TCD block. */
Pawel Zarembski 0:01f31e923fe2 1015 EDMA_TcdReset(&handle->tcdPool[currentTcd]);
Pawel Zarembski 0:01f31e923fe2 1016 EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
Pawel Zarembski 0:01f31e923fe2 1017 /* Enable major interrupt */
Pawel Zarembski 0:01f31e923fe2 1018 handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
Pawel Zarembski 0:01f31e923fe2 1019 /* Link current TCD with next TCD for identification of current TCD */
Pawel Zarembski 0:01f31e923fe2 1020 handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
Pawel Zarembski 0:01f31e923fe2 1021 /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
Pawel Zarembski 0:01f31e923fe2 1022 if (currentTcd != previousTcd)
Pawel Zarembski 0:01f31e923fe2 1023 {
Pawel Zarembski 0:01f31e923fe2 1024 /* Enable scatter/gather feature in the previous TCD block. */
Pawel Zarembski 0:01f31e923fe2 1025 csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
Pawel Zarembski 0:01f31e923fe2 1026 handle->tcdPool[previousTcd].CSR = csr;
Pawel Zarembski 0:01f31e923fe2 1027 /*
Pawel Zarembski 0:01f31e923fe2 1028 Check if the TCD block in the registers is the previous one (points to current TCD block). It
Pawel Zarembski 0:01f31e923fe2 1029 is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
Pawel Zarembski 0:01f31e923fe2 1030 link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
Pawel Zarembski 0:01f31e923fe2 1031 before link the previous TCD block.
Pawel Zarembski 0:01f31e923fe2 1032 */
Pawel Zarembski 0:01f31e923fe2 1033 if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
Pawel Zarembski 0:01f31e923fe2 1034 {
Pawel Zarembski 0:01f31e923fe2 1035 /* Clear the DREQ bits for the dynamic scatter gather */
Pawel Zarembski 0:01f31e923fe2 1036 tcdRegs->CSR |= DMA_CSR_DREQ_MASK;
Pawel Zarembski 0:01f31e923fe2 1037 /* Enable scatter/gather also in the TCD registers. */
Pawel Zarembski 0:01f31e923fe2 1038 csr = tcdRegs->CSR | DMA_CSR_ESG_MASK;
Pawel Zarembski 0:01f31e923fe2 1039 /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
Pawel Zarembski 0:01f31e923fe2 1040 tcdRegs->CSR = csr;
Pawel Zarembski 0:01f31e923fe2 1041 /*
Pawel Zarembski 0:01f31e923fe2 1042 It is very important to check the ESG bit!
Pawel Zarembski 0:01f31e923fe2 1043 Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
Pawel Zarembski 0:01f31e923fe2 1044 be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
Pawel Zarembski 0:01f31e923fe2 1045 and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
Pawel Zarembski 0:01f31e923fe2 1046 the current TCD block has been loaded into TCD registers), it means transfer finished
Pawel Zarembski 0:01f31e923fe2 1047 and TCD link operation fail, so must install TCD content into TCD registers and enable
Pawel Zarembski 0:01f31e923fe2 1048 transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic
Pawel Zarembski 0:01f31e923fe2 1049 link succeed.
Pawel Zarembski 0:01f31e923fe2 1050 */
Pawel Zarembski 0:01f31e923fe2 1051 if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
Pawel Zarembski 0:01f31e923fe2 1052 {
Pawel Zarembski 0:01f31e923fe2 1053 tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
Pawel Zarembski 0:01f31e923fe2 1054 return kStatus_Success;
Pawel Zarembski 0:01f31e923fe2 1055 }
Pawel Zarembski 0:01f31e923fe2 1056 /*
Pawel Zarembski 0:01f31e923fe2 1057 Check whether the current TCD block is already loaded in the TCD registers. It is another
Pawel Zarembski 0:01f31e923fe2 1058 condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
Pawel Zarembski 0:01f31e923fe2 1059 TCD block has been loaded into TCD registers.
Pawel Zarembski 0:01f31e923fe2 1060 */
Pawel Zarembski 0:01f31e923fe2 1061 if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
Pawel Zarembski 0:01f31e923fe2 1062 {
Pawel Zarembski 0:01f31e923fe2 1063 return kStatus_Success;
Pawel Zarembski 0:01f31e923fe2 1064 }
Pawel Zarembski 0:01f31e923fe2 1065 /*
Pawel Zarembski 0:01f31e923fe2 1066 If go to this, means the previous transfer finished, and the DONE bit is set.
Pawel Zarembski 0:01f31e923fe2 1067 So shall configure TCD registers.
Pawel Zarembski 0:01f31e923fe2 1068 */
Pawel Zarembski 0:01f31e923fe2 1069 }
Pawel Zarembski 0:01f31e923fe2 1070 else if (tcdRegs->DLAST_SGA != 0)
Pawel Zarembski 0:01f31e923fe2 1071 {
Pawel Zarembski 0:01f31e923fe2 1072 /* The current TCD block has been linked successfully. */
Pawel Zarembski 0:01f31e923fe2 1073 return kStatus_Success;
Pawel Zarembski 0:01f31e923fe2 1074 }
Pawel Zarembski 0:01f31e923fe2 1075 else
Pawel Zarembski 0:01f31e923fe2 1076 {
Pawel Zarembski 0:01f31e923fe2 1077 /*
Pawel Zarembski 0:01f31e923fe2 1078 DLAST_SGA is 0 and it means the first submit transfer, so shall configure
Pawel Zarembski 0:01f31e923fe2 1079 TCD registers.
Pawel Zarembski 0:01f31e923fe2 1080 */
Pawel Zarembski 0:01f31e923fe2 1081 }
Pawel Zarembski 0:01f31e923fe2 1082 }
Pawel Zarembski 0:01f31e923fe2 1083 /* There is no live chain, TCD block need to be installed in TCD registers. */
Pawel Zarembski 0:01f31e923fe2 1084 EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
Pawel Zarembski 0:01f31e923fe2 1085 /* Enable channel request again. */
Pawel Zarembski 0:01f31e923fe2 1086 if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
Pawel Zarembski 0:01f31e923fe2 1087 {
Pawel Zarembski 0:01f31e923fe2 1088 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
Pawel Zarembski 0:01f31e923fe2 1089 }
Pawel Zarembski 0:01f31e923fe2 1090
Pawel Zarembski 0:01f31e923fe2 1091 return kStatus_Success;
Pawel Zarembski 0:01f31e923fe2 1092 }
Pawel Zarembski 0:01f31e923fe2 1093 }
Pawel Zarembski 0:01f31e923fe2 1094
Pawel Zarembski 0:01f31e923fe2 1095 /*!
Pawel Zarembski 0:01f31e923fe2 1096 * brief eDMA starts transfer.
Pawel Zarembski 0:01f31e923fe2 1097 *
Pawel Zarembski 0:01f31e923fe2 1098 * This function enables the channel request. Users can call this function after submitting the transfer request
Pawel Zarembski 0:01f31e923fe2 1099 * or before submitting the transfer request.
Pawel Zarembski 0:01f31e923fe2 1100 *
Pawel Zarembski 0:01f31e923fe2 1101 * param handle eDMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 1102 */
Pawel Zarembski 0:01f31e923fe2 1103 void EDMA_StartTransfer(edma_handle_t *handle)
Pawel Zarembski 0:01f31e923fe2 1104 {
Pawel Zarembski 0:01f31e923fe2 1105 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 1106
Pawel Zarembski 0:01f31e923fe2 1107 if (handle->tcdPool == NULL)
Pawel Zarembski 0:01f31e923fe2 1108 {
Pawel Zarembski 0:01f31e923fe2 1109 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
Pawel Zarembski 0:01f31e923fe2 1110 }
Pawel Zarembski 0:01f31e923fe2 1111 else /* Use the TCD queue. */
Pawel Zarembski 0:01f31e923fe2 1112 {
Pawel Zarembski 0:01f31e923fe2 1113 uint32_t primask;
Pawel Zarembski 0:01f31e923fe2 1114 edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
Pawel Zarembski 0:01f31e923fe2 1115
Pawel Zarembski 0:01f31e923fe2 1116 handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
Pawel Zarembski 0:01f31e923fe2 1117
Pawel Zarembski 0:01f31e923fe2 1118 /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
Pawel Zarembski 0:01f31e923fe2 1119 if (tcdRegs->DLAST_SGA != 0U)
Pawel Zarembski 0:01f31e923fe2 1120 {
Pawel Zarembski 0:01f31e923fe2 1121 primask = DisableGlobalIRQ();
Pawel Zarembski 0:01f31e923fe2 1122 /* Check if channel request is actually disable. */
Pawel Zarembski 0:01f31e923fe2 1123 if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
Pawel Zarembski 0:01f31e923fe2 1124 {
Pawel Zarembski 0:01f31e923fe2 1125 /* Check if transfer is paused. */
Pawel Zarembski 0:01f31e923fe2 1126 if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
Pawel Zarembski 0:01f31e923fe2 1127 {
Pawel Zarembski 0:01f31e923fe2 1128 /*
Pawel Zarembski 0:01f31e923fe2 1129 Re-enable channel request must be as soon as possible, so must put it into
Pawel Zarembski 0:01f31e923fe2 1130 critical section to avoid task switching or interrupt service routine.
Pawel Zarembski 0:01f31e923fe2 1131 */
Pawel Zarembski 0:01f31e923fe2 1132 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
Pawel Zarembski 0:01f31e923fe2 1133 }
Pawel Zarembski 0:01f31e923fe2 1134 }
Pawel Zarembski 0:01f31e923fe2 1135 EnableGlobalIRQ(primask);
Pawel Zarembski 0:01f31e923fe2 1136 }
Pawel Zarembski 0:01f31e923fe2 1137 }
Pawel Zarembski 0:01f31e923fe2 1138 }
Pawel Zarembski 0:01f31e923fe2 1139
Pawel Zarembski 0:01f31e923fe2 1140 /*!
Pawel Zarembski 0:01f31e923fe2 1141 * brief eDMA stops transfer.
Pawel Zarembski 0:01f31e923fe2 1142 *
Pawel Zarembski 0:01f31e923fe2 1143 * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
Pawel Zarembski 0:01f31e923fe2 1144 * again to resume the transfer.
Pawel Zarembski 0:01f31e923fe2 1145 *
Pawel Zarembski 0:01f31e923fe2 1146 * param handle eDMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 1147 */
Pawel Zarembski 0:01f31e923fe2 1148 void EDMA_StopTransfer(edma_handle_t *handle)
Pawel Zarembski 0:01f31e923fe2 1149 {
Pawel Zarembski 0:01f31e923fe2 1150 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 1151
Pawel Zarembski 0:01f31e923fe2 1152 handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
Pawel Zarembski 0:01f31e923fe2 1153 handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
Pawel Zarembski 0:01f31e923fe2 1154 }
Pawel Zarembski 0:01f31e923fe2 1155
Pawel Zarembski 0:01f31e923fe2 1156 /*!
Pawel Zarembski 0:01f31e923fe2 1157 * brief eDMA aborts transfer.
Pawel Zarembski 0:01f31e923fe2 1158 *
Pawel Zarembski 0:01f31e923fe2 1159 * This function disables the channel request and clear transfer status bits.
Pawel Zarembski 0:01f31e923fe2 1160 * Users can submit another transfer after calling this API.
Pawel Zarembski 0:01f31e923fe2 1161 *
Pawel Zarembski 0:01f31e923fe2 1162 * param handle DMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 1163 */
Pawel Zarembski 0:01f31e923fe2 1164 void EDMA_AbortTransfer(edma_handle_t *handle)
Pawel Zarembski 0:01f31e923fe2 1165 {
Pawel Zarembski 0:01f31e923fe2 1166 handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
Pawel Zarembski 0:01f31e923fe2 1167 /*
Pawel Zarembski 0:01f31e923fe2 1168 Clear CSR to release channel. Because if the given channel started transfer,
Pawel Zarembski 0:01f31e923fe2 1169 CSR will be not zero. Because if it is the last transfer, DREQ will be set.
Pawel Zarembski 0:01f31e923fe2 1170 If not, ESG will be set.
Pawel Zarembski 0:01f31e923fe2 1171 */
Pawel Zarembski 0:01f31e923fe2 1172 handle->base->TCD[handle->channel].CSR = 0;
Pawel Zarembski 0:01f31e923fe2 1173 /* Cancel all next TCD transfer. */
Pawel Zarembski 0:01f31e923fe2 1174 handle->base->TCD[handle->channel].DLAST_SGA = 0;
Pawel Zarembski 0:01f31e923fe2 1175
Pawel Zarembski 0:01f31e923fe2 1176 /* Handle the tcd */
Pawel Zarembski 0:01f31e923fe2 1177 if (handle->tcdPool != NULL)
Pawel Zarembski 0:01f31e923fe2 1178 {
Pawel Zarembski 0:01f31e923fe2 1179 handle->header = 0;
Pawel Zarembski 0:01f31e923fe2 1180 handle->tail = 0;
Pawel Zarembski 0:01f31e923fe2 1181 handle->tcdUsed = 0;
Pawel Zarembski 0:01f31e923fe2 1182 }
Pawel Zarembski 0:01f31e923fe2 1183 }
Pawel Zarembski 0:01f31e923fe2 1184
Pawel Zarembski 0:01f31e923fe2 1185 /*!
Pawel Zarembski 0:01f31e923fe2 1186 * brief eDMA IRQ handler for the current major loop transfer completion.
Pawel Zarembski 0:01f31e923fe2 1187 *
Pawel Zarembski 0:01f31e923fe2 1188 * This function clears the channel major interrupt flag and calls
Pawel Zarembski 0:01f31e923fe2 1189 * the callback function if it is not NULL.
Pawel Zarembski 0:01f31e923fe2 1190 *
Pawel Zarembski 0:01f31e923fe2 1191 * Note:
Pawel Zarembski 0:01f31e923fe2 1192 * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
Pawel Zarembski 0:01f31e923fe2 1193 * These include the final address adjustments and reloading of the BITER field into the CITER.
Pawel Zarembski 0:01f31e923fe2 1194 * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
Pawel Zarembski 0:01f31e923fe2 1195 * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
Pawel Zarembski 0:01f31e923fe2 1196 *
Pawel Zarembski 0:01f31e923fe2 1197 * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
Pawel Zarembski 0:01f31e923fe2 1198 * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
Pawel Zarembski 0:01f31e923fe2 1199 * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
Pawel Zarembski 0:01f31e923fe2 1200 * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
Pawel Zarembski 0:01f31e923fe2 1201 * been loaded into the eDMA engine at this point already.).
Pawel Zarembski 0:01f31e923fe2 1202 *
Pawel Zarembski 0:01f31e923fe2 1203 * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not
Pawel Zarembski 0:01f31e923fe2 1204 * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
Pawel Zarembski 0:01f31e923fe2 1205 * Therefore, ensure that the header and tcdUsed updated are identical for them.
Pawel Zarembski 0:01f31e923fe2 1206 * tcdUsed are both 0 in this case as no TCD to be loaded.
Pawel Zarembski 0:01f31e923fe2 1207 *
Pawel Zarembski 0:01f31e923fe2 1208 * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
Pawel Zarembski 0:01f31e923fe2 1209 * further details.
Pawel Zarembski 0:01f31e923fe2 1210 *
Pawel Zarembski 0:01f31e923fe2 1211 * param handle eDMA handle pointer.
Pawel Zarembski 0:01f31e923fe2 1212 */
Pawel Zarembski 0:01f31e923fe2 1213 void EDMA_HandleIRQ(edma_handle_t *handle)
Pawel Zarembski 0:01f31e923fe2 1214 {
Pawel Zarembski 0:01f31e923fe2 1215 assert(handle != NULL);
Pawel Zarembski 0:01f31e923fe2 1216
Pawel Zarembski 0:01f31e923fe2 1217 /* Clear EDMA interrupt flag */
Pawel Zarembski 0:01f31e923fe2 1218 handle->base->CINT = handle->channel;
Pawel Zarembski 0:01f31e923fe2 1219 if ((handle->tcdPool == NULL) && (handle->callback != NULL))
Pawel Zarembski 0:01f31e923fe2 1220 {
Pawel Zarembski 0:01f31e923fe2 1221 (handle->callback)(handle, handle->userData, true, 0);
Pawel Zarembski 0:01f31e923fe2 1222 }
Pawel Zarembski 0:01f31e923fe2 1223 else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
Pawel Zarembski 0:01f31e923fe2 1224 {
Pawel Zarembski 0:01f31e923fe2 1225 uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
Pawel Zarembski 0:01f31e923fe2 1226 uint32_t sga_index;
Pawel Zarembski 0:01f31e923fe2 1227 int32_t tcds_done;
Pawel Zarembski 0:01f31e923fe2 1228 uint8_t new_header;
Pawel Zarembski 0:01f31e923fe2 1229 bool transfer_done;
Pawel Zarembski 0:01f31e923fe2 1230
Pawel Zarembski 0:01f31e923fe2 1231 /* Check if transfer is already finished. */
Pawel Zarembski 0:01f31e923fe2 1232 transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
Pawel Zarembski 0:01f31e923fe2 1233 /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */
Pawel Zarembski 0:01f31e923fe2 1234 sga -= (uint32_t)handle->tcdPool;
Pawel Zarembski 0:01f31e923fe2 1235 /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */
Pawel Zarembski 0:01f31e923fe2 1236 sga_index = sga / sizeof(edma_tcd_t);
Pawel Zarembski 0:01f31e923fe2 1237 /* Adjust header positions. */
Pawel Zarembski 0:01f31e923fe2 1238 if (transfer_done)
Pawel Zarembski 0:01f31e923fe2 1239 {
Pawel Zarembski 0:01f31e923fe2 1240 /* New header shall point to the next TCD to be loaded (current one is already finished) */
Pawel Zarembski 0:01f31e923fe2 1241 new_header = sga_index;
Pawel Zarembski 0:01f31e923fe2 1242 }
Pawel Zarembski 0:01f31e923fe2 1243 else
Pawel Zarembski 0:01f31e923fe2 1244 {
Pawel Zarembski 0:01f31e923fe2 1245 /* New header shall point to this descriptor currently loaded (not finished yet) */
Pawel Zarembski 0:01f31e923fe2 1246 new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
Pawel Zarembski 0:01f31e923fe2 1247 }
Pawel Zarembski 0:01f31e923fe2 1248 /* Calculate the number of finished TCDs */
Pawel Zarembski 0:01f31e923fe2 1249 if (new_header == handle->header)
Pawel Zarembski 0:01f31e923fe2 1250 {
Pawel Zarembski 0:01f31e923fe2 1251 if (handle->tcdUsed == handle->tcdSize)
Pawel Zarembski 0:01f31e923fe2 1252 {
Pawel Zarembski 0:01f31e923fe2 1253 tcds_done = handle->tcdUsed;
Pawel Zarembski 0:01f31e923fe2 1254 }
Pawel Zarembski 0:01f31e923fe2 1255 else
Pawel Zarembski 0:01f31e923fe2 1256 {
Pawel Zarembski 0:01f31e923fe2 1257 /* No TCD in the memory are going to be loaded or internal error occurs. */
Pawel Zarembski 0:01f31e923fe2 1258 tcds_done = 0;
Pawel Zarembski 0:01f31e923fe2 1259 }
Pawel Zarembski 0:01f31e923fe2 1260 }
Pawel Zarembski 0:01f31e923fe2 1261 else
Pawel Zarembski 0:01f31e923fe2 1262 {
Pawel Zarembski 0:01f31e923fe2 1263 tcds_done = new_header - handle->header;
Pawel Zarembski 0:01f31e923fe2 1264 if (tcds_done < 0)
Pawel Zarembski 0:01f31e923fe2 1265 {
Pawel Zarembski 0:01f31e923fe2 1266 tcds_done += handle->tcdSize;
Pawel Zarembski 0:01f31e923fe2 1267 }
Pawel Zarembski 0:01f31e923fe2 1268 }
Pawel Zarembski 0:01f31e923fe2 1269 /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
Pawel Zarembski 0:01f31e923fe2 1270 handle->header = new_header;
Pawel Zarembski 0:01f31e923fe2 1271 /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
Pawel Zarembski 0:01f31e923fe2 1272 handle->tcdUsed -= tcds_done;
Pawel Zarembski 0:01f31e923fe2 1273 /* Invoke callback function. */
Pawel Zarembski 0:01f31e923fe2 1274 if (handle->callback)
Pawel Zarembski 0:01f31e923fe2 1275 {
Pawel Zarembski 0:01f31e923fe2 1276 (handle->callback)(handle, handle->userData, transfer_done, tcds_done);
Pawel Zarembski 0:01f31e923fe2 1277 }
Pawel Zarembski 0:01f31e923fe2 1278
Pawel Zarembski 0:01f31e923fe2 1279 /* clear the DONE bit here is meaningful for below cases:
Pawel Zarembski 0:01f31e923fe2 1280 *1.A new TCD has been loaded to EDMA already:
Pawel Zarembski 0:01f31e923fe2 1281 * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten
Pawel Zarembski 0:01f31e923fe2 1282 * if peripheral request isn't coming before next transfer request.
Pawel Zarembski 0:01f31e923fe2 1283 *2.A new TCD has not been loaded to EDMA:
Pawel Zarembski 0:01f31e923fe2 1284 * for the case that transfer request occur in the privious edma callback, this is a case that doesn't
Pawel Zarembski 0:01f31e923fe2 1285 * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD.
Pawel Zarembski 0:01f31e923fe2 1286 */
Pawel Zarembski 0:01f31e923fe2 1287 if (transfer_done)
Pawel Zarembski 0:01f31e923fe2 1288 {
Pawel Zarembski 0:01f31e923fe2 1289 handle->base->CDNE = handle->channel;
Pawel Zarembski 0:01f31e923fe2 1290 }
Pawel Zarembski 0:01f31e923fe2 1291 }
Pawel Zarembski 0:01f31e923fe2 1292 }
Pawel Zarembski 0:01f31e923fe2 1293
Pawel Zarembski 0:01f31e923fe2 1294 /* 8 channels (Shared): kl28 */
Pawel Zarembski 0:01f31e923fe2 1295 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
Pawel Zarembski 0:01f31e923fe2 1296
Pawel Zarembski 0:01f31e923fe2 1297 #if defined(DMA0)
Pawel Zarembski 0:01f31e923fe2 1298 void DMA0_04_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1299 {
Pawel Zarembski 0:01f31e923fe2 1300 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1301 {
Pawel Zarembski 0:01f31e923fe2 1302 EDMA_HandleIRQ(s_EDMAHandle[0]);
Pawel Zarembski 0:01f31e923fe2 1303 }
Pawel Zarembski 0:01f31e923fe2 1304 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1305 {
Pawel Zarembski 0:01f31e923fe2 1306 EDMA_HandleIRQ(s_EDMAHandle[4]);
Pawel Zarembski 0:01f31e923fe2 1307 }
Pawel Zarembski 0:01f31e923fe2 1308 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1309 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1310 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1311 __DSB();
Pawel Zarembski 0:01f31e923fe2 1312 #endif
Pawel Zarembski 0:01f31e923fe2 1313 }
Pawel Zarembski 0:01f31e923fe2 1314
Pawel Zarembski 0:01f31e923fe2 1315 void DMA0_15_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1316 {
Pawel Zarembski 0:01f31e923fe2 1317 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1318 {
Pawel Zarembski 0:01f31e923fe2 1319 EDMA_HandleIRQ(s_EDMAHandle[1]);
Pawel Zarembski 0:01f31e923fe2 1320 }
Pawel Zarembski 0:01f31e923fe2 1321 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1322 {
Pawel Zarembski 0:01f31e923fe2 1323 EDMA_HandleIRQ(s_EDMAHandle[5]);
Pawel Zarembski 0:01f31e923fe2 1324 }
Pawel Zarembski 0:01f31e923fe2 1325 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1326 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1327 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1328 __DSB();
Pawel Zarembski 0:01f31e923fe2 1329 #endif
Pawel Zarembski 0:01f31e923fe2 1330 }
Pawel Zarembski 0:01f31e923fe2 1331
Pawel Zarembski 0:01f31e923fe2 1332 void DMA0_26_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1333 {
Pawel Zarembski 0:01f31e923fe2 1334 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1335 {
Pawel Zarembski 0:01f31e923fe2 1336 EDMA_HandleIRQ(s_EDMAHandle[2]);
Pawel Zarembski 0:01f31e923fe2 1337 }
Pawel Zarembski 0:01f31e923fe2 1338 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1339 {
Pawel Zarembski 0:01f31e923fe2 1340 EDMA_HandleIRQ(s_EDMAHandle[6]);
Pawel Zarembski 0:01f31e923fe2 1341 }
Pawel Zarembski 0:01f31e923fe2 1342 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1343 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1344 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1345 __DSB();
Pawel Zarembski 0:01f31e923fe2 1346 #endif
Pawel Zarembski 0:01f31e923fe2 1347 }
Pawel Zarembski 0:01f31e923fe2 1348
Pawel Zarembski 0:01f31e923fe2 1349 void DMA0_37_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1350 {
Pawel Zarembski 0:01f31e923fe2 1351 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1352 {
Pawel Zarembski 0:01f31e923fe2 1353 EDMA_HandleIRQ(s_EDMAHandle[3]);
Pawel Zarembski 0:01f31e923fe2 1354 }
Pawel Zarembski 0:01f31e923fe2 1355 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1356 {
Pawel Zarembski 0:01f31e923fe2 1357 EDMA_HandleIRQ(s_EDMAHandle[7]);
Pawel Zarembski 0:01f31e923fe2 1358 }
Pawel Zarembski 0:01f31e923fe2 1359 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1360 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1361 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1362 __DSB();
Pawel Zarembski 0:01f31e923fe2 1363 #endif
Pawel Zarembski 0:01f31e923fe2 1364 }
Pawel Zarembski 0:01f31e923fe2 1365 #endif
Pawel Zarembski 0:01f31e923fe2 1366
Pawel Zarembski 0:01f31e923fe2 1367 #if defined(DMA1)
Pawel Zarembski 0:01f31e923fe2 1368
Pawel Zarembski 0:01f31e923fe2 1369 #if defined(DMA0)
Pawel Zarembski 0:01f31e923fe2 1370 void DMA1_04_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1371 {
Pawel Zarembski 0:01f31e923fe2 1372 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1373 {
Pawel Zarembski 0:01f31e923fe2 1374 EDMA_HandleIRQ(s_EDMAHandle[8]);
Pawel Zarembski 0:01f31e923fe2 1375 }
Pawel Zarembski 0:01f31e923fe2 1376 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1377 {
Pawel Zarembski 0:01f31e923fe2 1378 EDMA_HandleIRQ(s_EDMAHandle[12]);
Pawel Zarembski 0:01f31e923fe2 1379 }
Pawel Zarembski 0:01f31e923fe2 1380 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1381 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1382 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1383 __DSB();
Pawel Zarembski 0:01f31e923fe2 1384 #endif
Pawel Zarembski 0:01f31e923fe2 1385 }
Pawel Zarembski 0:01f31e923fe2 1386
Pawel Zarembski 0:01f31e923fe2 1387 void DMA1_15_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1388 {
Pawel Zarembski 0:01f31e923fe2 1389 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1390 {
Pawel Zarembski 0:01f31e923fe2 1391 EDMA_HandleIRQ(s_EDMAHandle[9]);
Pawel Zarembski 0:01f31e923fe2 1392 }
Pawel Zarembski 0:01f31e923fe2 1393 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1394 {
Pawel Zarembski 0:01f31e923fe2 1395 EDMA_HandleIRQ(s_EDMAHandle[13]);
Pawel Zarembski 0:01f31e923fe2 1396 }
Pawel Zarembski 0:01f31e923fe2 1397 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1398 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1399 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1400 __DSB();
Pawel Zarembski 0:01f31e923fe2 1401 #endif
Pawel Zarembski 0:01f31e923fe2 1402 }
Pawel Zarembski 0:01f31e923fe2 1403
Pawel Zarembski 0:01f31e923fe2 1404 void DMA1_26_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1405 {
Pawel Zarembski 0:01f31e923fe2 1406 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1407 {
Pawel Zarembski 0:01f31e923fe2 1408 EDMA_HandleIRQ(s_EDMAHandle[10]);
Pawel Zarembski 0:01f31e923fe2 1409 }
Pawel Zarembski 0:01f31e923fe2 1410 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1411 {
Pawel Zarembski 0:01f31e923fe2 1412 EDMA_HandleIRQ(s_EDMAHandle[14]);
Pawel Zarembski 0:01f31e923fe2 1413 }
Pawel Zarembski 0:01f31e923fe2 1414 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1415 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1416 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1417 __DSB();
Pawel Zarembski 0:01f31e923fe2 1418 #endif
Pawel Zarembski 0:01f31e923fe2 1419 }
Pawel Zarembski 0:01f31e923fe2 1420
Pawel Zarembski 0:01f31e923fe2 1421 void DMA1_37_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1422 {
Pawel Zarembski 0:01f31e923fe2 1423 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1424 {
Pawel Zarembski 0:01f31e923fe2 1425 EDMA_HandleIRQ(s_EDMAHandle[11]);
Pawel Zarembski 0:01f31e923fe2 1426 }
Pawel Zarembski 0:01f31e923fe2 1427 if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1428 {
Pawel Zarembski 0:01f31e923fe2 1429 EDMA_HandleIRQ(s_EDMAHandle[15]);
Pawel Zarembski 0:01f31e923fe2 1430 }
Pawel Zarembski 0:01f31e923fe2 1431 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1432 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1433 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1434 __DSB();
Pawel Zarembski 0:01f31e923fe2 1435 #endif
Pawel Zarembski 0:01f31e923fe2 1436 }
Pawel Zarembski 0:01f31e923fe2 1437
Pawel Zarembski 0:01f31e923fe2 1438 #else
Pawel Zarembski 0:01f31e923fe2 1439 void DMA1_04_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1440 {
Pawel Zarembski 0:01f31e923fe2 1441 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1442 {
Pawel Zarembski 0:01f31e923fe2 1443 EDMA_HandleIRQ(s_EDMAHandle[0]);
Pawel Zarembski 0:01f31e923fe2 1444 }
Pawel Zarembski 0:01f31e923fe2 1445 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1446 {
Pawel Zarembski 0:01f31e923fe2 1447 EDMA_HandleIRQ(s_EDMAHandle[4]);
Pawel Zarembski 0:01f31e923fe2 1448 }
Pawel Zarembski 0:01f31e923fe2 1449 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1450 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1451 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1452 __DSB();
Pawel Zarembski 0:01f31e923fe2 1453 #endif
Pawel Zarembski 0:01f31e923fe2 1454 }
Pawel Zarembski 0:01f31e923fe2 1455
Pawel Zarembski 0:01f31e923fe2 1456 void DMA1_15_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1457 {
Pawel Zarembski 0:01f31e923fe2 1458 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1459 {
Pawel Zarembski 0:01f31e923fe2 1460 EDMA_HandleIRQ(s_EDMAHandle[1]);
Pawel Zarembski 0:01f31e923fe2 1461 }
Pawel Zarembski 0:01f31e923fe2 1462 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1463 {
Pawel Zarembski 0:01f31e923fe2 1464 EDMA_HandleIRQ(s_EDMAHandle[5]);
Pawel Zarembski 0:01f31e923fe2 1465 }
Pawel Zarembski 0:01f31e923fe2 1466 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1467 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1468 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1469 __DSB();
Pawel Zarembski 0:01f31e923fe2 1470 #endif
Pawel Zarembski 0:01f31e923fe2 1471 }
Pawel Zarembski 0:01f31e923fe2 1472
Pawel Zarembski 0:01f31e923fe2 1473 void DMA1_26_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1474 {
Pawel Zarembski 0:01f31e923fe2 1475 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1476 {
Pawel Zarembski 0:01f31e923fe2 1477 EDMA_HandleIRQ(s_EDMAHandle[2]);
Pawel Zarembski 0:01f31e923fe2 1478 }
Pawel Zarembski 0:01f31e923fe2 1479 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1480 {
Pawel Zarembski 0:01f31e923fe2 1481 EDMA_HandleIRQ(s_EDMAHandle[6]);
Pawel Zarembski 0:01f31e923fe2 1482 }
Pawel Zarembski 0:01f31e923fe2 1483 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1484 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1485 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1486 __DSB();
Pawel Zarembski 0:01f31e923fe2 1487 #endif
Pawel Zarembski 0:01f31e923fe2 1488 }
Pawel Zarembski 0:01f31e923fe2 1489
Pawel Zarembski 0:01f31e923fe2 1490 void DMA1_37_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1491 {
Pawel Zarembski 0:01f31e923fe2 1492 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1493 {
Pawel Zarembski 0:01f31e923fe2 1494 EDMA_HandleIRQ(s_EDMAHandle[3]);
Pawel Zarembski 0:01f31e923fe2 1495 }
Pawel Zarembski 0:01f31e923fe2 1496 if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1497 {
Pawel Zarembski 0:01f31e923fe2 1498 EDMA_HandleIRQ(s_EDMAHandle[7]);
Pawel Zarembski 0:01f31e923fe2 1499 }
Pawel Zarembski 0:01f31e923fe2 1500 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1501 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1502 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1503 __DSB();
Pawel Zarembski 0:01f31e923fe2 1504 #endif
Pawel Zarembski 0:01f31e923fe2 1505 }
Pawel Zarembski 0:01f31e923fe2 1506 #endif
Pawel Zarembski 0:01f31e923fe2 1507 #endif
Pawel Zarembski 0:01f31e923fe2 1508 #endif /* 8 channels (Shared) */
Pawel Zarembski 0:01f31e923fe2 1509
Pawel Zarembski 0:01f31e923fe2 1510 /* 16 channels (Shared): K32H844P */
Pawel Zarembski 0:01f31e923fe2 1511 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
Pawel Zarembski 0:01f31e923fe2 1512
Pawel Zarembski 0:01f31e923fe2 1513 void DMA0_08_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1514 {
Pawel Zarembski 0:01f31e923fe2 1515 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1516 {
Pawel Zarembski 0:01f31e923fe2 1517 EDMA_HandleIRQ(s_EDMAHandle[0]);
Pawel Zarembski 0:01f31e923fe2 1518 }
Pawel Zarembski 0:01f31e923fe2 1519 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1520 {
Pawel Zarembski 0:01f31e923fe2 1521 EDMA_HandleIRQ(s_EDMAHandle[8]);
Pawel Zarembski 0:01f31e923fe2 1522 }
Pawel Zarembski 0:01f31e923fe2 1523 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1524 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1525 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1526 __DSB();
Pawel Zarembski 0:01f31e923fe2 1527 #endif
Pawel Zarembski 0:01f31e923fe2 1528 }
Pawel Zarembski 0:01f31e923fe2 1529
Pawel Zarembski 0:01f31e923fe2 1530 void DMA0_19_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1531 {
Pawel Zarembski 0:01f31e923fe2 1532 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1533 {
Pawel Zarembski 0:01f31e923fe2 1534 EDMA_HandleIRQ(s_EDMAHandle[1]);
Pawel Zarembski 0:01f31e923fe2 1535 }
Pawel Zarembski 0:01f31e923fe2 1536 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1537 {
Pawel Zarembski 0:01f31e923fe2 1538 EDMA_HandleIRQ(s_EDMAHandle[9]);
Pawel Zarembski 0:01f31e923fe2 1539 }
Pawel Zarembski 0:01f31e923fe2 1540 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1541 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1542 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1543 __DSB();
Pawel Zarembski 0:01f31e923fe2 1544 #endif
Pawel Zarembski 0:01f31e923fe2 1545 }
Pawel Zarembski 0:01f31e923fe2 1546
Pawel Zarembski 0:01f31e923fe2 1547 void DMA0_210_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1548 {
Pawel Zarembski 0:01f31e923fe2 1549 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1550 {
Pawel Zarembski 0:01f31e923fe2 1551 EDMA_HandleIRQ(s_EDMAHandle[2]);
Pawel Zarembski 0:01f31e923fe2 1552 }
Pawel Zarembski 0:01f31e923fe2 1553 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1554 {
Pawel Zarembski 0:01f31e923fe2 1555 EDMA_HandleIRQ(s_EDMAHandle[10]);
Pawel Zarembski 0:01f31e923fe2 1556 }
Pawel Zarembski 0:01f31e923fe2 1557 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1558 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1559 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1560 __DSB();
Pawel Zarembski 0:01f31e923fe2 1561 #endif
Pawel Zarembski 0:01f31e923fe2 1562 }
Pawel Zarembski 0:01f31e923fe2 1563
Pawel Zarembski 0:01f31e923fe2 1564 void DMA0_311_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1565 {
Pawel Zarembski 0:01f31e923fe2 1566 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1567 {
Pawel Zarembski 0:01f31e923fe2 1568 EDMA_HandleIRQ(s_EDMAHandle[3]);
Pawel Zarembski 0:01f31e923fe2 1569 }
Pawel Zarembski 0:01f31e923fe2 1570 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1571 {
Pawel Zarembski 0:01f31e923fe2 1572 EDMA_HandleIRQ(s_EDMAHandle[11]);
Pawel Zarembski 0:01f31e923fe2 1573 }
Pawel Zarembski 0:01f31e923fe2 1574 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1575 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1576 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1577 __DSB();
Pawel Zarembski 0:01f31e923fe2 1578 #endif
Pawel Zarembski 0:01f31e923fe2 1579 }
Pawel Zarembski 0:01f31e923fe2 1580
Pawel Zarembski 0:01f31e923fe2 1581 void DMA0_412_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1582 {
Pawel Zarembski 0:01f31e923fe2 1583 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1584 {
Pawel Zarembski 0:01f31e923fe2 1585 EDMA_HandleIRQ(s_EDMAHandle[4]);
Pawel Zarembski 0:01f31e923fe2 1586 }
Pawel Zarembski 0:01f31e923fe2 1587 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1588 {
Pawel Zarembski 0:01f31e923fe2 1589 EDMA_HandleIRQ(s_EDMAHandle[12]);
Pawel Zarembski 0:01f31e923fe2 1590 }
Pawel Zarembski 0:01f31e923fe2 1591 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1592 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1593 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1594 __DSB();
Pawel Zarembski 0:01f31e923fe2 1595 #endif
Pawel Zarembski 0:01f31e923fe2 1596 }
Pawel Zarembski 0:01f31e923fe2 1597
Pawel Zarembski 0:01f31e923fe2 1598 void DMA0_513_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1599 {
Pawel Zarembski 0:01f31e923fe2 1600 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1601 {
Pawel Zarembski 0:01f31e923fe2 1602 EDMA_HandleIRQ(s_EDMAHandle[5]);
Pawel Zarembski 0:01f31e923fe2 1603 }
Pawel Zarembski 0:01f31e923fe2 1604 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1605 {
Pawel Zarembski 0:01f31e923fe2 1606 EDMA_HandleIRQ(s_EDMAHandle[13]);
Pawel Zarembski 0:01f31e923fe2 1607 }
Pawel Zarembski 0:01f31e923fe2 1608 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1609 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1610 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1611 __DSB();
Pawel Zarembski 0:01f31e923fe2 1612 #endif
Pawel Zarembski 0:01f31e923fe2 1613 }
Pawel Zarembski 0:01f31e923fe2 1614
Pawel Zarembski 0:01f31e923fe2 1615 void DMA0_614_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1616 {
Pawel Zarembski 0:01f31e923fe2 1617 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1618 {
Pawel Zarembski 0:01f31e923fe2 1619 EDMA_HandleIRQ(s_EDMAHandle[6]);
Pawel Zarembski 0:01f31e923fe2 1620 }
Pawel Zarembski 0:01f31e923fe2 1621 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1622 {
Pawel Zarembski 0:01f31e923fe2 1623 EDMA_HandleIRQ(s_EDMAHandle[14]);
Pawel Zarembski 0:01f31e923fe2 1624 }
Pawel Zarembski 0:01f31e923fe2 1625 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1626 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1627 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1628 __DSB();
Pawel Zarembski 0:01f31e923fe2 1629 #endif
Pawel Zarembski 0:01f31e923fe2 1630 }
Pawel Zarembski 0:01f31e923fe2 1631
Pawel Zarembski 0:01f31e923fe2 1632 void DMA0_715_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1633 {
Pawel Zarembski 0:01f31e923fe2 1634 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1635 {
Pawel Zarembski 0:01f31e923fe2 1636 EDMA_HandleIRQ(s_EDMAHandle[7]);
Pawel Zarembski 0:01f31e923fe2 1637 }
Pawel Zarembski 0:01f31e923fe2 1638 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1639 {
Pawel Zarembski 0:01f31e923fe2 1640 EDMA_HandleIRQ(s_EDMAHandle[15]);
Pawel Zarembski 0:01f31e923fe2 1641 }
Pawel Zarembski 0:01f31e923fe2 1642 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1643 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1644 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1645 __DSB();
Pawel Zarembski 0:01f31e923fe2 1646 #endif
Pawel Zarembski 0:01f31e923fe2 1647 }
Pawel Zarembski 0:01f31e923fe2 1648
Pawel Zarembski 0:01f31e923fe2 1649 #if defined(DMA1)
Pawel Zarembski 0:01f31e923fe2 1650 void DMA1_08_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1651 {
Pawel Zarembski 0:01f31e923fe2 1652 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1653 {
Pawel Zarembski 0:01f31e923fe2 1654 EDMA_HandleIRQ(s_EDMAHandle[16]);
Pawel Zarembski 0:01f31e923fe2 1655 }
Pawel Zarembski 0:01f31e923fe2 1656 if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1657 {
Pawel Zarembski 0:01f31e923fe2 1658 EDMA_HandleIRQ(s_EDMAHandle[24]);
Pawel Zarembski 0:01f31e923fe2 1659 }
Pawel Zarembski 0:01f31e923fe2 1660 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1661 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1662 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1663 __DSB();
Pawel Zarembski 0:01f31e923fe2 1664 #endif
Pawel Zarembski 0:01f31e923fe2 1665 }
Pawel Zarembski 0:01f31e923fe2 1666
Pawel Zarembski 0:01f31e923fe2 1667 void DMA1_19_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1668 {
Pawel Zarembski 0:01f31e923fe2 1669 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1670 {
Pawel Zarembski 0:01f31e923fe2 1671 EDMA_HandleIRQ(s_EDMAHandle[17]);
Pawel Zarembski 0:01f31e923fe2 1672 }
Pawel Zarembski 0:01f31e923fe2 1673 if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1674 {
Pawel Zarembski 0:01f31e923fe2 1675 EDMA_HandleIRQ(s_EDMAHandle[25]);
Pawel Zarembski 0:01f31e923fe2 1676 }
Pawel Zarembski 0:01f31e923fe2 1677 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1678 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1679 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1680 __DSB();
Pawel Zarembski 0:01f31e923fe2 1681 #endif
Pawel Zarembski 0:01f31e923fe2 1682 }
Pawel Zarembski 0:01f31e923fe2 1683
Pawel Zarembski 0:01f31e923fe2 1684 void DMA1_210_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1685 {
Pawel Zarembski 0:01f31e923fe2 1686 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1687 {
Pawel Zarembski 0:01f31e923fe2 1688 EDMA_HandleIRQ(s_EDMAHandle[18]);
Pawel Zarembski 0:01f31e923fe2 1689 }
Pawel Zarembski 0:01f31e923fe2 1690 if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1691 {
Pawel Zarembski 0:01f31e923fe2 1692 EDMA_HandleIRQ(s_EDMAHandle[26]);
Pawel Zarembski 0:01f31e923fe2 1693 }
Pawel Zarembski 0:01f31e923fe2 1694 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1695 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1696 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1697 __DSB();
Pawel Zarembski 0:01f31e923fe2 1698 #endif
Pawel Zarembski 0:01f31e923fe2 1699 }
Pawel Zarembski 0:01f31e923fe2 1700
Pawel Zarembski 0:01f31e923fe2 1701 void DMA1_311_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1702 {
Pawel Zarembski 0:01f31e923fe2 1703 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1704 {
Pawel Zarembski 0:01f31e923fe2 1705 EDMA_HandleIRQ(s_EDMAHandle[19]);
Pawel Zarembski 0:01f31e923fe2 1706 }
Pawel Zarembski 0:01f31e923fe2 1707 if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1708 {
Pawel Zarembski 0:01f31e923fe2 1709 EDMA_HandleIRQ(s_EDMAHandle[27]);
Pawel Zarembski 0:01f31e923fe2 1710 }
Pawel Zarembski 0:01f31e923fe2 1711 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1712 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1713 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1714 __DSB();
Pawel Zarembski 0:01f31e923fe2 1715 #endif
Pawel Zarembski 0:01f31e923fe2 1716 }
Pawel Zarembski 0:01f31e923fe2 1717
Pawel Zarembski 0:01f31e923fe2 1718 void DMA1_412_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1719 {
Pawel Zarembski 0:01f31e923fe2 1720 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1721 {
Pawel Zarembski 0:01f31e923fe2 1722 EDMA_HandleIRQ(s_EDMAHandle[20]);
Pawel Zarembski 0:01f31e923fe2 1723 }
Pawel Zarembski 0:01f31e923fe2 1724 if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1725 {
Pawel Zarembski 0:01f31e923fe2 1726 EDMA_HandleIRQ(s_EDMAHandle[28]);
Pawel Zarembski 0:01f31e923fe2 1727 }
Pawel Zarembski 0:01f31e923fe2 1728 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1729 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1730 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1731 __DSB();
Pawel Zarembski 0:01f31e923fe2 1732 #endif
Pawel Zarembski 0:01f31e923fe2 1733 }
Pawel Zarembski 0:01f31e923fe2 1734
Pawel Zarembski 0:01f31e923fe2 1735 void DMA1_513_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1736 {
Pawel Zarembski 0:01f31e923fe2 1737 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1738 {
Pawel Zarembski 0:01f31e923fe2 1739 EDMA_HandleIRQ(s_EDMAHandle[21]);
Pawel Zarembski 0:01f31e923fe2 1740 }
Pawel Zarembski 0:01f31e923fe2 1741 if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1742 {
Pawel Zarembski 0:01f31e923fe2 1743 EDMA_HandleIRQ(s_EDMAHandle[29]);
Pawel Zarembski 0:01f31e923fe2 1744 }
Pawel Zarembski 0:01f31e923fe2 1745 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1746 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1747 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1748 __DSB();
Pawel Zarembski 0:01f31e923fe2 1749 #endif
Pawel Zarembski 0:01f31e923fe2 1750 }
Pawel Zarembski 0:01f31e923fe2 1751
Pawel Zarembski 0:01f31e923fe2 1752 void DMA1_614_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1753 {
Pawel Zarembski 0:01f31e923fe2 1754 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1755 {
Pawel Zarembski 0:01f31e923fe2 1756 EDMA_HandleIRQ(s_EDMAHandle[22]);
Pawel Zarembski 0:01f31e923fe2 1757 }
Pawel Zarembski 0:01f31e923fe2 1758 if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1759 {
Pawel Zarembski 0:01f31e923fe2 1760 EDMA_HandleIRQ(s_EDMAHandle[30]);
Pawel Zarembski 0:01f31e923fe2 1761 }
Pawel Zarembski 0:01f31e923fe2 1762 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1763 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1764 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1765 __DSB();
Pawel Zarembski 0:01f31e923fe2 1766 #endif
Pawel Zarembski 0:01f31e923fe2 1767 }
Pawel Zarembski 0:01f31e923fe2 1768
Pawel Zarembski 0:01f31e923fe2 1769 void DMA1_715_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1770 {
Pawel Zarembski 0:01f31e923fe2 1771 if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1772 {
Pawel Zarembski 0:01f31e923fe2 1773 EDMA_HandleIRQ(s_EDMAHandle[23]);
Pawel Zarembski 0:01f31e923fe2 1774 }
Pawel Zarembski 0:01f31e923fe2 1775 if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1776 {
Pawel Zarembski 0:01f31e923fe2 1777 EDMA_HandleIRQ(s_EDMAHandle[31]);
Pawel Zarembski 0:01f31e923fe2 1778 }
Pawel Zarembski 0:01f31e923fe2 1779 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1780 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1781 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1782 __DSB();
Pawel Zarembski 0:01f31e923fe2 1783 #endif
Pawel Zarembski 0:01f31e923fe2 1784 }
Pawel Zarembski 0:01f31e923fe2 1785 #endif
Pawel Zarembski 0:01f31e923fe2 1786 #endif /* 16 channels (Shared) */
Pawel Zarembski 0:01f31e923fe2 1787
Pawel Zarembski 0:01f31e923fe2 1788 /* 32 channels (Shared): k80 */
Pawel Zarembski 0:01f31e923fe2 1789 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
Pawel Zarembski 0:01f31e923fe2 1790
Pawel Zarembski 0:01f31e923fe2 1791 void DMA0_DMA16_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1792 {
Pawel Zarembski 0:01f31e923fe2 1793 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1794 {
Pawel Zarembski 0:01f31e923fe2 1795 EDMA_HandleIRQ(s_EDMAHandle[0]);
Pawel Zarembski 0:01f31e923fe2 1796 }
Pawel Zarembski 0:01f31e923fe2 1797 if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1798 {
Pawel Zarembski 0:01f31e923fe2 1799 EDMA_HandleIRQ(s_EDMAHandle[16]);
Pawel Zarembski 0:01f31e923fe2 1800 }
Pawel Zarembski 0:01f31e923fe2 1801 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1802 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1803 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1804 __DSB();
Pawel Zarembski 0:01f31e923fe2 1805 #endif
Pawel Zarembski 0:01f31e923fe2 1806 }
Pawel Zarembski 0:01f31e923fe2 1807
Pawel Zarembski 0:01f31e923fe2 1808 void DMA1_DMA17_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1809 {
Pawel Zarembski 0:01f31e923fe2 1810 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1811 {
Pawel Zarembski 0:01f31e923fe2 1812 EDMA_HandleIRQ(s_EDMAHandle[1]);
Pawel Zarembski 0:01f31e923fe2 1813 }
Pawel Zarembski 0:01f31e923fe2 1814 if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1815 {
Pawel Zarembski 0:01f31e923fe2 1816 EDMA_HandleIRQ(s_EDMAHandle[17]);
Pawel Zarembski 0:01f31e923fe2 1817 }
Pawel Zarembski 0:01f31e923fe2 1818 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1819 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1820 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1821 __DSB();
Pawel Zarembski 0:01f31e923fe2 1822 #endif
Pawel Zarembski 0:01f31e923fe2 1823 }
Pawel Zarembski 0:01f31e923fe2 1824
Pawel Zarembski 0:01f31e923fe2 1825 void DMA2_DMA18_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1826 {
Pawel Zarembski 0:01f31e923fe2 1827 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1828 {
Pawel Zarembski 0:01f31e923fe2 1829 EDMA_HandleIRQ(s_EDMAHandle[2]);
Pawel Zarembski 0:01f31e923fe2 1830 }
Pawel Zarembski 0:01f31e923fe2 1831 if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1832 {
Pawel Zarembski 0:01f31e923fe2 1833 EDMA_HandleIRQ(s_EDMAHandle[18]);
Pawel Zarembski 0:01f31e923fe2 1834 }
Pawel Zarembski 0:01f31e923fe2 1835 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1836 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1837 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1838 __DSB();
Pawel Zarembski 0:01f31e923fe2 1839 #endif
Pawel Zarembski 0:01f31e923fe2 1840 }
Pawel Zarembski 0:01f31e923fe2 1841
Pawel Zarembski 0:01f31e923fe2 1842 void DMA3_DMA19_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1843 {
Pawel Zarembski 0:01f31e923fe2 1844 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1845 {
Pawel Zarembski 0:01f31e923fe2 1846 EDMA_HandleIRQ(s_EDMAHandle[3]);
Pawel Zarembski 0:01f31e923fe2 1847 }
Pawel Zarembski 0:01f31e923fe2 1848 if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1849 {
Pawel Zarembski 0:01f31e923fe2 1850 EDMA_HandleIRQ(s_EDMAHandle[19]);
Pawel Zarembski 0:01f31e923fe2 1851 }
Pawel Zarembski 0:01f31e923fe2 1852 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1853 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1854 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1855 __DSB();
Pawel Zarembski 0:01f31e923fe2 1856 #endif
Pawel Zarembski 0:01f31e923fe2 1857 }
Pawel Zarembski 0:01f31e923fe2 1858
Pawel Zarembski 0:01f31e923fe2 1859 void DMA4_DMA20_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1860 {
Pawel Zarembski 0:01f31e923fe2 1861 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1862 {
Pawel Zarembski 0:01f31e923fe2 1863 EDMA_HandleIRQ(s_EDMAHandle[4]);
Pawel Zarembski 0:01f31e923fe2 1864 }
Pawel Zarembski 0:01f31e923fe2 1865 if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1866 {
Pawel Zarembski 0:01f31e923fe2 1867 EDMA_HandleIRQ(s_EDMAHandle[20]);
Pawel Zarembski 0:01f31e923fe2 1868 }
Pawel Zarembski 0:01f31e923fe2 1869 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1870 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1871 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1872 __DSB();
Pawel Zarembski 0:01f31e923fe2 1873 #endif
Pawel Zarembski 0:01f31e923fe2 1874 }
Pawel Zarembski 0:01f31e923fe2 1875
Pawel Zarembski 0:01f31e923fe2 1876 void DMA5_DMA21_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1877 {
Pawel Zarembski 0:01f31e923fe2 1878 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1879 {
Pawel Zarembski 0:01f31e923fe2 1880 EDMA_HandleIRQ(s_EDMAHandle[5]);
Pawel Zarembski 0:01f31e923fe2 1881 }
Pawel Zarembski 0:01f31e923fe2 1882 if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1883 {
Pawel Zarembski 0:01f31e923fe2 1884 EDMA_HandleIRQ(s_EDMAHandle[21]);
Pawel Zarembski 0:01f31e923fe2 1885 }
Pawel Zarembski 0:01f31e923fe2 1886 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1887 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1888 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1889 __DSB();
Pawel Zarembski 0:01f31e923fe2 1890 #endif
Pawel Zarembski 0:01f31e923fe2 1891 }
Pawel Zarembski 0:01f31e923fe2 1892
Pawel Zarembski 0:01f31e923fe2 1893 void DMA6_DMA22_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1894 {
Pawel Zarembski 0:01f31e923fe2 1895 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1896 {
Pawel Zarembski 0:01f31e923fe2 1897 EDMA_HandleIRQ(s_EDMAHandle[6]);
Pawel Zarembski 0:01f31e923fe2 1898 }
Pawel Zarembski 0:01f31e923fe2 1899 if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1900 {
Pawel Zarembski 0:01f31e923fe2 1901 EDMA_HandleIRQ(s_EDMAHandle[22]);
Pawel Zarembski 0:01f31e923fe2 1902 }
Pawel Zarembski 0:01f31e923fe2 1903 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1904 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1905 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1906 __DSB();
Pawel Zarembski 0:01f31e923fe2 1907 #endif
Pawel Zarembski 0:01f31e923fe2 1908 }
Pawel Zarembski 0:01f31e923fe2 1909
Pawel Zarembski 0:01f31e923fe2 1910 void DMA7_DMA23_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1911 {
Pawel Zarembski 0:01f31e923fe2 1912 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1913 {
Pawel Zarembski 0:01f31e923fe2 1914 EDMA_HandleIRQ(s_EDMAHandle[7]);
Pawel Zarembski 0:01f31e923fe2 1915 }
Pawel Zarembski 0:01f31e923fe2 1916 if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1917 {
Pawel Zarembski 0:01f31e923fe2 1918 EDMA_HandleIRQ(s_EDMAHandle[23]);
Pawel Zarembski 0:01f31e923fe2 1919 }
Pawel Zarembski 0:01f31e923fe2 1920 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1921 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1922 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1923 __DSB();
Pawel Zarembski 0:01f31e923fe2 1924 #endif
Pawel Zarembski 0:01f31e923fe2 1925 }
Pawel Zarembski 0:01f31e923fe2 1926
Pawel Zarembski 0:01f31e923fe2 1927 void DMA8_DMA24_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1928 {
Pawel Zarembski 0:01f31e923fe2 1929 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1930 {
Pawel Zarembski 0:01f31e923fe2 1931 EDMA_HandleIRQ(s_EDMAHandle[8]);
Pawel Zarembski 0:01f31e923fe2 1932 }
Pawel Zarembski 0:01f31e923fe2 1933 if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1934 {
Pawel Zarembski 0:01f31e923fe2 1935 EDMA_HandleIRQ(s_EDMAHandle[24]);
Pawel Zarembski 0:01f31e923fe2 1936 }
Pawel Zarembski 0:01f31e923fe2 1937 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1938 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1939 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1940 __DSB();
Pawel Zarembski 0:01f31e923fe2 1941 #endif
Pawel Zarembski 0:01f31e923fe2 1942 }
Pawel Zarembski 0:01f31e923fe2 1943
Pawel Zarembski 0:01f31e923fe2 1944 void DMA9_DMA25_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1945 {
Pawel Zarembski 0:01f31e923fe2 1946 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1947 {
Pawel Zarembski 0:01f31e923fe2 1948 EDMA_HandleIRQ(s_EDMAHandle[9]);
Pawel Zarembski 0:01f31e923fe2 1949 }
Pawel Zarembski 0:01f31e923fe2 1950 if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1951 {
Pawel Zarembski 0:01f31e923fe2 1952 EDMA_HandleIRQ(s_EDMAHandle[25]);
Pawel Zarembski 0:01f31e923fe2 1953 }
Pawel Zarembski 0:01f31e923fe2 1954 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1955 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1956 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1957 __DSB();
Pawel Zarembski 0:01f31e923fe2 1958 #endif
Pawel Zarembski 0:01f31e923fe2 1959 }
Pawel Zarembski 0:01f31e923fe2 1960
Pawel Zarembski 0:01f31e923fe2 1961 void DMA10_DMA26_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1962 {
Pawel Zarembski 0:01f31e923fe2 1963 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1964 {
Pawel Zarembski 0:01f31e923fe2 1965 EDMA_HandleIRQ(s_EDMAHandle[10]);
Pawel Zarembski 0:01f31e923fe2 1966 }
Pawel Zarembski 0:01f31e923fe2 1967 if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1968 {
Pawel Zarembski 0:01f31e923fe2 1969 EDMA_HandleIRQ(s_EDMAHandle[26]);
Pawel Zarembski 0:01f31e923fe2 1970 }
Pawel Zarembski 0:01f31e923fe2 1971 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1972 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1973 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1974 __DSB();
Pawel Zarembski 0:01f31e923fe2 1975 #endif
Pawel Zarembski 0:01f31e923fe2 1976 }
Pawel Zarembski 0:01f31e923fe2 1977
Pawel Zarembski 0:01f31e923fe2 1978 void DMA11_DMA27_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1979 {
Pawel Zarembski 0:01f31e923fe2 1980 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1981 {
Pawel Zarembski 0:01f31e923fe2 1982 EDMA_HandleIRQ(s_EDMAHandle[11]);
Pawel Zarembski 0:01f31e923fe2 1983 }
Pawel Zarembski 0:01f31e923fe2 1984 if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1985 {
Pawel Zarembski 0:01f31e923fe2 1986 EDMA_HandleIRQ(s_EDMAHandle[27]);
Pawel Zarembski 0:01f31e923fe2 1987 }
Pawel Zarembski 0:01f31e923fe2 1988 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 1989 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 1990 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 1991 __DSB();
Pawel Zarembski 0:01f31e923fe2 1992 #endif
Pawel Zarembski 0:01f31e923fe2 1993 }
Pawel Zarembski 0:01f31e923fe2 1994
Pawel Zarembski 0:01f31e923fe2 1995 void DMA12_DMA28_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 1996 {
Pawel Zarembski 0:01f31e923fe2 1997 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 1998 {
Pawel Zarembski 0:01f31e923fe2 1999 EDMA_HandleIRQ(s_EDMAHandle[12]);
Pawel Zarembski 0:01f31e923fe2 2000 }
Pawel Zarembski 0:01f31e923fe2 2001 if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2002 {
Pawel Zarembski 0:01f31e923fe2 2003 EDMA_HandleIRQ(s_EDMAHandle[28]);
Pawel Zarembski 0:01f31e923fe2 2004 }
Pawel Zarembski 0:01f31e923fe2 2005 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2006 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2007 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2008 __DSB();
Pawel Zarembski 0:01f31e923fe2 2009 #endif
Pawel Zarembski 0:01f31e923fe2 2010 }
Pawel Zarembski 0:01f31e923fe2 2011
Pawel Zarembski 0:01f31e923fe2 2012 void DMA13_DMA29_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2013 {
Pawel Zarembski 0:01f31e923fe2 2014 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2015 {
Pawel Zarembski 0:01f31e923fe2 2016 EDMA_HandleIRQ(s_EDMAHandle[13]);
Pawel Zarembski 0:01f31e923fe2 2017 }
Pawel Zarembski 0:01f31e923fe2 2018 if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2019 {
Pawel Zarembski 0:01f31e923fe2 2020 EDMA_HandleIRQ(s_EDMAHandle[29]);
Pawel Zarembski 0:01f31e923fe2 2021 }
Pawel Zarembski 0:01f31e923fe2 2022 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2023 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2024 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2025 __DSB();
Pawel Zarembski 0:01f31e923fe2 2026 #endif
Pawel Zarembski 0:01f31e923fe2 2027 }
Pawel Zarembski 0:01f31e923fe2 2028
Pawel Zarembski 0:01f31e923fe2 2029 void DMA14_DMA30_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2030 {
Pawel Zarembski 0:01f31e923fe2 2031 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2032 {
Pawel Zarembski 0:01f31e923fe2 2033 EDMA_HandleIRQ(s_EDMAHandle[14]);
Pawel Zarembski 0:01f31e923fe2 2034 }
Pawel Zarembski 0:01f31e923fe2 2035 if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2036 {
Pawel Zarembski 0:01f31e923fe2 2037 EDMA_HandleIRQ(s_EDMAHandle[30]);
Pawel Zarembski 0:01f31e923fe2 2038 }
Pawel Zarembski 0:01f31e923fe2 2039 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2040 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2041 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2042 __DSB();
Pawel Zarembski 0:01f31e923fe2 2043 #endif
Pawel Zarembski 0:01f31e923fe2 2044 }
Pawel Zarembski 0:01f31e923fe2 2045
Pawel Zarembski 0:01f31e923fe2 2046 void DMA15_DMA31_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2047 {
Pawel Zarembski 0:01f31e923fe2 2048 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2049 {
Pawel Zarembski 0:01f31e923fe2 2050 EDMA_HandleIRQ(s_EDMAHandle[15]);
Pawel Zarembski 0:01f31e923fe2 2051 }
Pawel Zarembski 0:01f31e923fe2 2052 if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2053 {
Pawel Zarembski 0:01f31e923fe2 2054 EDMA_HandleIRQ(s_EDMAHandle[31]);
Pawel Zarembski 0:01f31e923fe2 2055 }
Pawel Zarembski 0:01f31e923fe2 2056 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2057 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2058 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2059 __DSB();
Pawel Zarembski 0:01f31e923fe2 2060 #endif
Pawel Zarembski 0:01f31e923fe2 2061 }
Pawel Zarembski 0:01f31e923fe2 2062 #endif /* 32 channels (Shared) */
Pawel Zarembski 0:01f31e923fe2 2063
Pawel Zarembski 0:01f31e923fe2 2064 /* 32 channels (Shared): MCIMX7U5_M4 */
Pawel Zarembski 0:01f31e923fe2 2065 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
Pawel Zarembski 0:01f31e923fe2 2066
Pawel Zarembski 0:01f31e923fe2 2067 void DMA0_0_4_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2068 {
Pawel Zarembski 0:01f31e923fe2 2069 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2070 {
Pawel Zarembski 0:01f31e923fe2 2071 EDMA_HandleIRQ(s_EDMAHandle[0]);
Pawel Zarembski 0:01f31e923fe2 2072 }
Pawel Zarembski 0:01f31e923fe2 2073 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2074 {
Pawel Zarembski 0:01f31e923fe2 2075 EDMA_HandleIRQ(s_EDMAHandle[4]);
Pawel Zarembski 0:01f31e923fe2 2076 }
Pawel Zarembski 0:01f31e923fe2 2077 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2078 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2079 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2080 __DSB();
Pawel Zarembski 0:01f31e923fe2 2081 #endif
Pawel Zarembski 0:01f31e923fe2 2082 }
Pawel Zarembski 0:01f31e923fe2 2083
Pawel Zarembski 0:01f31e923fe2 2084 void DMA0_1_5_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2085 {
Pawel Zarembski 0:01f31e923fe2 2086 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2087 {
Pawel Zarembski 0:01f31e923fe2 2088 EDMA_HandleIRQ(s_EDMAHandle[1]);
Pawel Zarembski 0:01f31e923fe2 2089 }
Pawel Zarembski 0:01f31e923fe2 2090 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2091 {
Pawel Zarembski 0:01f31e923fe2 2092 EDMA_HandleIRQ(s_EDMAHandle[5]);
Pawel Zarembski 0:01f31e923fe2 2093 }
Pawel Zarembski 0:01f31e923fe2 2094 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2095 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2096 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2097 __DSB();
Pawel Zarembski 0:01f31e923fe2 2098 #endif
Pawel Zarembski 0:01f31e923fe2 2099 }
Pawel Zarembski 0:01f31e923fe2 2100
Pawel Zarembski 0:01f31e923fe2 2101 void DMA0_2_6_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2102 {
Pawel Zarembski 0:01f31e923fe2 2103 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2104 {
Pawel Zarembski 0:01f31e923fe2 2105 EDMA_HandleIRQ(s_EDMAHandle[2]);
Pawel Zarembski 0:01f31e923fe2 2106 }
Pawel Zarembski 0:01f31e923fe2 2107 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2108 {
Pawel Zarembski 0:01f31e923fe2 2109 EDMA_HandleIRQ(s_EDMAHandle[6]);
Pawel Zarembski 0:01f31e923fe2 2110 }
Pawel Zarembski 0:01f31e923fe2 2111 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2112 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2113 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2114 __DSB();
Pawel Zarembski 0:01f31e923fe2 2115 #endif
Pawel Zarembski 0:01f31e923fe2 2116 }
Pawel Zarembski 0:01f31e923fe2 2117
Pawel Zarembski 0:01f31e923fe2 2118 void DMA0_3_7_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2119 {
Pawel Zarembski 0:01f31e923fe2 2120 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2121 {
Pawel Zarembski 0:01f31e923fe2 2122 EDMA_HandleIRQ(s_EDMAHandle[3]);
Pawel Zarembski 0:01f31e923fe2 2123 }
Pawel Zarembski 0:01f31e923fe2 2124 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2125 {
Pawel Zarembski 0:01f31e923fe2 2126 EDMA_HandleIRQ(s_EDMAHandle[7]);
Pawel Zarembski 0:01f31e923fe2 2127 }
Pawel Zarembski 0:01f31e923fe2 2128 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2129 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2130 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2131 __DSB();
Pawel Zarembski 0:01f31e923fe2 2132 #endif
Pawel Zarembski 0:01f31e923fe2 2133 }
Pawel Zarembski 0:01f31e923fe2 2134
Pawel Zarembski 0:01f31e923fe2 2135 void DMA0_8_12_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2136 {
Pawel Zarembski 0:01f31e923fe2 2137 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2138 {
Pawel Zarembski 0:01f31e923fe2 2139 EDMA_HandleIRQ(s_EDMAHandle[8]);
Pawel Zarembski 0:01f31e923fe2 2140 }
Pawel Zarembski 0:01f31e923fe2 2141 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2142 {
Pawel Zarembski 0:01f31e923fe2 2143 EDMA_HandleIRQ(s_EDMAHandle[12]);
Pawel Zarembski 0:01f31e923fe2 2144 }
Pawel Zarembski 0:01f31e923fe2 2145 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2146 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2147 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2148 __DSB();
Pawel Zarembski 0:01f31e923fe2 2149 #endif
Pawel Zarembski 0:01f31e923fe2 2150 }
Pawel Zarembski 0:01f31e923fe2 2151
Pawel Zarembski 0:01f31e923fe2 2152 void DMA0_9_13_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2153 {
Pawel Zarembski 0:01f31e923fe2 2154 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2155 {
Pawel Zarembski 0:01f31e923fe2 2156 EDMA_HandleIRQ(s_EDMAHandle[9]);
Pawel Zarembski 0:01f31e923fe2 2157 }
Pawel Zarembski 0:01f31e923fe2 2158 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2159 {
Pawel Zarembski 0:01f31e923fe2 2160 EDMA_HandleIRQ(s_EDMAHandle[13]);
Pawel Zarembski 0:01f31e923fe2 2161 }
Pawel Zarembski 0:01f31e923fe2 2162 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2163 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2164 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2165 __DSB();
Pawel Zarembski 0:01f31e923fe2 2166 #endif
Pawel Zarembski 0:01f31e923fe2 2167 }
Pawel Zarembski 0:01f31e923fe2 2168
Pawel Zarembski 0:01f31e923fe2 2169 void DMA0_10_14_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2170 {
Pawel Zarembski 0:01f31e923fe2 2171 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2172 {
Pawel Zarembski 0:01f31e923fe2 2173 EDMA_HandleIRQ(s_EDMAHandle[10]);
Pawel Zarembski 0:01f31e923fe2 2174 }
Pawel Zarembski 0:01f31e923fe2 2175 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2176 {
Pawel Zarembski 0:01f31e923fe2 2177 EDMA_HandleIRQ(s_EDMAHandle[14]);
Pawel Zarembski 0:01f31e923fe2 2178 }
Pawel Zarembski 0:01f31e923fe2 2179 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2180 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2181 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2182 __DSB();
Pawel Zarembski 0:01f31e923fe2 2183 #endif
Pawel Zarembski 0:01f31e923fe2 2184 }
Pawel Zarembski 0:01f31e923fe2 2185
Pawel Zarembski 0:01f31e923fe2 2186 void DMA0_11_15_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2187 {
Pawel Zarembski 0:01f31e923fe2 2188 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2189 {
Pawel Zarembski 0:01f31e923fe2 2190 EDMA_HandleIRQ(s_EDMAHandle[11]);
Pawel Zarembski 0:01f31e923fe2 2191 }
Pawel Zarembski 0:01f31e923fe2 2192 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2193 {
Pawel Zarembski 0:01f31e923fe2 2194 EDMA_HandleIRQ(s_EDMAHandle[15]);
Pawel Zarembski 0:01f31e923fe2 2195 }
Pawel Zarembski 0:01f31e923fe2 2196 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2197 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2198 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2199 __DSB();
Pawel Zarembski 0:01f31e923fe2 2200 #endif
Pawel Zarembski 0:01f31e923fe2 2201 }
Pawel Zarembski 0:01f31e923fe2 2202
Pawel Zarembski 0:01f31e923fe2 2203 void DMA0_16_20_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2204 {
Pawel Zarembski 0:01f31e923fe2 2205 if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2206 {
Pawel Zarembski 0:01f31e923fe2 2207 EDMA_HandleIRQ(s_EDMAHandle[16]);
Pawel Zarembski 0:01f31e923fe2 2208 }
Pawel Zarembski 0:01f31e923fe2 2209 if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2210 {
Pawel Zarembski 0:01f31e923fe2 2211 EDMA_HandleIRQ(s_EDMAHandle[20]);
Pawel Zarembski 0:01f31e923fe2 2212 }
Pawel Zarembski 0:01f31e923fe2 2213 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2214 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2215 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2216 __DSB();
Pawel Zarembski 0:01f31e923fe2 2217 #endif
Pawel Zarembski 0:01f31e923fe2 2218 }
Pawel Zarembski 0:01f31e923fe2 2219
Pawel Zarembski 0:01f31e923fe2 2220 void DMA0_17_21_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2221 {
Pawel Zarembski 0:01f31e923fe2 2222 if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2223 {
Pawel Zarembski 0:01f31e923fe2 2224 EDMA_HandleIRQ(s_EDMAHandle[17]);
Pawel Zarembski 0:01f31e923fe2 2225 }
Pawel Zarembski 0:01f31e923fe2 2226 if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2227 {
Pawel Zarembski 0:01f31e923fe2 2228 EDMA_HandleIRQ(s_EDMAHandle[21]);
Pawel Zarembski 0:01f31e923fe2 2229 }
Pawel Zarembski 0:01f31e923fe2 2230 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2231 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2232 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2233 __DSB();
Pawel Zarembski 0:01f31e923fe2 2234 #endif
Pawel Zarembski 0:01f31e923fe2 2235 }
Pawel Zarembski 0:01f31e923fe2 2236
Pawel Zarembski 0:01f31e923fe2 2237 void DMA0_18_22_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2238 {
Pawel Zarembski 0:01f31e923fe2 2239 if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2240 {
Pawel Zarembski 0:01f31e923fe2 2241 EDMA_HandleIRQ(s_EDMAHandle[18]);
Pawel Zarembski 0:01f31e923fe2 2242 }
Pawel Zarembski 0:01f31e923fe2 2243 if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2244 {
Pawel Zarembski 0:01f31e923fe2 2245 EDMA_HandleIRQ(s_EDMAHandle[22]);
Pawel Zarembski 0:01f31e923fe2 2246 }
Pawel Zarembski 0:01f31e923fe2 2247 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2248 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2249 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2250 __DSB();
Pawel Zarembski 0:01f31e923fe2 2251 #endif
Pawel Zarembski 0:01f31e923fe2 2252 }
Pawel Zarembski 0:01f31e923fe2 2253
Pawel Zarembski 0:01f31e923fe2 2254 void DMA0_19_23_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2255 {
Pawel Zarembski 0:01f31e923fe2 2256 if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2257 {
Pawel Zarembski 0:01f31e923fe2 2258 EDMA_HandleIRQ(s_EDMAHandle[19]);
Pawel Zarembski 0:01f31e923fe2 2259 }
Pawel Zarembski 0:01f31e923fe2 2260 if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2261 {
Pawel Zarembski 0:01f31e923fe2 2262 EDMA_HandleIRQ(s_EDMAHandle[23]);
Pawel Zarembski 0:01f31e923fe2 2263 }
Pawel Zarembski 0:01f31e923fe2 2264 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2265 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2266 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2267 __DSB();
Pawel Zarembski 0:01f31e923fe2 2268 #endif
Pawel Zarembski 0:01f31e923fe2 2269 }
Pawel Zarembski 0:01f31e923fe2 2270
Pawel Zarembski 0:01f31e923fe2 2271 void DMA0_24_28_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2272 {
Pawel Zarembski 0:01f31e923fe2 2273 if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2274 {
Pawel Zarembski 0:01f31e923fe2 2275 EDMA_HandleIRQ(s_EDMAHandle[24]);
Pawel Zarembski 0:01f31e923fe2 2276 }
Pawel Zarembski 0:01f31e923fe2 2277 if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2278 {
Pawel Zarembski 0:01f31e923fe2 2279 EDMA_HandleIRQ(s_EDMAHandle[28]);
Pawel Zarembski 0:01f31e923fe2 2280 }
Pawel Zarembski 0:01f31e923fe2 2281 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2282 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2283 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2284 __DSB();
Pawel Zarembski 0:01f31e923fe2 2285 #endif
Pawel Zarembski 0:01f31e923fe2 2286 }
Pawel Zarembski 0:01f31e923fe2 2287
Pawel Zarembski 0:01f31e923fe2 2288 void DMA0_25_29_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2289 {
Pawel Zarembski 0:01f31e923fe2 2290 if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2291 {
Pawel Zarembski 0:01f31e923fe2 2292 EDMA_HandleIRQ(s_EDMAHandle[25]);
Pawel Zarembski 0:01f31e923fe2 2293 }
Pawel Zarembski 0:01f31e923fe2 2294 if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2295 {
Pawel Zarembski 0:01f31e923fe2 2296 EDMA_HandleIRQ(s_EDMAHandle[29]);
Pawel Zarembski 0:01f31e923fe2 2297 }
Pawel Zarembski 0:01f31e923fe2 2298 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2299 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2300 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2301 __DSB();
Pawel Zarembski 0:01f31e923fe2 2302 #endif
Pawel Zarembski 0:01f31e923fe2 2303 }
Pawel Zarembski 0:01f31e923fe2 2304
Pawel Zarembski 0:01f31e923fe2 2305 void DMA0_26_30_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2306 {
Pawel Zarembski 0:01f31e923fe2 2307 if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2308 {
Pawel Zarembski 0:01f31e923fe2 2309 EDMA_HandleIRQ(s_EDMAHandle[26]);
Pawel Zarembski 0:01f31e923fe2 2310 }
Pawel Zarembski 0:01f31e923fe2 2311 if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2312 {
Pawel Zarembski 0:01f31e923fe2 2313 EDMA_HandleIRQ(s_EDMAHandle[30]);
Pawel Zarembski 0:01f31e923fe2 2314 }
Pawel Zarembski 0:01f31e923fe2 2315 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2316 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2317 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2318 __DSB();
Pawel Zarembski 0:01f31e923fe2 2319 #endif
Pawel Zarembski 0:01f31e923fe2 2320 }
Pawel Zarembski 0:01f31e923fe2 2321
Pawel Zarembski 0:01f31e923fe2 2322 void DMA0_27_31_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2323 {
Pawel Zarembski 0:01f31e923fe2 2324 if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2325 {
Pawel Zarembski 0:01f31e923fe2 2326 EDMA_HandleIRQ(s_EDMAHandle[27]);
Pawel Zarembski 0:01f31e923fe2 2327 }
Pawel Zarembski 0:01f31e923fe2 2328 if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
Pawel Zarembski 0:01f31e923fe2 2329 {
Pawel Zarembski 0:01f31e923fe2 2330 EDMA_HandleIRQ(s_EDMAHandle[31]);
Pawel Zarembski 0:01f31e923fe2 2331 }
Pawel Zarembski 0:01f31e923fe2 2332 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2333 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2334 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2335 __DSB();
Pawel Zarembski 0:01f31e923fe2 2336 #endif
Pawel Zarembski 0:01f31e923fe2 2337 }
Pawel Zarembski 0:01f31e923fe2 2338 #endif /* 32 channels (Shared): MCIMX7U5 */
Pawel Zarembski 0:01f31e923fe2 2339
Pawel Zarembski 0:01f31e923fe2 2340 /* 4 channels (No Shared): kv10 */
Pawel Zarembski 0:01f31e923fe2 2341 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
Pawel Zarembski 0:01f31e923fe2 2342
Pawel Zarembski 0:01f31e923fe2 2343 void DMA0_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2344 {
Pawel Zarembski 0:01f31e923fe2 2345 EDMA_HandleIRQ(s_EDMAHandle[0]);
Pawel Zarembski 0:01f31e923fe2 2346 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2347 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2348 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2349 __DSB();
Pawel Zarembski 0:01f31e923fe2 2350 #endif
Pawel Zarembski 0:01f31e923fe2 2351 }
Pawel Zarembski 0:01f31e923fe2 2352
Pawel Zarembski 0:01f31e923fe2 2353 void DMA1_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2354 {
Pawel Zarembski 0:01f31e923fe2 2355 EDMA_HandleIRQ(s_EDMAHandle[1]);
Pawel Zarembski 0:01f31e923fe2 2356 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2357 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2358 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2359 __DSB();
Pawel Zarembski 0:01f31e923fe2 2360 #endif
Pawel Zarembski 0:01f31e923fe2 2361 }
Pawel Zarembski 0:01f31e923fe2 2362
Pawel Zarembski 0:01f31e923fe2 2363 void DMA2_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2364 {
Pawel Zarembski 0:01f31e923fe2 2365 EDMA_HandleIRQ(s_EDMAHandle[2]);
Pawel Zarembski 0:01f31e923fe2 2366 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2367 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2368 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2369 __DSB();
Pawel Zarembski 0:01f31e923fe2 2370 #endif
Pawel Zarembski 0:01f31e923fe2 2371 }
Pawel Zarembski 0:01f31e923fe2 2372
Pawel Zarembski 0:01f31e923fe2 2373 void DMA3_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2374 {
Pawel Zarembski 0:01f31e923fe2 2375 EDMA_HandleIRQ(s_EDMAHandle[3]);
Pawel Zarembski 0:01f31e923fe2 2376 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2377 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2378 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2379 __DSB();
Pawel Zarembski 0:01f31e923fe2 2380 #endif
Pawel Zarembski 0:01f31e923fe2 2381 }
Pawel Zarembski 0:01f31e923fe2 2382
Pawel Zarembski 0:01f31e923fe2 2383 /* 8 channels (No Shared) */
Pawel Zarembski 0:01f31e923fe2 2384 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
Pawel Zarembski 0:01f31e923fe2 2385
Pawel Zarembski 0:01f31e923fe2 2386 void DMA4_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2387 {
Pawel Zarembski 0:01f31e923fe2 2388 EDMA_HandleIRQ(s_EDMAHandle[4]);
Pawel Zarembski 0:01f31e923fe2 2389 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2390 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2391 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2392 __DSB();
Pawel Zarembski 0:01f31e923fe2 2393 #endif
Pawel Zarembski 0:01f31e923fe2 2394 }
Pawel Zarembski 0:01f31e923fe2 2395
Pawel Zarembski 0:01f31e923fe2 2396 void DMA5_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2397 {
Pawel Zarembski 0:01f31e923fe2 2398 EDMA_HandleIRQ(s_EDMAHandle[5]);
Pawel Zarembski 0:01f31e923fe2 2399 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2400 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2401 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2402 __DSB();
Pawel Zarembski 0:01f31e923fe2 2403 #endif
Pawel Zarembski 0:01f31e923fe2 2404 }
Pawel Zarembski 0:01f31e923fe2 2405
Pawel Zarembski 0:01f31e923fe2 2406 void DMA6_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2407 {
Pawel Zarembski 0:01f31e923fe2 2408 EDMA_HandleIRQ(s_EDMAHandle[6]);
Pawel Zarembski 0:01f31e923fe2 2409 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2410 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2411 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2412 __DSB();
Pawel Zarembski 0:01f31e923fe2 2413 #endif
Pawel Zarembski 0:01f31e923fe2 2414 }
Pawel Zarembski 0:01f31e923fe2 2415
Pawel Zarembski 0:01f31e923fe2 2416 void DMA7_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2417 {
Pawel Zarembski 0:01f31e923fe2 2418 EDMA_HandleIRQ(s_EDMAHandle[7]);
Pawel Zarembski 0:01f31e923fe2 2419 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2420 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2421 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2422 __DSB();
Pawel Zarembski 0:01f31e923fe2 2423 #endif
Pawel Zarembski 0:01f31e923fe2 2424 }
Pawel Zarembski 0:01f31e923fe2 2425 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
Pawel Zarembski 0:01f31e923fe2 2426
Pawel Zarembski 0:01f31e923fe2 2427 /* 16 channels (No Shared) */
Pawel Zarembski 0:01f31e923fe2 2428 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
Pawel Zarembski 0:01f31e923fe2 2429
Pawel Zarembski 0:01f31e923fe2 2430 void DMA8_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2431 {
Pawel Zarembski 0:01f31e923fe2 2432 EDMA_HandleIRQ(s_EDMAHandle[8]);
Pawel Zarembski 0:01f31e923fe2 2433 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2434 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2435 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2436 __DSB();
Pawel Zarembski 0:01f31e923fe2 2437 #endif
Pawel Zarembski 0:01f31e923fe2 2438 }
Pawel Zarembski 0:01f31e923fe2 2439
Pawel Zarembski 0:01f31e923fe2 2440 void DMA9_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2441 {
Pawel Zarembski 0:01f31e923fe2 2442 EDMA_HandleIRQ(s_EDMAHandle[9]);
Pawel Zarembski 0:01f31e923fe2 2443 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2444 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2445 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2446 __DSB();
Pawel Zarembski 0:01f31e923fe2 2447 #endif
Pawel Zarembski 0:01f31e923fe2 2448 }
Pawel Zarembski 0:01f31e923fe2 2449
Pawel Zarembski 0:01f31e923fe2 2450 void DMA10_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2451 {
Pawel Zarembski 0:01f31e923fe2 2452 EDMA_HandleIRQ(s_EDMAHandle[10]);
Pawel Zarembski 0:01f31e923fe2 2453 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2454 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2455 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2456 __DSB();
Pawel Zarembski 0:01f31e923fe2 2457 #endif
Pawel Zarembski 0:01f31e923fe2 2458 }
Pawel Zarembski 0:01f31e923fe2 2459
Pawel Zarembski 0:01f31e923fe2 2460 void DMA11_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2461 {
Pawel Zarembski 0:01f31e923fe2 2462 EDMA_HandleIRQ(s_EDMAHandle[11]);
Pawel Zarembski 0:01f31e923fe2 2463 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2464 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2465 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2466 __DSB();
Pawel Zarembski 0:01f31e923fe2 2467 #endif
Pawel Zarembski 0:01f31e923fe2 2468 }
Pawel Zarembski 0:01f31e923fe2 2469
Pawel Zarembski 0:01f31e923fe2 2470 void DMA12_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2471 {
Pawel Zarembski 0:01f31e923fe2 2472 EDMA_HandleIRQ(s_EDMAHandle[12]);
Pawel Zarembski 0:01f31e923fe2 2473 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2474 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2475 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2476 __DSB();
Pawel Zarembski 0:01f31e923fe2 2477 #endif
Pawel Zarembski 0:01f31e923fe2 2478 }
Pawel Zarembski 0:01f31e923fe2 2479
Pawel Zarembski 0:01f31e923fe2 2480 void DMA13_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2481 {
Pawel Zarembski 0:01f31e923fe2 2482 EDMA_HandleIRQ(s_EDMAHandle[13]);
Pawel Zarembski 0:01f31e923fe2 2483 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2484 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2485 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2486 __DSB();
Pawel Zarembski 0:01f31e923fe2 2487 #endif
Pawel Zarembski 0:01f31e923fe2 2488 }
Pawel Zarembski 0:01f31e923fe2 2489
Pawel Zarembski 0:01f31e923fe2 2490 void DMA14_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2491 {
Pawel Zarembski 0:01f31e923fe2 2492 EDMA_HandleIRQ(s_EDMAHandle[14]);
Pawel Zarembski 0:01f31e923fe2 2493 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2494 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2495 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2496 __DSB();
Pawel Zarembski 0:01f31e923fe2 2497 #endif
Pawel Zarembski 0:01f31e923fe2 2498 }
Pawel Zarembski 0:01f31e923fe2 2499
Pawel Zarembski 0:01f31e923fe2 2500 void DMA15_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2501 {
Pawel Zarembski 0:01f31e923fe2 2502 EDMA_HandleIRQ(s_EDMAHandle[15]);
Pawel Zarembski 0:01f31e923fe2 2503 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2504 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2505 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2506 __DSB();
Pawel Zarembski 0:01f31e923fe2 2507 #endif
Pawel Zarembski 0:01f31e923fe2 2508 }
Pawel Zarembski 0:01f31e923fe2 2509 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
Pawel Zarembski 0:01f31e923fe2 2510
Pawel Zarembski 0:01f31e923fe2 2511 /* 32 channels (No Shared) */
Pawel Zarembski 0:01f31e923fe2 2512 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
Pawel Zarembski 0:01f31e923fe2 2513
Pawel Zarembski 0:01f31e923fe2 2514 void DMA16_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2515 {
Pawel Zarembski 0:01f31e923fe2 2516 EDMA_HandleIRQ(s_EDMAHandle[16]);
Pawel Zarembski 0:01f31e923fe2 2517 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2518 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2519 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2520 __DSB();
Pawel Zarembski 0:01f31e923fe2 2521 #endif
Pawel Zarembski 0:01f31e923fe2 2522 }
Pawel Zarembski 0:01f31e923fe2 2523
Pawel Zarembski 0:01f31e923fe2 2524 void DMA17_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2525 {
Pawel Zarembski 0:01f31e923fe2 2526 EDMA_HandleIRQ(s_EDMAHandle[17]);
Pawel Zarembski 0:01f31e923fe2 2527 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2528 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2529 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2530 __DSB();
Pawel Zarembski 0:01f31e923fe2 2531 #endif
Pawel Zarembski 0:01f31e923fe2 2532 }
Pawel Zarembski 0:01f31e923fe2 2533
Pawel Zarembski 0:01f31e923fe2 2534 void DMA18_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2535 {
Pawel Zarembski 0:01f31e923fe2 2536 EDMA_HandleIRQ(s_EDMAHandle[18]);
Pawel Zarembski 0:01f31e923fe2 2537 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2538 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2539 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2540 __DSB();
Pawel Zarembski 0:01f31e923fe2 2541 #endif
Pawel Zarembski 0:01f31e923fe2 2542 }
Pawel Zarembski 0:01f31e923fe2 2543
Pawel Zarembski 0:01f31e923fe2 2544 void DMA19_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2545 {
Pawel Zarembski 0:01f31e923fe2 2546 EDMA_HandleIRQ(s_EDMAHandle[19]);
Pawel Zarembski 0:01f31e923fe2 2547 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2548 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2549 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2550 __DSB();
Pawel Zarembski 0:01f31e923fe2 2551 #endif
Pawel Zarembski 0:01f31e923fe2 2552 }
Pawel Zarembski 0:01f31e923fe2 2553
Pawel Zarembski 0:01f31e923fe2 2554 void DMA20_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2555 {
Pawel Zarembski 0:01f31e923fe2 2556 EDMA_HandleIRQ(s_EDMAHandle[20]);
Pawel Zarembski 0:01f31e923fe2 2557 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2558 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2559 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2560 __DSB();
Pawel Zarembski 0:01f31e923fe2 2561 #endif
Pawel Zarembski 0:01f31e923fe2 2562 }
Pawel Zarembski 0:01f31e923fe2 2563
Pawel Zarembski 0:01f31e923fe2 2564 void DMA21_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2565 {
Pawel Zarembski 0:01f31e923fe2 2566 EDMA_HandleIRQ(s_EDMAHandle[21]);
Pawel Zarembski 0:01f31e923fe2 2567 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2568 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2569 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2570 __DSB();
Pawel Zarembski 0:01f31e923fe2 2571 #endif
Pawel Zarembski 0:01f31e923fe2 2572 }
Pawel Zarembski 0:01f31e923fe2 2573
Pawel Zarembski 0:01f31e923fe2 2574 void DMA22_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2575 {
Pawel Zarembski 0:01f31e923fe2 2576 EDMA_HandleIRQ(s_EDMAHandle[22]);
Pawel Zarembski 0:01f31e923fe2 2577 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2578 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2579 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2580 __DSB();
Pawel Zarembski 0:01f31e923fe2 2581 #endif
Pawel Zarembski 0:01f31e923fe2 2582 }
Pawel Zarembski 0:01f31e923fe2 2583
Pawel Zarembski 0:01f31e923fe2 2584 void DMA23_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2585 {
Pawel Zarembski 0:01f31e923fe2 2586 EDMA_HandleIRQ(s_EDMAHandle[23]);
Pawel Zarembski 0:01f31e923fe2 2587 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2588 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2589 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2590 __DSB();
Pawel Zarembski 0:01f31e923fe2 2591 #endif
Pawel Zarembski 0:01f31e923fe2 2592 }
Pawel Zarembski 0:01f31e923fe2 2593
Pawel Zarembski 0:01f31e923fe2 2594 void DMA24_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2595 {
Pawel Zarembski 0:01f31e923fe2 2596 EDMA_HandleIRQ(s_EDMAHandle[24]);
Pawel Zarembski 0:01f31e923fe2 2597 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2598 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2599 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2600 __DSB();
Pawel Zarembski 0:01f31e923fe2 2601 #endif
Pawel Zarembski 0:01f31e923fe2 2602 }
Pawel Zarembski 0:01f31e923fe2 2603
Pawel Zarembski 0:01f31e923fe2 2604 void DMA25_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2605 {
Pawel Zarembski 0:01f31e923fe2 2606 EDMA_HandleIRQ(s_EDMAHandle[25]);
Pawel Zarembski 0:01f31e923fe2 2607 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2608 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2609 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2610 __DSB();
Pawel Zarembski 0:01f31e923fe2 2611 #endif
Pawel Zarembski 0:01f31e923fe2 2612 }
Pawel Zarembski 0:01f31e923fe2 2613
Pawel Zarembski 0:01f31e923fe2 2614 void DMA26_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2615 {
Pawel Zarembski 0:01f31e923fe2 2616 EDMA_HandleIRQ(s_EDMAHandle[26]);
Pawel Zarembski 0:01f31e923fe2 2617 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2618 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2619 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2620 __DSB();
Pawel Zarembski 0:01f31e923fe2 2621 #endif
Pawel Zarembski 0:01f31e923fe2 2622 }
Pawel Zarembski 0:01f31e923fe2 2623
Pawel Zarembski 0:01f31e923fe2 2624 void DMA27_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2625 {
Pawel Zarembski 0:01f31e923fe2 2626 EDMA_HandleIRQ(s_EDMAHandle[27]);
Pawel Zarembski 0:01f31e923fe2 2627 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2628 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2629 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2630 __DSB();
Pawel Zarembski 0:01f31e923fe2 2631 #endif
Pawel Zarembski 0:01f31e923fe2 2632 }
Pawel Zarembski 0:01f31e923fe2 2633
Pawel Zarembski 0:01f31e923fe2 2634 void DMA28_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2635 {
Pawel Zarembski 0:01f31e923fe2 2636 EDMA_HandleIRQ(s_EDMAHandle[28]);
Pawel Zarembski 0:01f31e923fe2 2637 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2638 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2639 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2640 __DSB();
Pawel Zarembski 0:01f31e923fe2 2641 #endif
Pawel Zarembski 0:01f31e923fe2 2642 }
Pawel Zarembski 0:01f31e923fe2 2643
Pawel Zarembski 0:01f31e923fe2 2644 void DMA29_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2645 {
Pawel Zarembski 0:01f31e923fe2 2646 EDMA_HandleIRQ(s_EDMAHandle[29]);
Pawel Zarembski 0:01f31e923fe2 2647 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2648 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2649 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2650 __DSB();
Pawel Zarembski 0:01f31e923fe2 2651 #endif
Pawel Zarembski 0:01f31e923fe2 2652 }
Pawel Zarembski 0:01f31e923fe2 2653
Pawel Zarembski 0:01f31e923fe2 2654 void DMA30_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2655 {
Pawel Zarembski 0:01f31e923fe2 2656 EDMA_HandleIRQ(s_EDMAHandle[30]);
Pawel Zarembski 0:01f31e923fe2 2657 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2658 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2659 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2660 __DSB();
Pawel Zarembski 0:01f31e923fe2 2661 #endif
Pawel Zarembski 0:01f31e923fe2 2662 }
Pawel Zarembski 0:01f31e923fe2 2663
Pawel Zarembski 0:01f31e923fe2 2664 void DMA31_DriverIRQHandler(void)
Pawel Zarembski 0:01f31e923fe2 2665 {
Pawel Zarembski 0:01f31e923fe2 2666 EDMA_HandleIRQ(s_EDMAHandle[31]);
Pawel Zarembski 0:01f31e923fe2 2667 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
Pawel Zarembski 0:01f31e923fe2 2668 exception return operation might vector to incorrect interrupt */
Pawel Zarembski 0:01f31e923fe2 2669 #if defined __CORTEX_M && (__CORTEX_M == 4U)
Pawel Zarembski 0:01f31e923fe2 2670 __DSB();
Pawel Zarembski 0:01f31e923fe2 2671 #endif
Pawel Zarembski 0:01f31e923fe2 2672 }
Pawel Zarembski 0:01f31e923fe2 2673 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
Pawel Zarembski 0:01f31e923fe2 2674
Pawel Zarembski 0:01f31e923fe2 2675 #endif /* 4/8/16/32 channels (No Shared) */