Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/freescale/k26f/fsl_dmamux.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
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Pawel Zarembski |
0:01f31e923fe2 | 1 | /* |
Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
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0:01f31e923fe2 | 3 | * Copyright 2016-2017 NXP |
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0:01f31e923fe2 | 4 | * All rights reserved. |
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0:01f31e923fe2 | 5 | * |
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0:01f31e923fe2 | 6 | * SPDX-License-Identifier: BSD-3-Clause |
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0:01f31e923fe2 | 7 | */ |
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0:01f31e923fe2 | 8 | |
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0:01f31e923fe2 | 9 | #ifndef _FSL_DMAMUX_H_ |
Pawel Zarembski |
0:01f31e923fe2 | 10 | #define _FSL_DMAMUX_H_ |
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0:01f31e923fe2 | 11 | |
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0:01f31e923fe2 | 12 | #include "fsl_common.h" |
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0:01f31e923fe2 | 13 | |
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0:01f31e923fe2 | 14 | /*! |
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0:01f31e923fe2 | 15 | * @addtogroup dmamux |
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0:01f31e923fe2 | 16 | * @{ |
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0:01f31e923fe2 | 17 | */ |
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0:01f31e923fe2 | 18 | |
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0:01f31e923fe2 | 19 | |
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0:01f31e923fe2 | 20 | /******************************************************************************* |
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0:01f31e923fe2 | 21 | * Definitions |
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0:01f31e923fe2 | 22 | ******************************************************************************/ |
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0:01f31e923fe2 | 23 | |
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0:01f31e923fe2 | 24 | /*! @name Driver version */ |
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0:01f31e923fe2 | 25 | /*@{*/ |
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0:01f31e923fe2 | 26 | /*! @brief DMAMUX driver version 2.0.2. */ |
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0:01f31e923fe2 | 27 | #define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) |
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0:01f31e923fe2 | 28 | /*@}*/ |
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0:01f31e923fe2 | 29 | |
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0:01f31e923fe2 | 30 | /******************************************************************************* |
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0:01f31e923fe2 | 31 | * API |
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0:01f31e923fe2 | 32 | ******************************************************************************/ |
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0:01f31e923fe2 | 33 | |
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0:01f31e923fe2 | 34 | #if defined(__cplusplus) |
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0:01f31e923fe2 | 35 | extern "C" { |
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0:01f31e923fe2 | 36 | #endif /* __cplusplus */ |
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0:01f31e923fe2 | 37 | |
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0:01f31e923fe2 | 38 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 39 | * @name DMAMUX Initialization and de-initialization |
Pawel Zarembski |
0:01f31e923fe2 | 40 | * @{ |
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0:01f31e923fe2 | 41 | */ |
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0:01f31e923fe2 | 42 | |
Pawel Zarembski |
0:01f31e923fe2 | 43 | /*! |
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0:01f31e923fe2 | 44 | * @brief Initializes the DMAMUX peripheral. |
Pawel Zarembski |
0:01f31e923fe2 | 45 | * |
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0:01f31e923fe2 | 46 | * This function ungates the DMAMUX clock. |
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0:01f31e923fe2 | 47 | * |
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0:01f31e923fe2 | 48 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 49 | * |
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0:01f31e923fe2 | 50 | */ |
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0:01f31e923fe2 | 51 | void DMAMUX_Init(DMAMUX_Type *base); |
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0:01f31e923fe2 | 52 | |
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0:01f31e923fe2 | 53 | /*! |
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0:01f31e923fe2 | 54 | * @brief Deinitializes the DMAMUX peripheral. |
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0:01f31e923fe2 | 55 | * |
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0:01f31e923fe2 | 56 | * This function gates the DMAMUX clock. |
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0:01f31e923fe2 | 57 | * |
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0:01f31e923fe2 | 58 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 59 | */ |
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0:01f31e923fe2 | 60 | void DMAMUX_Deinit(DMAMUX_Type *base); |
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0:01f31e923fe2 | 61 | |
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0:01f31e923fe2 | 62 | /* @} */ |
Pawel Zarembski |
0:01f31e923fe2 | 63 | /*! |
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0:01f31e923fe2 | 64 | * @name DMAMUX Channel Operation |
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0:01f31e923fe2 | 65 | * @{ |
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0:01f31e923fe2 | 66 | */ |
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0:01f31e923fe2 | 67 | |
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0:01f31e923fe2 | 68 | /*! |
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0:01f31e923fe2 | 69 | * @brief Enables the DMAMUX channel. |
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0:01f31e923fe2 | 70 | * |
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0:01f31e923fe2 | 71 | * This function enables the DMAMUX channel. |
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0:01f31e923fe2 | 72 | * |
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0:01f31e923fe2 | 73 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 74 | * @param channel DMAMUX channel number. |
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0:01f31e923fe2 | 75 | */ |
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0:01f31e923fe2 | 76 | static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) |
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0:01f31e923fe2 | 77 | { |
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0:01f31e923fe2 | 78 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
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0:01f31e923fe2 | 79 | |
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0:01f31e923fe2 | 80 | base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; |
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0:01f31e923fe2 | 81 | } |
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0:01f31e923fe2 | 82 | |
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0:01f31e923fe2 | 83 | /*! |
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0:01f31e923fe2 | 84 | * @brief Disables the DMAMUX channel. |
Pawel Zarembski |
0:01f31e923fe2 | 85 | * |
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0:01f31e923fe2 | 86 | * This function disables the DMAMUX channel. |
Pawel Zarembski |
0:01f31e923fe2 | 87 | * |
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0:01f31e923fe2 | 88 | * @note The user must disable the DMAMUX channel before configuring it. |
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0:01f31e923fe2 | 89 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 90 | * @param channel DMAMUX channel number. |
Pawel Zarembski |
0:01f31e923fe2 | 91 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 92 | static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) |
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0:01f31e923fe2 | 93 | { |
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0:01f31e923fe2 | 94 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
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0:01f31e923fe2 | 95 | |
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0:01f31e923fe2 | 96 | base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; |
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0:01f31e923fe2 | 97 | } |
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0:01f31e923fe2 | 98 | |
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0:01f31e923fe2 | 99 | /*! |
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0:01f31e923fe2 | 100 | * @brief Configures the DMAMUX channel source. |
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0:01f31e923fe2 | 101 | * |
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0:01f31e923fe2 | 102 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 103 | * @param channel DMAMUX channel number. |
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0:01f31e923fe2 | 104 | * @param source Channel source, which is used to trigger the DMA transfer. |
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0:01f31e923fe2 | 105 | */ |
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0:01f31e923fe2 | 106 | static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) |
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0:01f31e923fe2 | 107 | { |
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0:01f31e923fe2 | 108 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
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0:01f31e923fe2 | 109 | |
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0:01f31e923fe2 | 110 | base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); |
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0:01f31e923fe2 | 111 | } |
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0:01f31e923fe2 | 112 | |
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0:01f31e923fe2 | 113 | #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U |
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0:01f31e923fe2 | 114 | /*! |
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0:01f31e923fe2 | 115 | * @brief Enables the DMAMUX period trigger. |
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0:01f31e923fe2 | 116 | * |
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0:01f31e923fe2 | 117 | * This function enables the DMAMUX period trigger feature. |
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0:01f31e923fe2 | 118 | * |
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0:01f31e923fe2 | 119 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 120 | * @param channel DMAMUX channel number. |
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0:01f31e923fe2 | 121 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 122 | static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) |
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0:01f31e923fe2 | 123 | { |
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0:01f31e923fe2 | 124 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
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0:01f31e923fe2 | 125 | |
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0:01f31e923fe2 | 126 | base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; |
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0:01f31e923fe2 | 127 | } |
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0:01f31e923fe2 | 128 | |
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0:01f31e923fe2 | 129 | /*! |
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0:01f31e923fe2 | 130 | * @brief Disables the DMAMUX period trigger. |
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0:01f31e923fe2 | 131 | * |
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0:01f31e923fe2 | 132 | * This function disables the DMAMUX period trigger. |
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0:01f31e923fe2 | 133 | * |
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0:01f31e923fe2 | 134 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 135 | * @param channel DMAMUX channel number. |
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0:01f31e923fe2 | 136 | */ |
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0:01f31e923fe2 | 137 | static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) |
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0:01f31e923fe2 | 138 | { |
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0:01f31e923fe2 | 139 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
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0:01f31e923fe2 | 140 | |
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0:01f31e923fe2 | 141 | base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; |
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0:01f31e923fe2 | 142 | } |
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0:01f31e923fe2 | 143 | #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ |
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0:01f31e923fe2 | 144 | |
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0:01f31e923fe2 | 145 | #if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) |
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0:01f31e923fe2 | 146 | /*! |
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0:01f31e923fe2 | 147 | * @brief Enables the DMA channel to be always ON. |
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0:01f31e923fe2 | 148 | * |
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0:01f31e923fe2 | 149 | * This function enables the DMAMUX channel always ON feature. |
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0:01f31e923fe2 | 150 | * |
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0:01f31e923fe2 | 151 | * @param base DMAMUX peripheral base address. |
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0:01f31e923fe2 | 152 | * @param channel DMAMUX channel number. |
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0:01f31e923fe2 | 153 | * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. |
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0:01f31e923fe2 | 154 | */ |
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0:01f31e923fe2 | 155 | static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) |
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0:01f31e923fe2 | 156 | { |
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0:01f31e923fe2 | 157 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
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0:01f31e923fe2 | 158 | |
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0:01f31e923fe2 | 159 | if (enable) |
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0:01f31e923fe2 | 160 | { |
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0:01f31e923fe2 | 161 | base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; |
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0:01f31e923fe2 | 162 | } |
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0:01f31e923fe2 | 163 | else |
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0:01f31e923fe2 | 164 | { |
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0:01f31e923fe2 | 165 | base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; |
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0:01f31e923fe2 | 166 | } |
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0:01f31e923fe2 | 167 | } |
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0:01f31e923fe2 | 168 | #endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ |
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0:01f31e923fe2 | 169 | |
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0:01f31e923fe2 | 170 | /* @} */ |
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0:01f31e923fe2 | 171 | |
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0:01f31e923fe2 | 172 | #if defined(__cplusplus) |
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0:01f31e923fe2 | 173 | } |
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0:01f31e923fe2 | 174 | #endif /* __cplusplus */ |
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0:01f31e923fe2 | 175 | |
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0:01f31e923fe2 | 176 | /* @} */ |
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0:01f31e923fe2 | 177 | |
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0:01f31e923fe2 | 178 | #endif /* _FSL_DMAMUX_H_ */ |