Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k26f/IO_Config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file IO_Config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "fsl_device_registers.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "compiler.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 // This GPIO configuration is only valid for the K26F HIC
Pawel Zarembski 0:01f31e923fe2 30 COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_K26F);
Pawel Zarembski 0:01f31e923fe2 31
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 // Debug Port I/O Pins
Pawel Zarembski 0:01f31e923fe2 34
Pawel Zarembski 0:01f31e923fe2 35 // SWCLK Pin PTC5
Pawel Zarembski 0:01f31e923fe2 36 // (SDA_SWD_SCK on schematic)
Pawel Zarembski 0:01f31e923fe2 37 #define PIN_SWCLK_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 38 #define PIN_SWCLK_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 39 #define PIN_SWCLK_BIT 5
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 // SWDIO Out Pin PTC6
Pawel Zarembski 0:01f31e923fe2 42 // (SDA_SWD_DOUT on schematic)
Pawel Zarembski 0:01f31e923fe2 43 #define PIN_SWDIO_OUT_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 44 #define PIN_SWDIO_OUT_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 45 #define PIN_SWDIO_OUT_BIT 6
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 // SWDIO In Pin PTC7
Pawel Zarembski 0:01f31e923fe2 48 // (SDA_SWD_DIN on schematic)
Pawel Zarembski 0:01f31e923fe2 49 #define PIN_SWDIO_IN_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 50 #define PIN_SWDIO_IN_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 51 #define PIN_SWDIO_IN_BIT 7
Pawel Zarembski 0:01f31e923fe2 52
Pawel Zarembski 0:01f31e923fe2 53 // SWDIO Output Enable Pin PTA5
Pawel Zarembski 0:01f31e923fe2 54 // (SDA_SWD_OE on schematic)
Pawel Zarembski 0:01f31e923fe2 55 #define PIN_SWDIO_OE_PORT PORTA
Pawel Zarembski 0:01f31e923fe2 56 #define PIN_SWDIO_OE_GPIO PTA
Pawel Zarembski 0:01f31e923fe2 57 #define PIN_SWDIO_OE_BIT 5
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 // SWD Enable Pin PTA4
Pawel Zarembski 0:01f31e923fe2 60 // (SDA_SWD_EN on schematic)
Pawel Zarembski 0:01f31e923fe2 61 #define PIN_SWD_OE_PORT PORTA
Pawel Zarembski 0:01f31e923fe2 62 #define PIN_SWD_OE_GPIO PTA
Pawel Zarembski 0:01f31e923fe2 63 #define PIN_SWD_OE_BIT 9
Pawel Zarembski 0:01f31e923fe2 64
Pawel Zarembski 0:01f31e923fe2 65 // SWO Input Pin PTC3
Pawel Zarembski 0:01f31e923fe2 66 // (SDA_SWD_SWO on schematic)
Pawel Zarembski 0:01f31e923fe2 67 #define PIN_SWO_RX_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 68 #define PIN_SWO_RX_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 69 #define PIN_SWO_RX_BIT 3
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 // nRESET Pin PTA7
Pawel Zarembski 0:01f31e923fe2 72 #define PIN_nRESET_PORT PORTA
Pawel Zarembski 0:01f31e923fe2 73 #define PIN_nRESET_GPIO PTA
Pawel Zarembski 0:01f31e923fe2 74 #define PIN_nRESET_BIT 7
Pawel Zarembski 0:01f31e923fe2 75 #define PIN_nRESET (1 << PIN_nRESET_BIT)
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 // nRESET Pin Level Shifter Enable PTA6
Pawel Zarembski 0:01f31e923fe2 78 // (SDA_LVLRST_EN on schematic)
Pawel Zarembski 0:01f31e923fe2 79 #define PIN_nRESET_EN_PORT PORTA
Pawel Zarembski 0:01f31e923fe2 80 #define PIN_nRESET_EN_GPIO PTA
Pawel Zarembski 0:01f31e923fe2 81 #define PIN_nRESET_EN_BIT 6
Pawel Zarembski 0:01f31e923fe2 82 #define PIN_nRESET_EN (1 << PIN_nRESET_EN_BIT)
Pawel Zarembski 0:01f31e923fe2 83
Pawel Zarembski 0:01f31e923fe2 84 // SWD Detect Pin PTA8
Pawel Zarembski 0:01f31e923fe2 85 // (x_SWD_DETECT on schematic)
Pawel Zarembski 0:01f31e923fe2 86 #define PIN_SWD_DETECT_PORT PORTA
Pawel Zarembski 0:01f31e923fe2 87 #define PIN_SWD_DETECTGPIO PTA
Pawel Zarembski 0:01f31e923fe2 88 #define PIN_SWD_DETECT_BIT 8
Pawel Zarembski 0:01f31e923fe2 89 #define PIN_SWD_DETECT (1 << PIN_SWD_DETECT_BIT)
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91
Pawel Zarembski 0:01f31e923fe2 92 // Power monitor
Pawel Zarembski 0:01f31e923fe2 93
Pawel Zarembski 0:01f31e923fe2 94 // SDA_G1 Pin PTE17
Pawel Zarembski 0:01f31e923fe2 95 #define PIN_G1_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 96 #define PIN_G1_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 97 #define PIN_G1_BIT 17
Pawel Zarembski 0:01f31e923fe2 98 #define PIN_G1 (1 << PIN_G1_BIT)
Pawel Zarembski 0:01f31e923fe2 99
Pawel Zarembski 0:01f31e923fe2 100 // SDA_G2 Pin PTE18
Pawel Zarembski 0:01f31e923fe2 101 #define PIN_G2_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 102 #define PIN_G2_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 103 #define PIN_G2_BIT 18
Pawel Zarembski 0:01f31e923fe2 104 #define PIN_G2 (1 << PIN_G2_BIT)
Pawel Zarembski 0:01f31e923fe2 105
Pawel Zarembski 0:01f31e923fe2 106 // SDA_LOW_RANGE_EN Pin PTE19
Pawel Zarembski 0:01f31e923fe2 107 #define PIN_LOW_RANGE_EN_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 108 #define PIN_LOW_RANGE_EN_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 109 #define PIN_LOW_RANGE_EN_BIT 19
Pawel Zarembski 0:01f31e923fe2 110 #define PIN_LOW_RANGE_EN (1 << PIN_LOW_RANGE_EN_BIT)
Pawel Zarembski 0:01f31e923fe2 111
Pawel Zarembski 0:01f31e923fe2 112 // SDA_CAL_EN Pin PTE24
Pawel Zarembski 0:01f31e923fe2 113 #define PIN_CAL_EN_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 114 #define PIN_CAL_EN_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 115 #define PIN_CAL_EN_BIT 24
Pawel Zarembski 0:01f31e923fe2 116 #define PIN_CAL_EN (1 << PIN_CAL_EN_BIT)
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118 // SDA_CTRL0 Pin PTE25
Pawel Zarembski 0:01f31e923fe2 119 #define PIN_CTRL0_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 120 #define PIN_CTRL0_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 121 #define PIN_CTRL0_BIT 25
Pawel Zarembski 0:01f31e923fe2 122 #define PIN_CTRL0 (1 << PIN_CTRL0_BIT)
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 // SDA_CTRL1 Pin PTE26
Pawel Zarembski 0:01f31e923fe2 125 #define PIN_CTRL1_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 126 #define PIN_CTRL1_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 127 #define PIN_CTRL1_BIT 26
Pawel Zarembski 0:01f31e923fe2 128 #define PIN_CTRL1 (1 << PIN_CTRL1_BIT)
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 // SDA_CTRL2 Pin PTE27
Pawel Zarembski 0:01f31e923fe2 131 #define PIN_CTRL2_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 132 #define PIN_CTRL2_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 133 #define PIN_CTRL2_BIT 27
Pawel Zarembski 0:01f31e923fe2 134 #define PIN_CTRL2 (1 << PIN_CTRL2_BIT)
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 // SDA_CTRL3 Pin PTE28
Pawel Zarembski 0:01f31e923fe2 137 #define PIN_CTRL3_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 138 #define PIN_CTRL3_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 139 #define PIN_CTRL3_BIT 28
Pawel Zarembski 0:01f31e923fe2 140 #define PIN_CTRL3 (1 << PIN_CTRL3_BIT)
Pawel Zarembski 0:01f31e923fe2 141
Pawel Zarembski 0:01f31e923fe2 142
Pawel Zarembski 0:01f31e923fe2 143 // Misc target connections
Pawel Zarembski 0:01f31e923fe2 144
Pawel Zarembski 0:01f31e923fe2 145 // SDA_GPIO0_B Pin PTB22
Pawel Zarembski 0:01f31e923fe2 146 #define PIN_GPIO0_B_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 147 #define PIN_GPIO0_B_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 148 #define PIN_GPIO0_B_BIT 22
Pawel Zarembski 0:01f31e923fe2 149 #define PIN_GPIO0_B (1 < PIN_GPIO0_B_BIT)
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 // SDA_CLKOUT_B Pin PTC
Pawel Zarembski 0:01f31e923fe2 152 #define PIN_CLKOUT_B_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 153 #define PIN_CLKOUT_B_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 154 #define PIN_CLKOUT_B_BIT 3
Pawel Zarembski 0:01f31e923fe2 155 #define PIN_CLKOUT_B (1 << PIN_CLKOUT_B_BIT)
Pawel Zarembski 0:01f31e923fe2 156
Pawel Zarembski 0:01f31e923fe2 157
Pawel Zarembski 0:01f31e923fe2 158 // Power and fault detection
Pawel Zarembski 0:01f31e923fe2 159
Pawel Zarembski 0:01f31e923fe2 160 // PWR_REG_EN PTE12
Pawel Zarembski 0:01f31e923fe2 161 #define PIN_POWER_EN_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 162 #define PIN_POWER_EN_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 163 #define PIN_POWER_EN_BIT 12
Pawel Zarembski 0:01f31e923fe2 164 #define PIN_POWER_EN (1 << PIN_POWER_EN_BIT)
Pawel Zarembski 0:01f31e923fe2 165
Pawel Zarembski 0:01f31e923fe2 166 // VTRG_FAULT_B PTE11
Pawel Zarembski 0:01f31e923fe2 167 #define PIN_VTRG_FAULT_B_PORT PORTE
Pawel Zarembski 0:01f31e923fe2 168 #define PIN_VTRG_FAULT_B_GPIO PTE
Pawel Zarembski 0:01f31e923fe2 169 #define PIN_VTRG_FAULT_B_BIT 11
Pawel Zarembski 0:01f31e923fe2 170
Pawel Zarembski 0:01f31e923fe2 171 // Debug Unit LEDs
Pawel Zarembski 0:01f31e923fe2 172
Pawel Zarembski 0:01f31e923fe2 173 // Connected LED PTD4
Pawel Zarembski 0:01f31e923fe2 174 #define LED_CONNECTED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 175 #define LED_CONNECTED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 176 #define LED_CONNECTED_BIT 4
Pawel Zarembski 0:01f31e923fe2 177 #define LED_CONNECTED (1 << LED_CONNECTED_BIT)
Pawel Zarembski 0:01f31e923fe2 178
Pawel Zarembski 0:01f31e923fe2 179 // Target Running LED Not available
Pawel Zarembski 0:01f31e923fe2 180
Pawel Zarembski 0:01f31e923fe2 181 // Debug Unit LEDs
Pawel Zarembski 0:01f31e923fe2 182
Pawel Zarembski 0:01f31e923fe2 183 // HID_LED PTD4
Pawel Zarembski 0:01f31e923fe2 184 #define PIN_HID_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 185 #define PIN_HID_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 186 #define PIN_HID_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 187 #define PIN_HID_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 188
Pawel Zarembski 0:01f31e923fe2 189 // MSC_LED PTD4
Pawel Zarembski 0:01f31e923fe2 190 #define PIN_MSC_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 191 #define PIN_MSC_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 192 #define PIN_MSC_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 193 #define PIN_MSC_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 194
Pawel Zarembski 0:01f31e923fe2 195 // CDC_LED PTD4
Pawel Zarembski 0:01f31e923fe2 196 #define PIN_CDC_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 197 #define PIN_CDC_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 198 #define PIN_CDC_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 199 #define PIN_CDC_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 200
Pawel Zarembski 0:01f31e923fe2 201 // SW RESET BUTTON PTB1
Pawel Zarembski 0:01f31e923fe2 202 #define PIN_SW_RESET_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 203 #define PIN_SW_RESET_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 204 #define PIN_SW_RESET_BIT (1)
Pawel Zarembski 0:01f31e923fe2 205 #define PIN_SW_RESET (1<<PIN_SW_RESET_BIT)
Pawel Zarembski 0:01f31e923fe2 206
Pawel Zarembski 0:01f31e923fe2 207 #endif