Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k26f/Driver_USART.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /*
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 5 *
Pawel Zarembski 0:01f31e923fe2 6 * Licensed under the Apache License, Version 2.0 (the License); you may
Pawel Zarembski 0:01f31e923fe2 7 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 8 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 11 *
Pawel Zarembski 0:01f31e923fe2 12 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 15 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 16 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 17 *
Pawel Zarembski 0:01f31e923fe2 18 * $Date: 2. Feb 2017
Pawel Zarembski 0:01f31e923fe2 19 * $Revision: V2.3
Pawel Zarembski 0:01f31e923fe2 20 *
Pawel Zarembski 0:01f31e923fe2 21 * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter)
Pawel Zarembski 0:01f31e923fe2 22 * Driver definitions
Pawel Zarembski 0:01f31e923fe2 23 */
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 /* History:
Pawel Zarembski 0:01f31e923fe2 26 * Version 2.3
Pawel Zarembski 0:01f31e923fe2 27 * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
Pawel Zarembski 0:01f31e923fe2 28 * Version 2.2
Pawel Zarembski 0:01f31e923fe2 29 * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
Pawel Zarembski 0:01f31e923fe2 30 * Version 2.1
Pawel Zarembski 0:01f31e923fe2 31 * Removed optional argument parameter from Signal Event
Pawel Zarembski 0:01f31e923fe2 32 * Version 2.0
Pawel Zarembski 0:01f31e923fe2 33 * New simplified driver:
Pawel Zarembski 0:01f31e923fe2 34 * complexity moved to upper layer (especially data handling)
Pawel Zarembski 0:01f31e923fe2 35 * more unified API for different communication interfaces
Pawel Zarembski 0:01f31e923fe2 36 * renamed driver UART -> USART (Asynchronous & Synchronous)
Pawel Zarembski 0:01f31e923fe2 37 * Added modes:
Pawel Zarembski 0:01f31e923fe2 38 * Synchronous
Pawel Zarembski 0:01f31e923fe2 39 * Single-wire
Pawel Zarembski 0:01f31e923fe2 40 * IrDA
Pawel Zarembski 0:01f31e923fe2 41 * Smart Card
Pawel Zarembski 0:01f31e923fe2 42 * Changed prefix ARM_DRV -> ARM_DRIVER
Pawel Zarembski 0:01f31e923fe2 43 * Version 1.10
Pawel Zarembski 0:01f31e923fe2 44 * Namespace prefix ARM_ added
Pawel Zarembski 0:01f31e923fe2 45 * Version 1.01
Pawel Zarembski 0:01f31e923fe2 46 * Added events:
Pawel Zarembski 0:01f31e923fe2 47 * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT
Pawel Zarembski 0:01f31e923fe2 48 * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
Pawel Zarembski 0:01f31e923fe2 49 * Added functions: SetTxThreshold, SetRxThreshold
Pawel Zarembski 0:01f31e923fe2 50 * Added "rx_timeout_event" to capabilities
Pawel Zarembski 0:01f31e923fe2 51 * Version 1.00
Pawel Zarembski 0:01f31e923fe2 52 * Initial release
Pawel Zarembski 0:01f31e923fe2 53 */
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 #ifndef DRIVER_USART_H_
Pawel Zarembski 0:01f31e923fe2 56 #define DRIVER_USART_H_
Pawel Zarembski 0:01f31e923fe2 57
Pawel Zarembski 0:01f31e923fe2 58 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 59 extern "C"
Pawel Zarembski 0:01f31e923fe2 60 {
Pawel Zarembski 0:01f31e923fe2 61 #endif
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 #include "Driver_Common.h"
Pawel Zarembski 0:01f31e923fe2 64
Pawel Zarembski 0:01f31e923fe2 65 #define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67
Pawel Zarembski 0:01f31e923fe2 68 /****** USART Control Codes *****/
Pawel Zarembski 0:01f31e923fe2 69
Pawel Zarembski 0:01f31e923fe2 70 #define ARM_USART_CONTROL_Pos 0
Pawel Zarembski 0:01f31e923fe2 71 #define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos)
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 /*----- USART Control Codes: Mode -----*/
Pawel Zarembski 0:01f31e923fe2 74 #define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate
Pawel Zarembski 0:01f31e923fe2 75 #define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate
Pawel Zarembski 0:01f31e923fe2 76 #define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal)
Pawel Zarembski 0:01f31e923fe2 77 #define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate
Pawel Zarembski 0:01f31e923fe2 78 #define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate
Pawel Zarembski 0:01f31e923fe2 79 #define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 /*----- USART Control Codes: Mode Parameters: Data Bits -----*/
Pawel Zarembski 0:01f31e923fe2 82 #define ARM_USART_DATA_BITS_Pos 8
Pawel Zarembski 0:01f31e923fe2 83 #define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos)
Pawel Zarembski 0:01f31e923fe2 84 #define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits
Pawel Zarembski 0:01f31e923fe2 85 #define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit
Pawel Zarembski 0:01f31e923fe2 86 #define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits
Pawel Zarembski 0:01f31e923fe2 87 #define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default)
Pawel Zarembski 0:01f31e923fe2 88 #define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits
Pawel Zarembski 0:01f31e923fe2 89
Pawel Zarembski 0:01f31e923fe2 90 /*----- USART Control Codes: Mode Parameters: Parity -----*/
Pawel Zarembski 0:01f31e923fe2 91 #define ARM_USART_PARITY_Pos 12
Pawel Zarembski 0:01f31e923fe2 92 #define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos)
Pawel Zarembski 0:01f31e923fe2 93 #define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default)
Pawel Zarembski 0:01f31e923fe2 94 #define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity
Pawel Zarembski 0:01f31e923fe2 95 #define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97 /*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
Pawel Zarembski 0:01f31e923fe2 98 #define ARM_USART_STOP_BITS_Pos 14
Pawel Zarembski 0:01f31e923fe2 99 #define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos)
Pawel Zarembski 0:01f31e923fe2 100 #define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default)
Pawel Zarembski 0:01f31e923fe2 101 #define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits
Pawel Zarembski 0:01f31e923fe2 102 #define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits
Pawel Zarembski 0:01f31e923fe2 103 #define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 /*----- USART Control Codes: Mode Parameters: Flow Control -----*/
Pawel Zarembski 0:01f31e923fe2 106 #define ARM_USART_FLOW_CONTROL_Pos 16
Pawel Zarembski 0:01f31e923fe2 107 #define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos)
Pawel Zarembski 0:01f31e923fe2 108 #define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
Pawel Zarembski 0:01f31e923fe2 109 #define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
Pawel Zarembski 0:01f31e923fe2 110 #define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
Pawel Zarembski 0:01f31e923fe2 111 #define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 /*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
Pawel Zarembski 0:01f31e923fe2 114 #define ARM_USART_CPOL_Pos 18
Pawel Zarembski 0:01f31e923fe2 115 #define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos)
Pawel Zarembski 0:01f31e923fe2 116 #define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default)
Pawel Zarembski 0:01f31e923fe2 117 #define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1
Pawel Zarembski 0:01f31e923fe2 118
Pawel Zarembski 0:01f31e923fe2 119 /*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
Pawel Zarembski 0:01f31e923fe2 120 #define ARM_USART_CPHA_Pos 19
Pawel Zarembski 0:01f31e923fe2 121 #define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos)
Pawel Zarembski 0:01f31e923fe2 122 #define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default)
Pawel Zarembski 0:01f31e923fe2 123 #define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1
Pawel Zarembski 0:01f31e923fe2 124
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126 /*----- USART Control Codes: Miscellaneous Controls -----*/
Pawel Zarembski 0:01f31e923fe2 127 #define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value
Pawel Zarembski 0:01f31e923fe2 128 #define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
Pawel Zarembski 0:01f31e923fe2 129 #define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods
Pawel Zarembski 0:01f31e923fe2 130 #define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
Pawel Zarembski 0:01f31e923fe2 131 #define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
Pawel Zarembski 0:01f31e923fe2 132 #define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled
Pawel Zarembski 0:01f31e923fe2 133 #define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled
Pawel Zarembski 0:01f31e923fe2 134 #define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
Pawel Zarembski 0:01f31e923fe2 135 #define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send
Pawel Zarembski 0:01f31e923fe2 136 #define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive
Pawel Zarembski 0:01f31e923fe2 137 #define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer
Pawel Zarembski 0:01f31e923fe2 138
Pawel Zarembski 0:01f31e923fe2 139
Pawel Zarembski 0:01f31e923fe2 140
Pawel Zarembski 0:01f31e923fe2 141 /****** USART specific error codes *****/
Pawel Zarembski 0:01f31e923fe2 142 #define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
Pawel Zarembski 0:01f31e923fe2 143 #define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported
Pawel Zarembski 0:01f31e923fe2 144 #define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
Pawel Zarembski 0:01f31e923fe2 145 #define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported
Pawel Zarembski 0:01f31e923fe2 146 #define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported
Pawel Zarembski 0:01f31e923fe2 147 #define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported
Pawel Zarembski 0:01f31e923fe2 148 #define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported
Pawel Zarembski 0:01f31e923fe2 149 #define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151
Pawel Zarembski 0:01f31e923fe2 152 /**
Pawel Zarembski 0:01f31e923fe2 153 \brief USART Status
Pawel Zarembski 0:01f31e923fe2 154 */
Pawel Zarembski 0:01f31e923fe2 155 typedef volatile struct _ARM_USART_STATUS {
Pawel Zarembski 0:01f31e923fe2 156 uint32_t tx_busy : 1; ///< Transmitter busy flag
Pawel Zarembski 0:01f31e923fe2 157 uint32_t rx_busy : 1; ///< Receiver busy flag
Pawel Zarembski 0:01f31e923fe2 158 uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
Pawel Zarembski 0:01f31e923fe2 159 uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
Pawel Zarembski 0:01f31e923fe2 160 uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
Pawel Zarembski 0:01f31e923fe2 161 uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
Pawel Zarembski 0:01f31e923fe2 162 uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
Pawel Zarembski 0:01f31e923fe2 163 uint32_t reserved : 25;
Pawel Zarembski 0:01f31e923fe2 164 } ARM_USART_STATUS;
Pawel Zarembski 0:01f31e923fe2 165
Pawel Zarembski 0:01f31e923fe2 166 /**
Pawel Zarembski 0:01f31e923fe2 167 \brief USART Modem Control
Pawel Zarembski 0:01f31e923fe2 168 */
Pawel Zarembski 0:01f31e923fe2 169 typedef enum _ARM_USART_MODEM_CONTROL {
Pawel Zarembski 0:01f31e923fe2 170 ARM_USART_RTS_CLEAR, ///< Deactivate RTS
Pawel Zarembski 0:01f31e923fe2 171 ARM_USART_RTS_SET, ///< Activate RTS
Pawel Zarembski 0:01f31e923fe2 172 ARM_USART_DTR_CLEAR, ///< Deactivate DTR
Pawel Zarembski 0:01f31e923fe2 173 ARM_USART_DTR_SET ///< Activate DTR
Pawel Zarembski 0:01f31e923fe2 174 } ARM_USART_MODEM_CONTROL;
Pawel Zarembski 0:01f31e923fe2 175
Pawel Zarembski 0:01f31e923fe2 176 /**
Pawel Zarembski 0:01f31e923fe2 177 \brief USART Modem Status
Pawel Zarembski 0:01f31e923fe2 178 */
Pawel Zarembski 0:01f31e923fe2 179 typedef volatile struct _ARM_USART_MODEM_STATUS {
Pawel Zarembski 0:01f31e923fe2 180 uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
Pawel Zarembski 0:01f31e923fe2 181 uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
Pawel Zarembski 0:01f31e923fe2 182 uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
Pawel Zarembski 0:01f31e923fe2 183 uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
Pawel Zarembski 0:01f31e923fe2 184 uint32_t reserved : 28;
Pawel Zarembski 0:01f31e923fe2 185 } ARM_USART_MODEM_STATUS;
Pawel Zarembski 0:01f31e923fe2 186
Pawel Zarembski 0:01f31e923fe2 187
Pawel Zarembski 0:01f31e923fe2 188 /****** USART Event *****/
Pawel Zarembski 0:01f31e923fe2 189 #define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data
Pawel Zarembski 0:01f31e923fe2 190 #define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
Pawel Zarembski 0:01f31e923fe2 191 #define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed
Pawel Zarembski 0:01f31e923fe2 192 #define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional)
Pawel Zarembski 0:01f31e923fe2 193 #define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave)
Pawel Zarembski 0:01f31e923fe2 194 #define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow
Pawel Zarembski 0:01f31e923fe2 195 #define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional)
Pawel Zarembski 0:01f31e923fe2 196 #define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive
Pawel Zarembski 0:01f31e923fe2 197 #define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive
Pawel Zarembski 0:01f31e923fe2 198 #define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive
Pawel Zarembski 0:01f31e923fe2 199 #define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional)
Pawel Zarembski 0:01f31e923fe2 200 #define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional)
Pawel Zarembski 0:01f31e923fe2 201 #define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional)
Pawel Zarembski 0:01f31e923fe2 202 #define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional)
Pawel Zarembski 0:01f31e923fe2 203
Pawel Zarembski 0:01f31e923fe2 204
Pawel Zarembski 0:01f31e923fe2 205 // Function documentation
Pawel Zarembski 0:01f31e923fe2 206 /**
Pawel Zarembski 0:01f31e923fe2 207 \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
Pawel Zarembski 0:01f31e923fe2 208 \brief Get driver version.
Pawel Zarembski 0:01f31e923fe2 209 \return \ref ARM_DRIVER_VERSION
Pawel Zarembski 0:01f31e923fe2 210
Pawel Zarembski 0:01f31e923fe2 211 \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
Pawel Zarembski 0:01f31e923fe2 212 \brief Get driver capabilities
Pawel Zarembski 0:01f31e923fe2 213 \return \ref ARM_USART_CAPABILITIES
Pawel Zarembski 0:01f31e923fe2 214
Pawel Zarembski 0:01f31e923fe2 215 \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
Pawel Zarembski 0:01f31e923fe2 216 \brief Initialize USART Interface.
Pawel Zarembski 0:01f31e923fe2 217 \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent
Pawel Zarembski 0:01f31e923fe2 218 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 219
Pawel Zarembski 0:01f31e923fe2 220 \fn int32_t ARM_USART_Uninitialize (void)
Pawel Zarembski 0:01f31e923fe2 221 \brief De-initialize USART Interface.
Pawel Zarembski 0:01f31e923fe2 222 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 223
Pawel Zarembski 0:01f31e923fe2 224 \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
Pawel Zarembski 0:01f31e923fe2 225 \brief Control USART Interface Power.
Pawel Zarembski 0:01f31e923fe2 226 \param[in] state Power state
Pawel Zarembski 0:01f31e923fe2 227 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 228
Pawel Zarembski 0:01f31e923fe2 229 \fn int32_t ARM_USART_Send (const void *data, uint32_t num)
Pawel Zarembski 0:01f31e923fe2 230 \brief Start sending data to USART transmitter.
Pawel Zarembski 0:01f31e923fe2 231 \param[in] data Pointer to buffer with data to send to USART transmitter
Pawel Zarembski 0:01f31e923fe2 232 \param[in] num Number of data items to send
Pawel Zarembski 0:01f31e923fe2 233 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 234
Pawel Zarembski 0:01f31e923fe2 235 \fn int32_t ARM_USART_Receive (void *data, uint32_t num)
Pawel Zarembski 0:01f31e923fe2 236 \brief Start receiving data from USART receiver.
Pawel Zarembski 0:01f31e923fe2 237 \param[out] data Pointer to buffer for data to receive from USART receiver
Pawel Zarembski 0:01f31e923fe2 238 \param[in] num Number of data items to receive
Pawel Zarembski 0:01f31e923fe2 239 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 240
Pawel Zarembski 0:01f31e923fe2 241 \fn int32_t ARM_USART_Transfer (const void *data_out,
Pawel Zarembski 0:01f31e923fe2 242 void *data_in,
Pawel Zarembski 0:01f31e923fe2 243 uint32_t num)
Pawel Zarembski 0:01f31e923fe2 244 \brief Start sending/receiving data to/from USART transmitter/receiver.
Pawel Zarembski 0:01f31e923fe2 245 \param[in] data_out Pointer to buffer with data to send to USART transmitter
Pawel Zarembski 0:01f31e923fe2 246 \param[out] data_in Pointer to buffer for data to receive from USART receiver
Pawel Zarembski 0:01f31e923fe2 247 \param[in] num Number of data items to transfer
Pawel Zarembski 0:01f31e923fe2 248 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 249
Pawel Zarembski 0:01f31e923fe2 250 \fn uint32_t ARM_USART_GetTxCount (void)
Pawel Zarembski 0:01f31e923fe2 251 \brief Get transmitted data count.
Pawel Zarembski 0:01f31e923fe2 252 \return number of data items transmitted
Pawel Zarembski 0:01f31e923fe2 253
Pawel Zarembski 0:01f31e923fe2 254 \fn uint32_t ARM_USART_GetRxCount (void)
Pawel Zarembski 0:01f31e923fe2 255 \brief Get received data count.
Pawel Zarembski 0:01f31e923fe2 256 \return number of data items received
Pawel Zarembski 0:01f31e923fe2 257
Pawel Zarembski 0:01f31e923fe2 258 \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
Pawel Zarembski 0:01f31e923fe2 259 \brief Control USART Interface.
Pawel Zarembski 0:01f31e923fe2 260 \param[in] control Operation
Pawel Zarembski 0:01f31e923fe2 261 \param[in] arg Argument of operation (optional)
Pawel Zarembski 0:01f31e923fe2 262 \return common \ref execution_status and driver specific \ref usart_execution_status
Pawel Zarembski 0:01f31e923fe2 263
Pawel Zarembski 0:01f31e923fe2 264 \fn ARM_USART_STATUS ARM_USART_GetStatus (void)
Pawel Zarembski 0:01f31e923fe2 265 \brief Get USART status.
Pawel Zarembski 0:01f31e923fe2 266 \return USART status \ref ARM_USART_STATUS
Pawel Zarembski 0:01f31e923fe2 267
Pawel Zarembski 0:01f31e923fe2 268 \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
Pawel Zarembski 0:01f31e923fe2 269 \brief Set USART Modem Control line state.
Pawel Zarembski 0:01f31e923fe2 270 \param[in] control \ref ARM_USART_MODEM_CONTROL
Pawel Zarembski 0:01f31e923fe2 271 \return \ref execution_status
Pawel Zarembski 0:01f31e923fe2 272
Pawel Zarembski 0:01f31e923fe2 273 \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
Pawel Zarembski 0:01f31e923fe2 274 \brief Get USART Modem Status lines state.
Pawel Zarembski 0:01f31e923fe2 275 \return modem status \ref ARM_USART_MODEM_STATUS
Pawel Zarembski 0:01f31e923fe2 276
Pawel Zarembski 0:01f31e923fe2 277 \fn void ARM_USART_SignalEvent (uint32_t event)
Pawel Zarembski 0:01f31e923fe2 278 \brief Signal USART Events.
Pawel Zarembski 0:01f31e923fe2 279 \param[in] event \ref USART_events notification mask
Pawel Zarembski 0:01f31e923fe2 280 \return none
Pawel Zarembski 0:01f31e923fe2 281 */
Pawel Zarembski 0:01f31e923fe2 282
Pawel Zarembski 0:01f31e923fe2 283 typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
Pawel Zarembski 0:01f31e923fe2 284
Pawel Zarembski 0:01f31e923fe2 285
Pawel Zarembski 0:01f31e923fe2 286 /**
Pawel Zarembski 0:01f31e923fe2 287 \brief USART Device Driver Capabilities.
Pawel Zarembski 0:01f31e923fe2 288 */
Pawel Zarembski 0:01f31e923fe2 289 typedef struct _ARM_USART_CAPABILITIES {
Pawel Zarembski 0:01f31e923fe2 290 uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
Pawel Zarembski 0:01f31e923fe2 291 uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
Pawel Zarembski 0:01f31e923fe2 292 uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
Pawel Zarembski 0:01f31e923fe2 293 uint32_t single_wire : 1; ///< supports UART Single-wire mode
Pawel Zarembski 0:01f31e923fe2 294 uint32_t irda : 1; ///< supports UART IrDA mode
Pawel Zarembski 0:01f31e923fe2 295 uint32_t smart_card : 1; ///< supports UART Smart Card mode
Pawel Zarembski 0:01f31e923fe2 296 uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
Pawel Zarembski 0:01f31e923fe2 297 uint32_t flow_control_rts : 1; ///< RTS Flow Control available
Pawel Zarembski 0:01f31e923fe2 298 uint32_t flow_control_cts : 1; ///< CTS Flow Control available
Pawel Zarembski 0:01f31e923fe2 299 uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
Pawel Zarembski 0:01f31e923fe2 300 uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
Pawel Zarembski 0:01f31e923fe2 301 uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
Pawel Zarembski 0:01f31e923fe2 302 uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
Pawel Zarembski 0:01f31e923fe2 303 uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
Pawel Zarembski 0:01f31e923fe2 304 uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
Pawel Zarembski 0:01f31e923fe2 305 uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
Pawel Zarembski 0:01f31e923fe2 306 uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
Pawel Zarembski 0:01f31e923fe2 307 uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
Pawel Zarembski 0:01f31e923fe2 308 uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
Pawel Zarembski 0:01f31e923fe2 309 uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
Pawel Zarembski 0:01f31e923fe2 310 uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI
Pawel Zarembski 0:01f31e923fe2 311 uint32_t reserved : 11; ///< Reserved (must be zero)
Pawel Zarembski 0:01f31e923fe2 312 } ARM_USART_CAPABILITIES;
Pawel Zarembski 0:01f31e923fe2 313
Pawel Zarembski 0:01f31e923fe2 314
Pawel Zarembski 0:01f31e923fe2 315 /**
Pawel Zarembski 0:01f31e923fe2 316 \brief Access structure of the USART Driver.
Pawel Zarembski 0:01f31e923fe2 317 */
Pawel Zarembski 0:01f31e923fe2 318 typedef struct _ARM_DRIVER_USART {
Pawel Zarembski 0:01f31e923fe2 319 ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
Pawel Zarembski 0:01f31e923fe2 320 ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
Pawel Zarembski 0:01f31e923fe2 321 int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
Pawel Zarembski 0:01f31e923fe2 322 int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
Pawel Zarembski 0:01f31e923fe2 323 int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
Pawel Zarembski 0:01f31e923fe2 324 int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
Pawel Zarembski 0:01f31e923fe2 325 int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
Pawel Zarembski 0:01f31e923fe2 326 int32_t (*Transfer) (const void *data_out,
Pawel Zarembski 0:01f31e923fe2 327 void *data_in,
Pawel Zarembski 0:01f31e923fe2 328 uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
Pawel Zarembski 0:01f31e923fe2 329 uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
Pawel Zarembski 0:01f31e923fe2 330 uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
Pawel Zarembski 0:01f31e923fe2 331 int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
Pawel Zarembski 0:01f31e923fe2 332 ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
Pawel Zarembski 0:01f31e923fe2 333 int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
Pawel Zarembski 0:01f31e923fe2 334 ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
Pawel Zarembski 0:01f31e923fe2 335 } const ARM_DRIVER_USART;
Pawel Zarembski 0:01f31e923fe2 336
Pawel Zarembski 0:01f31e923fe2 337 #ifdef __cplusplus
Pawel Zarembski 0:01f31e923fe2 338 }
Pawel Zarembski 0:01f31e923fe2 339 #endif
Pawel Zarembski 0:01f31e923fe2 340
Pawel Zarembski 0:01f31e923fe2 341 #endif /* DRIVER_USART_H_ */