Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k26f/DAP_config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file DAP_config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #ifndef __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 23 #define __DAP_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 24
Pawel Zarembski 0:01f31e923fe2 25 #include "IO_Config.h"
Pawel Zarembski 0:01f31e923fe2 26
Pawel Zarembski 0:01f31e923fe2 27 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 28 /**
Pawel Zarembski 0:01f31e923fe2 29 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
Pawel Zarembski 0:01f31e923fe2 30 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 31 @{
Pawel Zarembski 0:01f31e923fe2 32 Provides definitions about the hardware and configuration of the Debug Unit.
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 This information includes:
Pawel Zarembski 0:01f31e923fe2 35 - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 36 - Debug Unit communication packet size.
Pawel Zarembski 0:01f31e923fe2 37 - Debug Access Port communication mode (JTAG or SWD).
Pawel Zarembski 0:01f31e923fe2 38 - Optional information about a connected Target Device (for Evaluation Boards).
Pawel Zarembski 0:01f31e923fe2 39 */
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 #include "fsl_device_registers.h" // Debug Unit Cortex-M Processor Header File
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
Pawel Zarembski 0:01f31e923fe2 44 /// This value is used to calculate the SWD/JTAG clock speed.
Pawel Zarembski 0:01f31e923fe2 45 #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 /// Number of processor cycles for I/O Port write operations.
Pawel Zarembski 0:01f31e923fe2 48 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
Pawel Zarembski 0:01f31e923fe2 49 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
Pawel Zarembski 0:01f31e923fe2 50 /// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
Pawel Zarembski 0:01f31e923fe2 51 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
Pawel Zarembski 0:01f31e923fe2 52 /// required.
Pawel Zarembski 0:01f31e923fe2 53 #define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 56 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 57 #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 58
Pawel Zarembski 0:01f31e923fe2 59 /// Indicate that JTAG communication mode is available at the Debug Port.
Pawel Zarembski 0:01f31e923fe2 60 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 61 #define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 64 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
Pawel Zarembski 0:01f31e923fe2 65 #define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 /// Default communication mode on the Debug Access Port.
Pawel Zarembski 0:01f31e923fe2 68 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
Pawel Zarembski 0:01f31e923fe2 69 #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
Pawel Zarembski 0:01f31e923fe2 70
Pawel Zarembski 0:01f31e923fe2 71 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
Pawel Zarembski 0:01f31e923fe2 72 /// Used to initialize the default SWD/JTAG clock frequency.
Pawel Zarembski 0:01f31e923fe2 73 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
Pawel Zarembski 0:01f31e923fe2 74 #define DAP_DEFAULT_SWJ_CLOCK 4000000 ///< Default SWD/JTAG clock frequency in Hz.
Pawel Zarembski 0:01f31e923fe2 75
Pawel Zarembski 0:01f31e923fe2 76 /// Maximum Package Size for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 77 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 78 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 79 #ifndef HID_ENDPOINT //HID end points currently set limits to 64
Pawel Zarembski 0:01f31e923fe2 80 #define DAP_PACKET_SIZE 512 ///< USB: 64 = Full-Speed, 512 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 81 #else
Pawel Zarembski 0:01f31e923fe2 82 #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 512 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 83 #endif
Pawel Zarembski 0:01f31e923fe2 84
Pawel Zarembski 0:01f31e923fe2 85 /// Maximum Package Buffers for Command and Response data.
Pawel Zarembski 0:01f31e923fe2 86 /// This configuration settings is used to optimized the communication performance with the
Pawel Zarembski 0:01f31e923fe2 87 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
Pawel Zarembski 0:01f31e923fe2 88 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
Pawel Zarembski 0:01f31e923fe2 89 #define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
Pawel Zarembski 0:01f31e923fe2 90
Pawel Zarembski 0:01f31e923fe2 91 /// Indicate that UART Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 92 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 93 #define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 94
Pawel Zarembski 0:01f31e923fe2 95 /// Maximum SWO UART Baudrate
Pawel Zarembski 0:01f31e923fe2 96 #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
Pawel Zarembski 0:01f31e923fe2 97
Pawel Zarembski 0:01f31e923fe2 98 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
Pawel Zarembski 0:01f31e923fe2 99 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
Pawel Zarembski 0:01f31e923fe2 100 #define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
Pawel Zarembski 0:01f31e923fe2 101
Pawel Zarembski 0:01f31e923fe2 102 /// SWO Trace Buffer Size.
Pawel Zarembski 0:01f31e923fe2 103 #define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 #define SWO_USART_PORT 1 ///< UART1 is used for the SWO UART.
Pawel Zarembski 0:01f31e923fe2 106
Pawel Zarembski 0:01f31e923fe2 107 /// SWO Streaming Trace.
Pawel Zarembski 0:01f31e923fe2 108 #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
Pawel Zarembski 0:01f31e923fe2 109
Pawel Zarembski 0:01f31e923fe2 110 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
Pawel Zarembski 0:01f31e923fe2 111 #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
Pawel Zarembski 0:01f31e923fe2 112
Pawel Zarembski 0:01f31e923fe2 113 /// Debug Unit is connected to fixed Target Device.
Pawel Zarembski 0:01f31e923fe2 114 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
Pawel Zarembski 0:01f31e923fe2 115 /// known device. In this case a Device Vendor and Device Name string is stored which
Pawel Zarembski 0:01f31e923fe2 116 /// may be used by the debugger or IDE to configure device parameters.
Pawel Zarembski 0:01f31e923fe2 117 #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
Pawel Zarembski 0:01f31e923fe2 118
Pawel Zarembski 0:01f31e923fe2 119 #if TARGET_DEVICE_FIXED
Pawel Zarembski 0:01f31e923fe2 120 #define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
Pawel Zarembski 0:01f31e923fe2 121 #define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
Pawel Zarembski 0:01f31e923fe2 122 #endif
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 ///@}
Pawel Zarembski 0:01f31e923fe2 125
Pawel Zarembski 0:01f31e923fe2 126 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 127 /**
Pawel Zarembski 0:01f31e923fe2 128 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
Pawel Zarembski 0:01f31e923fe2 129 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 130 @{
Pawel Zarembski 0:01f31e923fe2 131
Pawel Zarembski 0:01f31e923fe2 132 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
Pawel Zarembski 0:01f31e923fe2 133 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
Pawel Zarembski 0:01f31e923fe2 134 interface of a device. The following I/O Pins are provided:
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
Pawel Zarembski 0:01f31e923fe2 137 ---------------------------- | -------------------- | ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 138 TCK: Test Clock | SWCLK: Clock | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 139 TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
Pawel Zarembski 0:01f31e923fe2 140 TDI: Test Data Input | | Output Push/Pull
Pawel Zarembski 0:01f31e923fe2 141 TDO: Test Data Output | | Input
Pawel Zarembski 0:01f31e923fe2 142 nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 143 nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
Pawel Zarembski 0:01f31e923fe2 144
Pawel Zarembski 0:01f31e923fe2 145
Pawel Zarembski 0:01f31e923fe2 146 DAP Hardware I/O Pin Access Functions
Pawel Zarembski 0:01f31e923fe2 147 -------------------------------------
Pawel Zarembski 0:01f31e923fe2 148 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
Pawel Zarembski 0:01f31e923fe2 149 these I/O Pins.
Pawel Zarembski 0:01f31e923fe2 150
Pawel Zarembski 0:01f31e923fe2 151 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
Pawel Zarembski 0:01f31e923fe2 152 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
Pawel Zarembski 0:01f31e923fe2 153 peripherals that can independently write/read a single I/O pin without affecting any other pins
Pawel Zarembski 0:01f31e923fe2 154 of the same I/O port. The following SWDIO I/O Pin functions are provided:
Pawel Zarembski 0:01f31e923fe2 155 - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 156 - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
Pawel Zarembski 0:01f31e923fe2 157 - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 158 - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
Pawel Zarembski 0:01f31e923fe2 159 */
Pawel Zarembski 0:01f31e923fe2 160
Pawel Zarembski 0:01f31e923fe2 161
Pawel Zarembski 0:01f31e923fe2 162 // Configure DAP I/O pins ------------------------------
Pawel Zarembski 0:01f31e923fe2 163
Pawel Zarembski 0:01f31e923fe2 164 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Pawel Zarembski 0:01f31e923fe2 165 Configures the DAP Hardware I/O pins for JTAG mode:
Pawel Zarembski 0:01f31e923fe2 166 - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
Pawel Zarembski 0:01f31e923fe2 167 - TDO to input mode.
Pawel Zarembski 0:01f31e923fe2 168 */
Pawel Zarembski 0:01f31e923fe2 169 static inline void PORT_JTAG_SETUP(void) {}
Pawel Zarembski 0:01f31e923fe2 170
Pawel Zarembski 0:01f31e923fe2 171 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Pawel Zarembski 0:01f31e923fe2 172 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
Pawel Zarembski 0:01f31e923fe2 173 - SWCLK, SWDIO, nRESET to output mode and set to default high level.
Pawel Zarembski 0:01f31e923fe2 174 - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
Pawel Zarembski 0:01f31e923fe2 175 */
Pawel Zarembski 0:01f31e923fe2 176 static inline void PORT_SWD_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 177 {
Pawel Zarembski 0:01f31e923fe2 178 PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
Pawel Zarembski 0:01f31e923fe2 179 PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
Pawel Zarembski 0:01f31e923fe2 180 PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT;
Pawel Zarembski 0:01f31e923fe2 181 PIN_SWD_OE_GPIO->PSOR = 1 << PIN_SWD_OE_BIT;
Pawel Zarembski 0:01f31e923fe2 182 PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT;
Pawel Zarembski 0:01f31e923fe2 183 PIN_SWD_OE_GPIO->PDDR = PIN_SWD_OE_GPIO->PDDR | (1 << PIN_SWD_OE_BIT);
Pawel Zarembski 0:01f31e923fe2 184 PIN_nRESET_GPIO->PSOR = PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 185 PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output
Pawel Zarembski 0:01f31e923fe2 186 PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 187 }
Pawel Zarembski 0:01f31e923fe2 188
Pawel Zarembski 0:01f31e923fe2 189 /** Disable JTAG/SWD I/O Pins.
Pawel Zarembski 0:01f31e923fe2 190 Disables the DAP Hardware I/O pins which configures:
Pawel Zarembski 0:01f31e923fe2 191 - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
Pawel Zarembski 0:01f31e923fe2 192 */
Pawel Zarembski 0:01f31e923fe2 193 static inline void PORT_OFF(void)
Pawel Zarembski 0:01f31e923fe2 194 {
Pawel Zarembski 0:01f31e923fe2 195 PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT;
Pawel Zarembski 0:01f31e923fe2 196 PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT;
Pawel Zarembski 0:01f31e923fe2 197 PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT;
Pawel Zarembski 0:01f31e923fe2 198 PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input
Pawel Zarembski 0:01f31e923fe2 199 PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
Pawel Zarembski 0:01f31e923fe2 200 PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 201 }
Pawel Zarembski 0:01f31e923fe2 202
Pawel Zarembski 0:01f31e923fe2 203
Pawel Zarembski 0:01f31e923fe2 204 // SWCLK/TCK I/O pin -------------------------------------
Pawel Zarembski 0:01f31e923fe2 205
Pawel Zarembski 0:01f31e923fe2 206 /** SWCLK/TCK I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 207 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 208 */
Pawel Zarembski 0:01f31e923fe2 209 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
Pawel Zarembski 0:01f31e923fe2 210 {
Pawel Zarembski 0:01f31e923fe2 211 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 212 }
Pawel Zarembski 0:01f31e923fe2 213
Pawel Zarembski 0:01f31e923fe2 214 /** SWCLK/TCK I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 215 Set the SWCLK/TCK DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 216 */
Pawel Zarembski 0:01f31e923fe2 217 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
Pawel Zarembski 0:01f31e923fe2 218 {
Pawel Zarembski 0:01f31e923fe2 219 PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
Pawel Zarembski 0:01f31e923fe2 220 }
Pawel Zarembski 0:01f31e923fe2 221
Pawel Zarembski 0:01f31e923fe2 222 /** SWCLK/TCK I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 223 Set the SWCLK/TCK DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 224 */
Pawel Zarembski 0:01f31e923fe2 225 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
Pawel Zarembski 0:01f31e923fe2 226 {
Pawel Zarembski 0:01f31e923fe2 227 PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT;
Pawel Zarembski 0:01f31e923fe2 228 }
Pawel Zarembski 0:01f31e923fe2 229
Pawel Zarembski 0:01f31e923fe2 230
Pawel Zarembski 0:01f31e923fe2 231 // SWDIO/TMS Pin I/O --------------------------------------
Pawel Zarembski 0:01f31e923fe2 232
Pawel Zarembski 0:01f31e923fe2 233 /** SWDIO/TMS I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 234 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 235 */
Pawel Zarembski 0:01f31e923fe2 236 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
Pawel Zarembski 0:01f31e923fe2 237 {
Pawel Zarembski 0:01f31e923fe2 238 return ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1);
Pawel Zarembski 0:01f31e923fe2 239 }
Pawel Zarembski 0:01f31e923fe2 240
Pawel Zarembski 0:01f31e923fe2 241 /** SWDIO/TMS I/O pin: Set Output to High.
Pawel Zarembski 0:01f31e923fe2 242 Set the SWDIO/TMS DAP hardware I/O pin to high level.
Pawel Zarembski 0:01f31e923fe2 243 */
Pawel Zarembski 0:01f31e923fe2 244 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
Pawel Zarembski 0:01f31e923fe2 245 {
Pawel Zarembski 0:01f31e923fe2 246 PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
Pawel Zarembski 0:01f31e923fe2 247 }
Pawel Zarembski 0:01f31e923fe2 248
Pawel Zarembski 0:01f31e923fe2 249 /** SWDIO/TMS I/O pin: Set Output to Low.
Pawel Zarembski 0:01f31e923fe2 250 Set the SWDIO/TMS DAP hardware I/O pin to low level.
Pawel Zarembski 0:01f31e923fe2 251 */
Pawel Zarembski 0:01f31e923fe2 252 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
Pawel Zarembski 0:01f31e923fe2 253 {
Pawel Zarembski 0:01f31e923fe2 254 PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT;
Pawel Zarembski 0:01f31e923fe2 255 }
Pawel Zarembski 0:01f31e923fe2 256
Pawel Zarembski 0:01f31e923fe2 257 /** SWDIO I/O pin: Get Input (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 258 \return Current status of the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 259 */
Pawel Zarembski 0:01f31e923fe2 260 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
Pawel Zarembski 0:01f31e923fe2 261 {
Pawel Zarembski 0:01f31e923fe2 262 return (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT));
Pawel Zarembski 0:01f31e923fe2 263 }
Pawel Zarembski 0:01f31e923fe2 264
Pawel Zarembski 0:01f31e923fe2 265 /** SWDIO I/O pin: Set Output (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 266 \param bit Output value for the SWDIO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 267 */
Pawel Zarembski 0:01f31e923fe2 268 __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 269 {
Pawel Zarembski 0:01f31e923fe2 270 BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit;
Pawel Zarembski 0:01f31e923fe2 271 }
Pawel Zarembski 0:01f31e923fe2 272
Pawel Zarembski 0:01f31e923fe2 273 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 274 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
Pawel Zarembski 0:01f31e923fe2 275 called prior \ref PIN_SWDIO_OUT function calls.
Pawel Zarembski 0:01f31e923fe2 276 */
Pawel Zarembski 0:01f31e923fe2 277 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
Pawel Zarembski 0:01f31e923fe2 278 {
Pawel Zarembski 0:01f31e923fe2 279 PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT;
Pawel Zarembski 0:01f31e923fe2 280 }
Pawel Zarembski 0:01f31e923fe2 281
Pawel Zarembski 0:01f31e923fe2 282 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Pawel Zarembski 0:01f31e923fe2 283 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
Pawel Zarembski 0:01f31e923fe2 284 called prior \ref PIN_SWDIO_IN function calls.
Pawel Zarembski 0:01f31e923fe2 285 */
Pawel Zarembski 0:01f31e923fe2 286 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
Pawel Zarembski 0:01f31e923fe2 287 {
Pawel Zarembski 0:01f31e923fe2 288 PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT;
Pawel Zarembski 0:01f31e923fe2 289 }
Pawel Zarembski 0:01f31e923fe2 290
Pawel Zarembski 0:01f31e923fe2 291
Pawel Zarembski 0:01f31e923fe2 292 // TDI Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 293
Pawel Zarembski 0:01f31e923fe2 294 /** TDI I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 295 \return Current status of the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 296 */
Pawel Zarembski 0:01f31e923fe2 297 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
Pawel Zarembski 0:01f31e923fe2 298 {
Pawel Zarembski 0:01f31e923fe2 299 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 300 }
Pawel Zarembski 0:01f31e923fe2 301
Pawel Zarembski 0:01f31e923fe2 302 /** TDI I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 303 \param bit Output value for the TDI DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 304 */
Pawel Zarembski 0:01f31e923fe2 305 __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 306 {
Pawel Zarembski 0:01f31e923fe2 307 ; // Not available
Pawel Zarembski 0:01f31e923fe2 308 }
Pawel Zarembski 0:01f31e923fe2 309
Pawel Zarembski 0:01f31e923fe2 310
Pawel Zarembski 0:01f31e923fe2 311 // TDO Pin I/O ---------------------------------------------
Pawel Zarembski 0:01f31e923fe2 312
Pawel Zarembski 0:01f31e923fe2 313 /** TDO I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 314 \return Current status of the TDO DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 315 */
Pawel Zarembski 0:01f31e923fe2 316 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
Pawel Zarembski 0:01f31e923fe2 317 {
Pawel Zarembski 0:01f31e923fe2 318 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 319 }
Pawel Zarembski 0:01f31e923fe2 320
Pawel Zarembski 0:01f31e923fe2 321
Pawel Zarembski 0:01f31e923fe2 322 // nTRST Pin I/O -------------------------------------------
Pawel Zarembski 0:01f31e923fe2 323
Pawel Zarembski 0:01f31e923fe2 324 /** nTRST I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 325 \return Current status of the nTRST DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 326 */
Pawel Zarembski 0:01f31e923fe2 327 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
Pawel Zarembski 0:01f31e923fe2 328 {
Pawel Zarembski 0:01f31e923fe2 329 return (0); // Not available
Pawel Zarembski 0:01f31e923fe2 330 }
Pawel Zarembski 0:01f31e923fe2 331
Pawel Zarembski 0:01f31e923fe2 332 /** nTRST I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 333 \param bit JTAG TRST Test Reset pin status:
Pawel Zarembski 0:01f31e923fe2 334 - 0: issue a JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 335 - 1: release JTAG TRST Test Reset.
Pawel Zarembski 0:01f31e923fe2 336 */
Pawel Zarembski 0:01f31e923fe2 337 __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 338 {
Pawel Zarembski 0:01f31e923fe2 339 ; // Not available
Pawel Zarembski 0:01f31e923fe2 340 }
Pawel Zarembski 0:01f31e923fe2 341
Pawel Zarembski 0:01f31e923fe2 342 // nRESET Pin I/O------------------------------------------
Pawel Zarembski 0:01f31e923fe2 343
Pawel Zarembski 0:01f31e923fe2 344 /** nRESET I/O pin: Get Input.
Pawel Zarembski 0:01f31e923fe2 345 \return Current status of the nRESET DAP hardware I/O pin.
Pawel Zarembski 0:01f31e923fe2 346 */
Pawel Zarembski 0:01f31e923fe2 347 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
Pawel Zarembski 0:01f31e923fe2 348 {
Pawel Zarembski 0:01f31e923fe2 349 return ((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1);
Pawel Zarembski 0:01f31e923fe2 350 }
Pawel Zarembski 0:01f31e923fe2 351
Pawel Zarembski 0:01f31e923fe2 352 /** nRESET I/O pin: Set Output.
Pawel Zarembski 0:01f31e923fe2 353 \param bit target device hardware reset pin status:
Pawel Zarembski 0:01f31e923fe2 354 - 0: issue a device hardware reset.
Pawel Zarembski 0:01f31e923fe2 355 - 1: release device hardware reset.
Pawel Zarembski 0:01f31e923fe2 356 */
Pawel Zarembski 0:01f31e923fe2 357 __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 358 {
Pawel Zarembski 0:01f31e923fe2 359 BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit;
Pawel Zarembski 0:01f31e923fe2 360 }
Pawel Zarembski 0:01f31e923fe2 361
Pawel Zarembski 0:01f31e923fe2 362 ///@}
Pawel Zarembski 0:01f31e923fe2 363
Pawel Zarembski 0:01f31e923fe2 364
Pawel Zarembski 0:01f31e923fe2 365 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 366 /**
Pawel Zarembski 0:01f31e923fe2 367 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
Pawel Zarembski 0:01f31e923fe2 368 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 369 @{
Pawel Zarembski 0:01f31e923fe2 370
Pawel Zarembski 0:01f31e923fe2 371 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 372
Pawel Zarembski 0:01f31e923fe2 373 It is recommended to provide the following LEDs for status indication:
Pawel Zarembski 0:01f31e923fe2 374 - Connect LED: is active when the DAP hardware is connected to a debugger.
Pawel Zarembski 0:01f31e923fe2 375 - Running LED: is active when the debugger has put the target device into running state.
Pawel Zarembski 0:01f31e923fe2 376 */
Pawel Zarembski 0:01f31e923fe2 377
Pawel Zarembski 0:01f31e923fe2 378 /** Debug Unit: Set status of Connected LED.
Pawel Zarembski 0:01f31e923fe2 379 \param bit status of the Connect LED.
Pawel Zarembski 0:01f31e923fe2 380 - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 381 - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
Pawel Zarembski 0:01f31e923fe2 382 */
Pawel Zarembski 0:01f31e923fe2 383 static inline void LED_CONNECTED_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 384 {
Pawel Zarembski 0:01f31e923fe2 385 BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit;
Pawel Zarembski 0:01f31e923fe2 386 }
Pawel Zarembski 0:01f31e923fe2 387
Pawel Zarembski 0:01f31e923fe2 388 /** Debug Unit: Set status Target Running LED.
Pawel Zarembski 0:01f31e923fe2 389 \param bit status of the Target Running LED.
Pawel Zarembski 0:01f31e923fe2 390 - 1: Target Running LED ON: program execution in target started.
Pawel Zarembski 0:01f31e923fe2 391 - 0: Target Running LED OFF: program execution in target stopped.
Pawel Zarembski 0:01f31e923fe2 392 */
Pawel Zarembski 0:01f31e923fe2 393 static inline void LED_RUNNING_OUT(uint32_t bit)
Pawel Zarembski 0:01f31e923fe2 394 {
Pawel Zarembski 0:01f31e923fe2 395 ; // Not available
Pawel Zarembski 0:01f31e923fe2 396 }
Pawel Zarembski 0:01f31e923fe2 397
Pawel Zarembski 0:01f31e923fe2 398 ///@}
Pawel Zarembski 0:01f31e923fe2 399
Pawel Zarembski 0:01f31e923fe2 400
Pawel Zarembski 0:01f31e923fe2 401 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 402 /**
Pawel Zarembski 0:01f31e923fe2 403 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
Pawel Zarembski 0:01f31e923fe2 404 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 405 @{
Pawel Zarembski 0:01f31e923fe2 406 Access function for Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 407
Pawel Zarembski 0:01f31e923fe2 408 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
Pawel Zarembski 0:01f31e923fe2 409 default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
Pawel Zarembski 0:01f31e923fe2 410
Pawel Zarembski 0:01f31e923fe2 411 */
Pawel Zarembski 0:01f31e923fe2 412
Pawel Zarembski 0:01f31e923fe2 413 /** Get timestamp of Test Domain Timer.
Pawel Zarembski 0:01f31e923fe2 414 \return Current timestamp value.
Pawel Zarembski 0:01f31e923fe2 415 */
Pawel Zarembski 0:01f31e923fe2 416 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
Pawel Zarembski 0:01f31e923fe2 417 return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
Pawel Zarembski 0:01f31e923fe2 418 }
Pawel Zarembski 0:01f31e923fe2 419
Pawel Zarembski 0:01f31e923fe2 420 ///@}
Pawel Zarembski 0:01f31e923fe2 421
Pawel Zarembski 0:01f31e923fe2 422
Pawel Zarembski 0:01f31e923fe2 423 //**************************************************************************************************
Pawel Zarembski 0:01f31e923fe2 424 /**
Pawel Zarembski 0:01f31e923fe2 425 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
Pawel Zarembski 0:01f31e923fe2 426 \ingroup DAP_ConfigIO_gr
Pawel Zarembski 0:01f31e923fe2 427 @{
Pawel Zarembski 0:01f31e923fe2 428
Pawel Zarembski 0:01f31e923fe2 429 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
Pawel Zarembski 0:01f31e923fe2 430 */
Pawel Zarembski 0:01f31e923fe2 431
Pawel Zarembski 0:01f31e923fe2 432 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
Pawel Zarembski 0:01f31e923fe2 433 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Pawel Zarembski 0:01f31e923fe2 434 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
Pawel Zarembski 0:01f31e923fe2 435 - I/O clock system enabled.
Pawel Zarembski 0:01f31e923fe2 436 - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
Pawel Zarembski 0:01f31e923fe2 437 - for nTRST, nRESET a weak pull-up (if available) is enabled.
Pawel Zarembski 0:01f31e923fe2 438 - LED output pins are enabled and LEDs are turned off.
Pawel Zarembski 0:01f31e923fe2 439 */
Pawel Zarembski 0:01f31e923fe2 440 static inline void DAP_SETUP(void)
Pawel Zarembski 0:01f31e923fe2 441 {
Pawel Zarembski 0:01f31e923fe2 442 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */
Pawel Zarembski 0:01f31e923fe2 443 SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */
Pawel Zarembski 0:01f31e923fe2 444 SIM_SCGC5_PORTC_MASK | /* Enable Port C Clock */
Pawel Zarembski 0:01f31e923fe2 445 SIM_SCGC5_PORTD_MASK; /* Enable Port D Clock */
Pawel Zarembski 0:01f31e923fe2 446 /* Configure I/O pin SWCLK */
Pawel Zarembski 0:01f31e923fe2 447 PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 448 PORT_PCR_DSE_MASK; /* High drive strength */
Pawel Zarembski 0:01f31e923fe2 449 PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; /* High level */
Pawel Zarembski 0:01f31e923fe2 450 PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT; /* Output */
Pawel Zarembski 0:01f31e923fe2 451 /* Configure I/O pin SWDIO_OUT */
Pawel Zarembski 0:01f31e923fe2 452 PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 453 PORT_PCR_DSE_MASK; /* High drive strength */
Pawel Zarembski 0:01f31e923fe2 454 PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; /* High level */
Pawel Zarembski 0:01f31e923fe2 455 PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT; /* Output */
Pawel Zarembski 0:01f31e923fe2 456 /* Configure I/O pin SWDIO_IN */
Pawel Zarembski 0:01f31e923fe2 457 PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 458 PORT_PCR_PE_MASK | /* Pull enable */
Pawel Zarembski 0:01f31e923fe2 459 PORT_PCR_PS_MASK; /* Pull-up */
Pawel Zarembski 0:01f31e923fe2 460 PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT); /* Input */
Pawel Zarembski 0:01f31e923fe2 461 /* Configure I/O pin SWDIO_OE */
Pawel Zarembski 0:01f31e923fe2 462 PIN_SWDIO_OE_PORT->PCR[PIN_SWDIO_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 463 PORT_PCR_DSE_MASK; /* High drive strength */
Pawel Zarembski 0:01f31e923fe2 464 PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; /* Low level */
Pawel Zarembski 0:01f31e923fe2 465 PIN_SWDIO_OE_GPIO->PDDR |= 1 << PIN_SWDIO_OE_BIT; /* Output */
Pawel Zarembski 0:01f31e923fe2 466 /* Configure I/O pin SWD_OE */
Pawel Zarembski 0:01f31e923fe2 467 PIN_SWD_OE_PORT->PCR[PIN_SWD_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 468 PORT_PCR_DSE_MASK; /* High drive strength */
Pawel Zarembski 0:01f31e923fe2 469 PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; /* Low level */
Pawel Zarembski 0:01f31e923fe2 470 PIN_SWD_OE_GPIO->PDDR |= 1 << PIN_SWD_OE_BIT; /* Output */
Pawel Zarembski 0:01f31e923fe2 471 /* Configure I/O pin nRESET */
Pawel Zarembski 0:01f31e923fe2 472 PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 473 PORT_PCR_PE_MASK | /* Pull enable */
Pawel Zarembski 0:01f31e923fe2 474 PORT_PCR_PS_MASK | /* Pull-up */
Pawel Zarembski 0:01f31e923fe2 475 PORT_PCR_ODE_MASK; /* Open-drain */
Pawel Zarembski 0:01f31e923fe2 476 PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; /* High level */
Pawel Zarembski 0:01f31e923fe2 477 PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT); /* Input */
Pawel Zarembski 0:01f31e923fe2 478 // Configure I/O pin LVLRST_EN
Pawel Zarembski 0:01f31e923fe2 479 // The nRESET level translator is enabled by default. The translator is auto-
Pawel Zarembski 0:01f31e923fe2 480 // direction sensing. So as long as we don't drive nRESET from our side, we won't
Pawel Zarembski 0:01f31e923fe2 481 // interfere with another debug probe connected to the target SWD header.
Pawel Zarembski 0:01f31e923fe2 482 PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 483 PORT_PCR_ODE_MASK; /* Open-drain */
Pawel Zarembski 0:01f31e923fe2 484 PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN; /* High level */
Pawel Zarembski 0:01f31e923fe2 485 PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN; /* Output */
Pawel Zarembski 0:01f31e923fe2 486 /* Configure LED */
Pawel Zarembski 0:01f31e923fe2 487 LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 488 PORT_PCR_ODE_MASK; /* Open-drain */
Pawel Zarembski 0:01f31e923fe2 489 LED_CONNECTED_GPIO->PCOR = 1 << LED_CONNECTED_BIT; /* Turned on */
Pawel Zarembski 0:01f31e923fe2 490 LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT; /* Output */
Pawel Zarembski 0:01f31e923fe2 491 }
Pawel Zarembski 0:01f31e923fe2 492
Pawel Zarembski 0:01f31e923fe2 493 /** Reset Target Device with custom specific I/O pin or command sequence.
Pawel Zarembski 0:01f31e923fe2 494 This function allows the optional implementation of a device specific reset sequence.
Pawel Zarembski 0:01f31e923fe2 495 It is called when the command \ref DAP_ResetTarget and is for example required
Pawel Zarembski 0:01f31e923fe2 496 when a device needs a time-critical unlock sequence that enables the debug port.
Pawel Zarembski 0:01f31e923fe2 497 \return 0 = no device specific reset sequence is implemented.\n
Pawel Zarembski 0:01f31e923fe2 498 1 = a device specific reset sequence is implemented.
Pawel Zarembski 0:01f31e923fe2 499 */
Pawel Zarembski 0:01f31e923fe2 500 static inline uint32_t RESET_TARGET(void)
Pawel Zarembski 0:01f31e923fe2 501 {
Pawel Zarembski 0:01f31e923fe2 502 return (0); // change to '1' when a device reset sequence is implemented
Pawel Zarembski 0:01f31e923fe2 503 }
Pawel Zarembski 0:01f31e923fe2 504
Pawel Zarembski 0:01f31e923fe2 505 ///@}
Pawel Zarembski 0:01f31e923fe2 506
Pawel Zarembski 0:01f31e923fe2 507
Pawel Zarembski 0:01f31e923fe2 508 #endif /* __DAP_CONFIG_H__ */